Display panel and electronic device
By using pins with unequal area design and multi-layer metal interconnect structure, the problem of insufficient pad space in high-resolution display panels is solved, achieving stable signal transmission and efficient resource utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI VISIONOX TECH CO LTD
- Filing Date
- 2023-06-29
- Publication Date
- 2026-05-29
AI Technical Summary
In high-resolution display panels, the increased number of pads in the flexible circuit board bonding area leads to insufficient space, affecting signal transmission stability and wasting resources.
The pins are designed with unequal area, with the area of the first target pin being larger than that of the second target pin. Combined with the interconnect structure of multiple metal layers and insulating layers, the signal transmission path is optimized.
Stable signal transmission was achieved, resistance was reduced, space resources were saved, and resource waste and abnormal analysis were avoided.
Smart Images
Figure CN116863819B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of display technology, specifically relating to a display panel and an electronic device. Background Technology
[0002] In recent years, display products have been developed towards higher resolutions. However, the higher the resolution, the more pads (also known as pins) are required in the flexible circuit board on panel (FOP). This results in an increase in the space occupied by the pads in the FOP, leading to insufficient space for pad arrangement.
[0003] Therefore, it is urgent to adjust the space required by the pads in the bonding area of the flexible circuit board while ensuring the normal operation of the display panel. Summary of the Invention
[0004] This application provides a display panel and an electronic device that can ensure stable signal transmission.
[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a display panel, which includes a substrate, a plurality of first pins, a plurality of second pins, and a plurality of connecting lines; wherein, the plurality of first pins are disposed on a first side of the substrate, the plurality of first pins are arranged side by side, and the first pins are used to connect to a flexible circuit board; the plurality of second pins are disposed on the first side of the substrate, the plurality of second pins are arranged side by side, and the second pins are used to connect to a driver chip; the plurality of connecting lines are disposed on the first side of the substrate, one end of the connecting line is electrically connected to a first pin, and the other end is electrically connected to a second pin; wherein, the plurality of first pins include a first target pin and a second target pin, and the area of the first target pin is larger than the area of the second target pin.
[0006] The plurality of first pins further includes a third target pin, the third target pin being located between the first target pin and the second target pin, and the area of the third target pin being equal to the area of the second target pin; wherein the distance between the first target pin and the third target pin is greater than the distance between the third target pin and the second target pin.
[0007] The second pin electrically connected to the first target pin is defined as the fourth target pin, and the second pin electrically connected to the second target pin is defined as the fifth target pin, wherein the area of the fourth target pin is larger than the area of the fifth target pin.
[0008] Wherein, the connecting line electrically connected to the first target pin is defined as the first target connecting line, and the connecting line electrically connected to the second target pin is defined as the second target connecting line; wherein, the width of the first target connecting line is greater than the width of the second target connecting line.
[0009] Wherein, the first target pin is electrically connected to multiple second pins simultaneously through a single connection line; and / or, the second target pin is electrically connected to multiple second pins simultaneously through a single connection line.
[0010] The connecting line comprises a plurality of metal layers stacked sequentially on the substrate, with an insulating layer disposed between any two adjacent metal layers, and each metal layer is electrically connected to the first pin and the second pin; preferably, the thickness of the metal layers in the connecting line is in the range of 2500A-10000A; preferably, the connecting line comprises at least three metal layers.
[0011] The plurality of metal layers include a first metal layer, which includes multiple sub-metal layers stacked sequentially; preferably, the multiple sub-metal layers include a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer; preferably, the first sub-metal layer and the third sub-metal layer are made of titanium, and the second sub-metal layer is made of aluminum.
[0012] Wherein, the width of the first target pin is in the range of 50-110μm, and / or the width of the second target pin is in the range of 25-55μm, and / or the spacing between any two adjacent first pins is in the range of 25-70μm;
[0013] The display panel further includes: a third pin, wherein a plurality of the third pins are arranged side by side, and the third pins are used to connect to the test device during screen testing; wherein the first pin and the third pins are arranged in the same row.
[0014] Wherein, the width of the first target pin is greater than the width of the second target pin; preferably, the length of the first target pin is equal to the length of the second target pin; preferably, the connecting line electrically connected to the first target pin is defined as the first target connecting line, and the connecting line electrically connected to the second target pin is defined as the second target connecting line, the width of the first target connecting line is greater than the width of the second target connecting line; the first target connecting line includes a plurality of metal layers sequentially stacked on the substrate, an insulating layer is disposed between any two adjacent metal layers, and any metal layer is electrically connected to the first target pin; at the same time, the second pin electrically connected to the first target pin is defined as the fourth target pin, and the second pin electrically connected to the second target pin is defined as the fifth target pin, the area of the fourth target pin is greater than the area of the fifth target pin.
[0015] Another technical solution adopted in this application is to provide an electronic device that includes the display panel described in any of the above embodiments.
[0016] The beneficial effects of this application are: by designing multiple first pins with unequal areas, and setting the area of the first target pin to be larger than that of the second target pin, the resistance of the signal transmitted by the first target pin can meet the usage requirements, thereby enabling multiple first pins to transmit different signals with different resistance requirements at the same time, thus meeting various transmission needs. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:
[0018] Figure 1 This is a top view of an embodiment in which the first pin and the second pin are connected;
[0019] Figure 2 This is a side view structural diagram of an embodiment of the display panel in this application;
[0020] Figure 3 This is a top view of one embodiment of the display panel in this application;
[0021] Figure 4 This is a top view of another embodiment in which the first pin and the second pin are connected;
[0022] Figure 5 This is a side view of an embodiment in which the first pin and the second pin are connected.
[0023] Figure 6 This is a side view of another embodiment in which the first pin and the second pin are connected;
[0024] Figure 7 This is a top view of an embodiment of the first and third pin arrangements in this application.
[0025] Explanation of reference numerals in the attached figures: 1 First pin; 11 First target pin; 12 Second target pin; 13 Third target pin; 2 Second pin; 24 Fourth target pin; 25 Fifth target pin; 3 Connecting line; 31 First target connecting line; 32 Second target connecting line; 4 Signal line; 5 Driver chip; 6 Flexible circuit board; 8 Pixel circuit; 9 Substrate; 40 Metal layer; 41 First metal layer; 42 Second metal layer; 43 Third metal layer; 44 Insulating layer; 7 Third pin. Detailed Implementation
[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0027] The inventors discovered that, due to the size limitations of the display panel, the space for the CT (Computed Tolerance) pads and FOP (Frame Opening) pads used in the conventional design for some products is insufficient. This necessitates extending the CT pads beyond the screen's cutting line and cutting them off after the CT test on the screen segment. This not only wastes significant resources and increases costs but also affects the resolution of module segment anomalies, making it impossible to confirm the screen's display status upon module arrival via CT testing. Therefore, the overall width of the FOP needs to be reduced to meet the design requirements of high-resolution products.
[0028] However, reducing the overall width of the FOP (Flexible Display Panel) causes the resistance in the connecting cables to exceed the specifications. Therefore, improvements to the display panel are urgently needed to reduce the resistance in the connecting cables.
[0029] Please see Figure 1 , Figure 2 and Figure 3This application provides a display panel, which includes a substrate 9, a plurality of first pins 1, a plurality of second pins 2, and a plurality of connecting lines 3; wherein, the plurality of first pins 1 are disposed on a first side of the substrate 9, the plurality of first pins 1 are arranged side by side, and the first pins 1 are used to connect to a flexible circuit board 6; the plurality of second pins 2 are disposed on the first side of the substrate 9, the plurality of second pins 2 are arranged side by side, and the second pins 2 are used to connect to a driver chip 5; the plurality of connecting lines 3 are disposed on the first side of the substrate 9, one end of the connecting line 3 is electrically connected to a first pin 1, and the other end is electrically connected to a second pin 2; wherein, the plurality of first pins 1 include a first target pin 11 and a second target pin 12, the area of the first target pin 11 being larger than the area of the second target pin 12.
[0030] In one embodiment, the first target pin 11 is used to transmit the digital power signal DVDD or the ground signal DVSS corresponding to DVDD, and the second target pin 12 is used to transmit the reset voltage signal VREF, the ground signal VSSB corresponding to the communication protocol signal, the ground signal AVSS corresponding to the analog power supply, or the communication protocol signal VDDI.
[0031] Specifically, multiple first pins 1 and multiple second pins 2 are arranged side by side. The first pins 1 are used to bond the flexible circuit board 6, and the second pins 2 are used to bond the driver chip 5. One end of the connecting line 3 is connected to one end of the first pin 1, and the other end is connected to one end of the second pin 2. The second pin 2 is used to bond the driver chip 5. In one embodiment, the electrical signal is transmitted from the outside of the display panel (for example, the outside can be the motherboard of the electronic device, such as an external power supply) to the flexible circuit board 6. The flexible circuit board 6 transmits the signal to the driver chip 5 through the connecting line 3. The driver chip 5 then transmits the signal to the inside of the display panel to realize the display of the image in the AA area (display area) of the display panel.
[0032] The substrate 9 can be a rigid substrate or a flexible substrate, and it provides support for the first pin 1 and the second pin 2. In the above scheme, the multiple first pins 1 are designed with unequal areas, and the area of the first target pin 11 is set to be larger than the area of the second target pin 12. This allows the signal resistance transmitted by the first target pin 11 to meet the usage requirements, and thus allows multiple first pins 1 to simultaneously transmit different signals with different resistance requirements, meeting various transmission needs and ensuring stable signal transmission.
[0033] In the prior art, the areas of multiple first pins 1 are all equal. When the areas of multiple first pins 1 are equal and less than a certain threshold, the resistance of the signal transmitted by a certain first pin 1 may exceed the standard and exceed the allowable range of the driver chip. In the solution of this application, the multiple first pins 1 are designed with unequal areas, which allows multiple first pins 1 to transmit different signals with different resistance requirements at the same time, meet the transmission requirements, and ensure stable signal transmission.
[0034] In order to ensure that the area of the first target pin 11 is greater than the area of the second target pin 12, in one embodiment, the width of the first target pin 11 is set to be greater than the width of the second target pin 12. In this case, the length of the first target pin 11 can be equal to or greater than the length of the second target pin 12. For the sake of the regularity of the arrangement of multiple first pins 11, it is preferable that the length of the first target pin 11 is equal to the length of the second target pin 12. Of course, in other embodiments, the width of the first target pin 11 can also be equal to the width of the second target pin 12, but the length of the first target pin 11 is greater than the length of the second target pin 12. In short, as long as the area of the first target pin 11 is greater than the area of the second target pin 12, it is acceptable.
[0035] Please see Figure 4 The plurality of first pins 1 further include a third target pin 13, which is located between the first target pin 11 and the second target pin 12, and the area of the third target pin 13 is equal to the area of the second target pin 12. The distance between the first target pin 11 and the third target pin 13 is greater than the distance between the third target pin 13 and the second target pin 12. This configuration reduces the difficulty of fabrication and avoids short circuits between the first target pin 11 and the third target pin 13. Simultaneously, it satisfies the clearance requirements for normal operation between the connecting line 3 connected to the first target pin 11 and the connecting line 3 connected to the third target pin 13, ensuring the normal operation of the connecting line 3.
[0036] Of course, in other embodiments, the distance between the first target pin 11 and the third target pin 13, and the distance between the third target pin 13 and the second target pin 12, can also be the same, and there is no limitation here.
[0037] Please continue reading Figure 4The second pin 2 electrically connected to the first target pin 11 is defined as the fourth target pin 24, and the second pin 2 electrically connected to the second target pin 12 is defined as the fifth target pin 25. The area of the fourth target pin 24 is larger than the area of the fifth target pin 25. Specifically, because the area of the fourth target pin 24 is larger than the area of the fifth target pin 25, the resistance of the fourth target pin 24 is less than the resistance of the fifth target pin 25. This further reduces the resistance of the signal transmitted between the first target pin 11 and the fourth target pin 24, thus meeting the transmission requirements.
[0038] Of course, in other embodiments, the area of the fourth target pin 24 can also be equal to the area of the fifth target pin 25.
[0039] Please continue reading Figure 4 The connecting line 3 electrically connected to the first target pin 11 is defined as the first target connecting line 31, and the connecting line 3 electrically connected to the second target pin 12 is defined as the second target connecting line 32; wherein, the width of the first target connecting line 31 is greater than the width of the second target connecting line 32. Specifically, the width of the first target connecting line 31 is greater than the width of the second target connecting line 32, so that the resistance of the first target connecting line 31 is less than the resistance of the second target connecting line 32, which can further reduce the resistance of the signal transmitted between the first target pin 11 and the fourth target pin 24, thereby meeting the transmission requirements.
[0040] Of course, in other embodiments, the width of the first target connecting line 31 may also be equal to the width of the second target connecting line 32.
[0041] In one embodiment, a first target pin 11 is electrically connected to multiple second pins 2 simultaneously via a connecting line 3. Similarly, a second target pin 12 is electrically connected to multiple second pins 2 simultaneously via a connecting line 3.
[0042] Specifically, when multiple adjacent second pins 2 transmit the same signal, the first target pin 11 is electrically connected to the multiple adjacent second pins 2 simultaneously through a connecting line 3. This enables the same signal in the second pins 2 to be transmitted to the first target pin 11 through the same connecting line 3, thereby reducing the number of connecting lines 3 and reducing the manufacturing difficulty. Similarly, the second target pin 12 is electrically connected to multiple adjacent second pins 2 simultaneously through a connecting line 3. This enables the same signal in the second pins 2 to be transmitted to the second target pin 12 through the same connecting line 3, thereby reducing the number of connecting lines 3 and reducing the manufacturing difficulty.
[0043] Please see Figure 5The connecting line 3 includes a plurality of metal layers 40 stacked sequentially on the substrate 9, an insulating layer 44 is provided between any two adjacent metal layers 40, and any metal layer 40 is electrically connected to the first pin 1 and the second pin 2.
[0044] Specifically, the connecting line 3 includes multiple metal layers 40, which are made of metal material and are capable of conducting electricity and transmitting electrical signals. The insulating layer 44 located between two adjacent metal layers 40 can prevent short circuits between the two adjacent metal layers 40.
[0045] Any metal layer 40 is electrically connected to the first pin 1 and the second pin 2, which is equivalent to multiple metal layers 40 connected in parallel. This reduces the resistance of the connecting line 3 and makes the resistance in the connecting line 3 meet the usage requirements.
[0046] In one embodiment, the thickness of the metal layer 40 is in the range of 2500 Å to 10000 Å. For example, the thickness of the metal layer 40 is 2500 Å, 5000 Å or 10000 Å, which is convenient for preparation and meets the operational requirements of the connecting wire 3.
[0047] In one embodiment, the connecting line 3 includes at least three metal layers 40, that is, the number of metal layers 40 in the connecting line 3 is at least three, for example, three, four or more.
[0048] Continue reading Figure 5 as well as Figure 6 In one embodiment, the connecting line 3 includes three metal layers 40, and for ease of explanation, these three metal layers 40 are respectively defined as a first metal layer 41, a second metal layer 42, and a third metal layer 43. The thicknesses of the first metal layer 41, the second metal layer 42, and the third metal layer 43 can be equal or unequal, and there is no specific limitation. For example, in... Figure 5 In this embodiment, the first metal layer 41, the second metal layer 42, and the third metal layer 43 have equal thicknesses. For example, in... Figure 6 In this embodiment, the thickness of the first metal layer 41 is equal to the thickness of the second metal layer 42, and the thickness of the third metal layer 43 is greater than the thicknesses of the first metal layer 41 and the second metal layer 42.
[0049] In one embodiment, the first metal layer 41 comprises multiple sub-metal layers stacked sequentially; that is, the first metal layer 41 is a stacked structure composed of multiple sub-metal layers. Of course, in other embodiments, the first metal layer 41 may also be a single-layer structure.
[0050] In one embodiment, the first metal layer 41 comprises multiple sub-metal layers, including a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer; that is, the first metal layer 41 includes three sub-metal layers. Of course, in other embodiments, the first metal layer 41 may include four, five, or more sub-metal layers. In one embodiment, the first and third sub-metal layers are made of titanium, and the second sub-metal layer is made of aluminum. In this case, the first metal layer 41 is a titanium-aluminum-titanium stacked structure.
[0051] The structures of the second metal layer 42 and the third metal layer 43 may be the same as or different from the structure of the first metal layer 41, and no restrictions are imposed here.
[0052] In one embodiment, the width of the first target pin 11 is in the range of 50-110μm. For example, the width of the first target pin 11 can be 50μm, 60μm, 70μm, 80μm, 90μm, 100μm or 110μm.
[0053] In one embodiment, the width of the second target pin 12 is in the range of 25-55μm. For example, the width of the second target pin 12 can be 25μm, 30μm, 35μm, 40μm, 45μm, 50μm or 55μm.
[0054] In one embodiment, the spacing between any two adjacent first pins 1 ranges from 25 to 70 μm. For example, the spacing between any two adjacent first pins 1 can be 25, 30 μm, 40 μm, 50 μm, 60 μm, or 70 μm.
[0055] In the above design, the width design of the first target pin 11 and the second target pin 12 ensures their normal operation, while also ensuring that the resistance in the connecting line 3 meets the usage specifications. The spacing design between adjacent first pins 1 enables the normal operation of the first pin 1.
[0056] Please see Figure 7 The display panel further includes a third pin 7, with multiple third pins 7 arranged side by side. The third pins 7 are used to connect to the test equipment during screen testing; wherein, the first pin 1 and the third pin 7 are arranged in the same row. Specifically, this application sets the multiple first pins 1 with unequal widths. While meeting the requirements of signal transmission, the width of the first pins 1 can be reduced, thereby freeing up space for multiple third pins 7 to be arranged in the same row with multiple first pins 1. There is no need to place the third pins 7 outside the cut line in the display panel, which saves space and avoids resource waste.
[0057] This application also provides an electronic device that includes the display panel described in any of the above embodiments. Therefore, this electronic device possesses all the features and advantages of the aforementioned display panel. Specifically, the electronic device includes mobile or fixed terminals such as electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, smart bracelets, smartwatches, supercomputers, and navigators.
[0058] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A display panel, characterized in that, include: substrate; Multiple first pins are disposed on a first side of the substrate, and the multiple first pins are arranged side by side. The first pins are used to connect to the flexible circuit board. Multiple second pins are disposed on the first side of the substrate, and the multiple second pins are arranged side by side. The second pins are used to connect to the driver chip. Multiple connecting lines are disposed on the first side of the substrate, one end of each connecting line is electrically connected to the first pin, and the other end is electrically connected to the second pin. The plurality of first pins include a first target pin and a second target pin, wherein the area of the first target pin is larger than the area of the second target pin; The second pin electrically connected to the first target pin is defined as the fourth target pin, and the second pin electrically connected to the second target pin is defined as the fifth target pin, wherein the area of the fourth target pin is larger than the area of the fifth target pin; The connection line electrically connected to the first target pin is defined as the first target connection line, and the connection line electrically connected to the second target pin is defined as the second target connection line; wherein, the width of the first target connection line is greater than the width of the second target connection line, and wherein, the resistance value of the first overall structure formed by the first target pin, the first target connection line, and the fourth target pin is less than the resistance value of the second overall structure formed by the second target pin, the second target connection line, and the fifth target pin; The display panel further includes: a third pin, wherein a plurality of the third pins are arranged side by side, and the third pins are used to connect to the test device during screen testing; wherein the first pin and the third pins are arranged in the same row; The plurality of first pins further includes a third target pin, the third target pin being located between the first target pin and the second target pin, and the area of the third target pin being equal to the area of the second target pin; wherein the distance between the first target pin and the third target pin is greater than the distance between the third target pin and the second target pin.
2. The display panel according to claim 1, characterized in that, The first target pin is electrically connected to multiple second pins simultaneously via a single connection line; and / or, the second target pin is electrically connected to multiple second pins simultaneously via a single connection line.
3. The display panel according to claim 1, characterized in that, The connection line includes a plurality of metal layers stacked sequentially on the substrate, with an insulating layer disposed between any two adjacent metal layers, and each metal layer is electrically connected to the first pin and the second pin.
4. The display panel according to claim 3, characterized in that, The thickness of the metal layer in the connecting line ranges from 2500A to 10000A.
5. The display panel according to claim 3, characterized in that, The connecting line includes at least three metal layers.
6. The display panel according to claim 3, characterized in that, The plurality of metal layers include a first metal layer, which comprises multiple sub-metal layers stacked sequentially.
7. The display panel according to claim 6, characterized in that, The multilayer sub-metal layer includes a first sub-metal layer, a second sub-metal layer, and a third sub-metal layer.
8. The display panel according to claim 7, characterized in that, The first and third sub-metal layers are made of titanium, and the second sub-metal layer is made of aluminum.
9. The display panel according to claim 1, characterized in that, The width of the first target pin is 50-110 μm, and / or the width of the second target pin is 25-55 μm, and / or the spacing between any two adjacent first pins is 25-70 μm.
10. The display panel according to claim 1, characterized in that, The width of the first target pin is greater than the width of the second target pin.
11. The display panel according to claim 10, characterized in that, The length of the first target pin is equal to the length of the second target pin.
12. The display panel according to claim 1, characterized in that, The connection line electrically connected to the first target pin is defined as the first target connection line, and the connection line electrically connected to the second target pin is defined as the second target connection line, wherein the width of the first target connection line is greater than the width of the second target connection line; The first target connection line includes a plurality of metal layers stacked sequentially on the substrate, an insulating layer is disposed between any two adjacent metal layers, and any metal layer is electrically connected to the first target pin. Meanwhile, the second pin electrically connected to the first target pin is defined as the fourth target pin, and the second pin electrically connected to the second target pin is defined as the fifth target pin, wherein the area of the fourth target pin is larger than the area of the fifth target pin.
13. An electronic device, characterized in that, The display panel includes any one of claims 1-12.