A LDPC decoding device based on hybrid computing power

Abstract

The present invention discloses an LDPC decoding device based on hybrid computing power, which relates to the field of communications. It includes a control unit, a decoding preprocessing unit, a logic computing unit, an iterative storage unit, a storage computing unit and a decoding output interface unit. The logic computing unit and the storage computing unit mainly complete the core processing function of the decoding data. The iterative storage unit mainly completes the conversion and storage of data formats between different computing units during the decoding process. The control unit completes the scheduling and management of the entire decoding process. The decoding preprocessing unit mainly completes the preprocessing of the data to be decoded. The decoding output interface unit mainly completes the output adaptation of the decoded data. Compared with the traditional LDPC decoder, the present invention has the advantages of short decoding delay, low resource consumption, rate adaptation, etc.

Description

Technical Field

[0001] The invention relates to an LDPC decoding device based on hybrid computing power in the communication field, and is particularly suitable for real-time service processing in satellite communications and realization of a high-speed LDPC decoder under conditions of limited satellite resources. Background Art

[0002] In satellite communications, onboard resources are limited, and waveform software optimization is required to reduce complexity and resource consumption, thereby reducing the design pressure of onboard hardware platforms and reducing platform power consumption. In the satellite-to-ground feeder link, the LDPC decoder uses a large number of mathematical operations such as addition, subtraction, and multiplication during the decoding process, which places huge demands on FPGA resources. It is necessary to optimize the decoding implementation method, reduce FPGA resource consumption, and achieve higher decoding throughput under resource-constrained onboard conditions.

[0003] Real-time services such as voice in satellite communications are sensitive to processing delays. Traditional LDPC decoders require multiple iterative processes, which results in long delays. Therefore, fast decoding is required to reduce transmission delays.

[0004] The LDPC decoding technology based on storage computing power changes the decoding implementation architecture and implements the core algorithm processing of LDPC decoding through storage computing power, which can effectively reduce the consumption of onboard hardware resources and platform power consumption and reduce processing latency. Summary of the invention

[0005] The purpose of the present invention is to improve the deficiencies in the above-mentioned background technology and provide an LDPC decoding device based on hybrid computing power. The present invention has the characteristics of low latency, low resource consumption, and self-loop detection.

[0006] The technical solution adopted by the present invention is:

[0007] An LDPC decoding device based on hybrid computing power includes a control unit 1, a decoding preprocessing unit 2, a logic computing power unit 3, an iterative storage unit 4, a storage computing power unit 5 and a decoding output interface unit 6;

[0008] The control unit 1 is used to receive external instructions, parse the instructions, and generate local control signals as control inputs for the decoding preprocessing unit 2, the logic computing unit 3, the iteration storage unit 4, the storage computing unit 5, and the decoding output interface unit 6;

[0009] The decoding preprocessing unit 2 is used to receive an external data source or generate a pseudo-random sequence, and output it as channel data to the iteration storage unit 4 after adaptation processing;

[0010] The iterative storage unit 4 is used to convert the format of the channel data output by the decoding preprocessing unit 2 and output it to the logic computing unit 3; and to convert the data format of the logic processing result of the decoded data output by the logic computing unit 3, and output the conversion result to the storage computing unit 5; and to convert the processing result of the storage computing unit 5 and output it to the logic computing unit 3;

[0011] The logic computing unit 3 is used to perform decoding data logic processing on the received data and output the processing result to the iteration storage unit 4;

[0012] The storage computing unit 5 is used to perform storage computing processing. If the maximum number of iterations is reached, the processing result is output to the decoding output interface unit 6. If the maximum number of iterations is not reached, the processing result is output to the iteration storage unit 4 to enter the next iteration processing;

[0013] The decoding output interface unit 6 is used to convert the processing result into a required format for output.

[0014] Furthermore, the control unit 1 includes an instruction parsing module 7, an iteration control module 8 and a parameter reporting module 9;

[0015] The instruction parsing module 7 is used to receive and parse external control instructions and output them to the iteration control module 8;

[0016] The iteration control module 8 is used to generate a local control signal as a control input of the decoding preprocessing unit 2, the logic computing unit 3, the iteration storage unit 4, the storage computing unit 5 and the decoding output interface unit 6, and to determine the number of iterations, control the entire iterative decoding process, and output the acquired parameters to the parameter reporting module 9;

[0017] The parameter reporting module 9 is used to organize and report the acquired parameters of other modules.

[0018] Furthermore, the decoding preprocessing unit 2 includes a feature recognition module 10, a preprocessing module 11 and a pseudo code generation module 12;

[0019] The feature recognition module 10 is used to recognize the received external data to be decoded or the test pseudo-random sequence generated by the pseudo-code generation module 12, determine the channel state, and output the determination result to the pre-processing module 11;

[0020] The pre-processing module 11 is used to perform adaptation processing on the data to be decoded and output it to the iterative storage unit 4 after processing;

[0021] The pseudo-code generation module 12 is used to generate a pseudo-random test pseudo-random sequence and output it to the feature recognition module 10 .

[0022] Furthermore, the logic computing unit 3 includes a symbol checking module 13, a descending sorting module 14, a minimum replacement module 15 and a data synthesis module 16;

[0023] The sign checking module 13 is used to check the sign bit of the input data from the iterative storage unit 4, and output the checked data to the data synthesis module 16;

[0024] The descending sorting module 14 is used to sort the input data from the iterative storage unit 4 from large to small, and output the minimum value and the second minimum value to the minimum replacement module 15;

[0025] The minimum replacement module 15 is used to replace the minimum value of the input data from the iteration storage unit 4 with the next minimum value, replace other data from the iteration storage unit 4 with the minimum value, and output the replaced data to the data synthesis module 16;

[0026] The data synthesis module 16 is used to synthesize the data of the symbol check module 13 and the minimum replacement module 15 into a logic processing result and then output it to the iteration storage unit 4.

[0027] Further, the iterative storage unit 4 includes a logic computing power input addressing module 17, a logic computing power output addressing module 18, a memory module 19, a storage computing power input addressing module 20 and a storage computing power output addressing module 21;

[0028] The logic computing power input addressing module 17 is used to generate the input data reading address of the logic computing power unit 3;

[0029] The logic computing power output addressing module 18 is used to generate the output data storage address of the logic computing power unit 3;

[0030] The memory module 19 is used to store the data output by the logic computing unit 3, the storage computing unit 5 and the decoding preprocessing unit 2, and output it to the corresponding module after format conversion;

[0031] The storage computing power input addressing module 20 generates the storage computing power unit 5 input data reading address;

[0032] The storage computing power output addressing module 21 is used to generate the storage computing power unit 5 output data storage address.

[0033] Further, the storage computing unit 5 includes a first mapping module 22, a second mapping module 23 and a third mapping module 24;

[0034] The first mapping module 22 is used to complete the first storage computing power operation and output the operation data to the second mapping module 23;

[0035] The second mapping module 23 is used to perform a second storage computing operation on the input data, and output the operation data to the third mapping module 24;

[0036] The third mapping module 24 is used to perform a third storage computing operation on the input data. If the maximum number of iterations is reached, the final result is output to the decoding output interface unit 6. If the maximum number of iterations is not reached, the result is output to the iteration storage unit 4.

[0037] Furthermore, the decoding output unit 6 includes an output buffer module 25, an output adaptation module 26 and a self-test comparison module 27;

[0038] The input buffer module 25 is used to buffer and store the received data and to frame it, and to output it to the output adapter module 26 in the normal communication mode and to the self-test comparison module 27 in the test mode;

[0039] The output adaptation module 26 is used to match the format of the output data according to the instruction requirements of the control unit 1, and output the matched decoded data;

[0040] The self-test comparison module 27 is used to generate a corresponding pseudo-random sequence according to the instruction requirements of the control unit 1 in the test mode, and then perform bit error comparison, and output the bit error comparison result to display the bit error rate.

[0041] Compared with the background technology, the present invention has the following advantages:

[0042] 1. The operation of the LDPC decoder in the present invention is mainly based on storage computing power, which has the advantages of saving resources and short processing delay.

[0043] 2. The present invention is implemented with VHDL code and a universal storage module built into FPGA, has no dependence on special hardware, and is easy to transplant and promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a principle block diagram of the present invention.

[0045] Figure 2 It is the electrical schematic diagram of the control unit of the present invention.

[0046] Figure 3 It is the electrical schematic diagram of the decoding preprocessing unit of the present invention.

[0047] Figure 4 It is the electrical schematic diagram of the logic computing unit of the present invention.

[0048] Figure 5 1 is an electrical schematic diagram of the iterative storage unit of the present invention.

[0049] Figure 6It is an electrical schematic diagram of the storage computing power unit of the present invention.

[0050] Figure 7 It is the electrical schematic diagram of the decoding output interface unit of the present invention. DETAILED DESCRIPTION

[0051] Reference Figures 1 to 7 , the present invention is further explained.

[0052] like Figure 1 As shown, an LDPC decoding device based on hybrid computing power includes a control unit 1, a decoding preprocessing unit 2, a logic computing power unit 3, an iterative storage unit 4, a storage computing power unit 5 and a decoding output interface unit 6;

[0053] The control unit 1 is used to receive external instructions, parse the instructions, and generate local control signals as control inputs for the decoding preprocessing unit 2, the logic computing unit 3, the iteration storage unit 4, the storage computing unit 5, and the decoding output interface unit 6;

[0054] The decoding preprocessing unit 2 is used to receive an external data source or generate a pseudo-random sequence, and output it as channel data to the iteration storage unit 4 after adaptation processing;

[0055] The iterative storage unit 4 is used to convert the format of the channel data output by the decoding preprocessing unit 2 and output it to the logic computing unit 3; and to convert the data format of the logic processing result of the decoded data output by the logic computing unit 3, and output the conversion result to the storage computing unit 5; and to convert the processing result of the storage computing unit 5 and output it to the logic computing unit 3;

[0056] The logic computing unit 3 is used to perform decoding data logic processing on the received data and output the processing result to the iteration storage unit 4;

[0057] The storage computing unit 5 is used to perform storage computing processing. If the maximum number of iterations is reached, the processing result is output to the decoding output interface unit 6. If the maximum number of iterations is not reached, the processing result is output to the iteration storage unit 4 to enter the next iteration processing;

[0058] The decoding output interface unit 6 is used to convert the processing result into a required format for output.

[0059] like Figure 2 As shown, the control unit 1 includes an instruction parsing module 7, an iteration control module 8 and a parameter reporting module 9;

[0060] The instruction parsing module 7 is used to receive and parse external control instructions and output them to the iteration control module 8;

[0061] The iteration control module 8 is used to generate a local control signal as a control input of the decoding preprocessing unit 2, the logic computing unit 3, the iteration storage unit 4, the storage computing unit 5 and the decoding output interface unit 6, and to determine the number of iterations, control the entire iterative decoding process, and output the acquired parameters to the parameter reporting module 9;

[0062] The parameter reporting module 9 is used to organize and report the acquired parameters of other modules.

[0063] like Figure 3 As shown, the decoding preprocessing unit 2 includes a feature recognition module 10, a preprocessing module 11 and a pseudo code generation module 12;

[0064] The feature recognition module 10 is used to recognize the received external data to be decoded or the test pseudo-random sequence generated by the pseudo-code generation module 12, determine the channel state, and output the determination result to the pre-processing module 11;

[0065] The pre-processing module 11 is used to perform adaptation processing on the data to be decoded and output it to the iterative storage unit 4 after processing;

[0066] The pseudo-code generation module 12 is used to generate a pseudo-random test pseudo-random sequence and output it to the feature recognition module 10 .

[0067] like Figure 4 As shown, the logic computing unit 3 includes a symbol checking module 13, a descending sorting module 14, a minimum replacement module 15 and a data synthesis module 16;

[0068] The sign checking module 13 is used to check the sign bit of the input data from the iterative storage unit 4, and output the checked data to the data synthesis module 16;

[0069] The descending sorting module 14 is used to sort the input data from the iterative storage unit 4 from large to small, and output the minimum value and the second minimum value to the minimum replacement module 15;

[0070] The minimum replacement module 15 is used to replace the minimum value of the input data from the iteration storage unit 4 with the next minimum value, replace other data from the iteration storage unit 4 with the minimum value, and output the replaced data to the data synthesis module 16;

[0071] The data synthesis module 16 is used to synthesize the data of the symbol check module 13 and the minimum replacement module 15 into a logic processing result and then output it to the iteration storage unit 4.

[0072] like Figure 5 As shown, the iterative storage unit 4 includes a logic computing power input addressing module 17, a logic computing power output addressing module 18, a memory module 19, a storage computing power input addressing module 20 and a storage computing power output addressing module 21;

[0073] The logic computing power input addressing module 17 is used to generate the input data reading address of the logic computing power unit 3;

[0074] The logic computing power output addressing module 18 is used to generate the output data storage address of the logic computing power unit 3;

[0075] The memory module 19 is used to store the data output by the logic computing unit 3, the storage computing unit 5 and the decoding preprocessing unit 2, and output it to the corresponding module after format conversion;

[0076] The storage computing power input addressing module 20 generates the storage computing power unit 5 input data reading address;

[0077] The storage computing power output addressing module 21 is used to generate the storage computing power unit 5 output data storage address.

[0078] like Figure 6 As shown, the storage computing unit 5 includes a first mapping module 22, a second mapping module 23 and a third mapping module 24;

[0079] The first mapping module 22 is used to complete the first storage computing power operation and output the operation data to the second mapping module 23;

[0080] The second mapping module 23 is used to perform a second storage computing operation on the input data, and output the operation data to the third mapping module 24;

[0081] The third mapping module 24 is used to perform a third storage computing operation on the input data. If the maximum number of iterations is reached, the final result is output to the decoding output interface unit 6. If the maximum number of iterations is not reached, the result is output to the iteration storage unit 4.

[0082] like Figure 7 As shown, the decoding output unit 6 includes an output buffer module 25, an output adaptation module 26 and a self-test comparison module 27;

[0083] The input buffer module 25 is used to buffer and store the received data and to frame it, and to output it to the output adapter module 26 in the normal communication mode and to the self-test comparison module 27 in the test mode;

[0084] The output adaptation module 26 is used to match the format of the output data according to the instruction requirements of the control unit 1, and output the matched decoded data;

[0085] The self-test comparison module 27 is used to generate a corresponding pseudo-random sequence according to the instruction requirements of the control unit 1 in the test mode, and then perform bit error comparison, and output the bit error comparison result to display the bit error rate.

Claims

1. An LDPC decoding device based on hybrid computing power, comprising a control unit (1), a decoding preprocessing unit (2), a logic computing power unit (3), an iteration storage unit (4), a storage computing power unit (5) and a decoding output interface unit (6); characterized in that: The control unit (1) is used to receive external instructions, parse the instructions, and generate local control signals as control inputs for the decoding preprocessing unit (2), the logic computing unit (3), the iteration storage unit (4), the storage computing unit (5), and the decoding output interface unit (6); The decoding preprocessing unit (2) is used to receive an external data source or generate a pseudo-random sequence, and output it as channel data to the iterative storage unit (4) after performing adaptation processing; The iterative storage unit (4) is used to convert the format of the channel data output by the decoding preprocessing unit (2) and output it to the logic computing unit (3); and to convert the data format of the logic processing result of the decoded data output by the logic computing unit (3) and output the conversion result to the storage computing unit (5); and is also used to convert the format of the processing result of the storage computing unit (5) and output it to the logic computing unit (3); The logic computing unit (3) is used to perform logic processing on the received data and decode the data, and output the processing result to the iteration storage unit (4); The storage computing unit (5) is used to perform storage computing processing. If the maximum number of iterations is reached, the processing result is output to the decoding output interface unit (6); if the maximum number of iterations is not reached, the processing result is output to the iteration storage unit (4) to enter the next iteration processing; The decoding output interface unit (6) is used to convert the processing result into a required format for output; The logic computing unit (3) includes a symbol checking module (13), a descending sorting module (14), a minimum replacement module (15) and a data synthesis module (16); The sign checking module (13) is used to check the sign bit of the input data from the iterative storage unit (4), and output the checked data to the data synthesis module (16); The descending sorting module (14) is used to sort the input data from the iterative storage unit (4) from large to small, and output the minimum value and the second minimum value to the minimum replacement module (15); The minimum replacement module (15) is used to replace the minimum value of the input data from the iteration storage unit (4) with the next minimum value, replace other data from the iteration storage unit (4) with the minimum value, and output the replaced data to the data synthesis module (16); The data synthesis module (16) is used to synthesize the data of the symbol check module (13) and the minimum replacement module (15) into a logic processing result and then output it to the iteration storage unit (4); The storage computing unit (5) comprises a first mapping module (22), a second mapping module (23) and a third mapping module (24); The first mapping module (22) is used to complete the first storage computing power operation and output the operation data to the second mapping module (23); The second mapping module (23) is used to perform a second storage computing operation on the input data, and output the operation data to the third mapping module (24); The third mapping module (24) is used to perform a third storage computing operation on the input data, and if the maximum number of iterations is reached, the final result is output to the decoding output interface unit (6); if the maximum number of iterations is not reached, the result is output to the iteration storage unit (4).

2. The LDPC decoding device based on hybrid computing power according to claim 1, characterized in that: The control unit (1) comprises an instruction parsing module (7), an iteration control module (8) and a parameter reporting module (9); The instruction parsing module (7) is used to receive and parse external control instructions and output them to the iterative control module (8); The iteration control module (8) is used to generate a local control signal as a control input of the decoding preprocessing unit (2), the logic computing unit (3), the iteration storage unit (4), the storage computing unit (5) and the decoding output interface unit (6), and to determine the number of iterations, control the entire iterative decoding process, and output the acquired parameters to the parameter reporting module (9); The parameter reporting module (9) is used to organize and report the acquired parameters of other modules.

3. The LDPC decoding device based on hybrid computing power according to claim 1 or 2, characterized in that: The decoding preprocessing unit (2) comprises a feature recognition module (10), a preprocessing module (11) and a pseudo code generation module (12); The feature recognition module (10) is used to recognize the received external data to be decoded or the test pseudo-random sequence generated by the pseudo-code generation module (12), determine the channel state, and output the determination result to the pre-processing module (11); The preprocessing module (11) is used to perform adaptation processing on the data to be decoded, and output the processed data to the iterative storage unit (4); The pseudo-code generation module (12) is used to generate a pseudo-random test pseudo-random sequence and output it to the feature recognition module (10).

4. The LDPC decoding device based on hybrid computing power according to claim 1, further characterized in that: The iterative storage unit (4) comprises a logic computing power input addressing module (17), a logic computing power output addressing module (18), a memory module (19), a storage computing power input addressing module (20) and a storage computing power output addressing module (21); The logic computing power input addressing module (17) is used to generate an input data reading address of the logic computing power unit (3); The logic computing power output addressing module (18) is used to generate an output data storage address of the logic computing power unit (3); The memory module (19) is used to store data output by the logic computing unit (3), the storage computing unit (5) and the decoding preprocessing unit (2), and to output the data to the corresponding module after performing format conversion; The storage computing power input addressing module (20) generates an input data reading address for the storage computing power unit (5); The storage computing power output addressing module (21) is used to generate a data storage address output by the storage computing power unit (5).

5. The LDPC decoding device based on hybrid computing power according to claim 1, further characterized in that: The decoding output interface unit (6) comprises an output buffer module (25), an output adaptation module (26) and a self-test comparison module (27); The output buffer module (25) is used to buffer and store the received data and to frame the received data, and to output the received data to the output adapter module (26) in the normal communication mode and to output the received data to the self-test comparison module (27) in the test mode. The output adaptation module (26) is used to match the format of the output data according to the instruction requirements of the control unit (1), and output the matched decoded data; The self-test comparison module (27) is used to generate a corresponding pseudo-random sequence in a test mode according to the instruction requirements of the control unit (1), and then perform a bit error comparison, and output the bit error comparison result to display the bit error rate.

Images