Switching circuit, control method and chip of NMOS switch tube

Abstract

The embodiment of the present invention discloses a switch circuit, a control method and a chip of an NMOS switch tube, wherein the source of the NMOS switch tube is used to input an input voltage and the drain is used to output an output voltage. When it is necessary to control the NMOS switch tube to be turned off, the control module controls the clamp switch to be turned on, and the charge pump charges the gate of the NMOS switch tube with a maintenance current to turn on the clamp circuit. The clamp circuit uses the input voltage as a reference to clamp the gate of the NMOS switch tube at a voltage that makes the NMOS switch tube in a turned-off state. When it is necessary to control the NMOS switch tube to be turned on, the control module controls the clamp switch to be turned off to turn off the clamp circuit, the clamp circuit stops clamping the gate of the NMOS switch tube, and the charge pump charges the gate of the NMOS switch tube with a start current to control the NMOS switch tube to be turned on, thereby outputting the output voltage. This embodiment can increase the turn-on speed of the NMOS switch tube.

Description

[0001] This application is a divisional application of the invention patent application with the application date of January 16, 2023, application number 202310091780.4, and name “Switching circuit, control method and chip of NMOS switch tube”. Technical Field

[0002] The present invention relates to the field of NMOS switch tubes, and in particular to a switch circuit, a control method and a chip of an NMOS switch tube. Background Art

[0003] NMOS switch tubes are widely used in integrated circuits. Compared with PMOS switch tubes, the on-resistance of NMOS switches is lower than that of PMOS switches under the same area.

[0004] In the known technology, when the NMOS switch tube needs to be turned on, the gate voltage of the NMOS switch tube is loaded to a certain high level through the driving circuit, thereby turning on the NMOS switch tube; when the NMOS switch tube needs to be turned off, the gate voltage of the NMOS switch tube is pulled down to 0 through the driving circuit, thereby turning off the NMOS switch tube.

[0005] However, the driving circuit takes a long time to switch the NMOS switch tube from an off state to an on state. Summary of the invention

[0006] Based on the above situation, the main purpose of the embodiments of the present invention is to provide a switch circuit, a control method and a chip of an NMOS switch tube to increase the turn-on speed of the NMOS switch tube.

[0007] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0008] A switch circuit of an NMOS switch tube, comprising a charge pump and an NMOS switch tube, and also comprising a clamp circuit and a control module, wherein the clamp circuit comprises a clamp switch; the source of the NMOS switch tube is connected to an input end for inputting an input voltage, and the drain is connected to an output end for outputting an output voltage; one end of the clamp circuit is connected to a gate of the NMOS switch tube, and the other end is connected to the input end; when the NMOS switch tube needs to be turned off, the control module controls the clamp switch to be turned on, and the charge pump charges the gate of the NMOS switch tube with a maintenance current to make the clamp The circuit is turned on, and the clamping circuit uses the input voltage as a reference to clamp the gate of the NMOS switch tube at a voltage that makes the NMOS switch tube in an off state; when it is necessary to control the NMOS switch tube to be turned on, the control module controls the clamping switch to be turned off so that the clamping circuit is turned off, and the clamping circuit stops clamping the gate of the NMOS switch tube, and the charge pump charges the gate of the NMOS switch tube with a turn-on current to control the NMOS switch tube to be turned on, thereby outputting the output voltage; wherein the holding current is less than the turn-on current.

[0009] A control method for a switch circuit of an NMOS switch tube, the switch circuit comprising a charge pump and an NMOS switch tube, the switch circuit further comprising a clamp circuit and a control module, the clamp circuit comprising a clamp switch; the source of the NMOS switch tube is connected to an input end for inputting an input voltage, and the drain is connected to an output end for outputting an output voltage; the control method comprises the following steps: when it is necessary to control the NMOS switch tube to be turned off, the control module controls the clamp switch to be turned on, and the charge pump charges the gate of the NMOS switch tube with a maintenance current, so that the clamp circuit The control module controls the clamping switch to be turned on, and the clamping circuit uses the input voltage as a reference to clamp the gate of the NMOS switch tube at a voltage that makes the NMOS switch tube in an off state; when it is necessary to control the NMOS switch tube to be turned on, the control module controls the clamping switch to be turned off so that the clamping circuit is turned off, and the clamping circuit stops clamping the gate of the NMOS switch tube, and the charge pump charges the gate of the NMOS switch tube with a turn-on current to control the NMOS switch tube to be turned on, thereby outputting the output voltage; wherein the holding current is less than the turn-on current.

[0010] A chip comprises a switch circuit of any NMOS switch tube as described above.

[0011] In this embodiment, when it is necessary to control the NMOS switch tube to be turned off, the clamping circuit uses the input voltage as a reference to clamp the gate of the NMOS switch tube at a voltage that puts the NMOS switch tube in an off state; when it is necessary to control the NMOS switch tube to be turned on, the clamping circuit stops clamping the gate of the NMOS switch tube, and the charge pump charges the gate of the NMOS switch tube with a turn-on current. Compared with the known technology, in this embodiment, the amount of charge transferred by the charge pump to the gate of the NMOS switch tube is greatly reduced, so the NMOS switch tube can be quickly turned on, which is very suitable for applications in scenarios where the NMOS switch tube needs to be turned on quickly.

[0012] Other beneficial effects of the present invention will be explained in the specific implementation manner through the introduction of specific technical features and technical solutions. Through the introduction of these technical features and technical solutions, those skilled in the art should be able to understand the beneficial technical effects brought about by the technical features and technical solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[0014] Figure 1 A switch circuit of an NMOS switch tube according to a preferred embodiment of the present invention;

[0015] Figure 2 A curve diagram showing the relationship between the parasitic capacitance of the gate of an NMOS switch tube and different gate-source voltages in a preferred embodiment of the present invention;

[0016] Figure 3 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0017] Figure 4 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0018] Figure 5 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0019] Figure 6 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0020] Figure 7 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0021] Figure 8 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0022] Fig. 9A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0023] Fig.10 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0024] Fig.11 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0025] Fig.12 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0026] Fig.13 A switch circuit of an NMOS switch tube according to another preferred embodiment of the present invention;

[0027] Fig.14 yes Fig.13 A waveform diagram of the switching circuit of the embodiment under certain circumstances. DETAILED DESCRIPTION

[0028] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the following detailed description of the present invention, some specific details are described in detail. In order to avoid confusing the essence of the present invention, known methods, processes, procedures, and components are not described in detail.

[0029] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0030] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprising" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0031] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0032] Figure 1It is a switching circuit of an NMOS switch tube according to an embodiment of the present invention, and the switching circuit can be applied to circuits of various electronic devices, such as circuits of integrated circuits or discrete components. The NMOS switch tube Ms can be a power type or a non-power type switch tube. The switching circuit includes a charge pump 100, an NMOS switch tube Ms, and a clamping circuit 200; wherein the source of the NMOS switch tube Ms is connected to the input terminal Vin for inputting an input voltage, and the drain of the NMOS switch tube Ms is connected to the output terminal Vout for outputting an output voltage; the output terminal of the charge pump 100 is connected to the gate of the NMOS switch tube Ms; one end of the clamping circuit 200 is connected to the gate Vgate of the NMOS switch tube Ms, and the other end is connected to the input terminal; the input terminal can be connected to a power supply, and the output terminal can be connected to a subsequent circuit.

[0033] When it is necessary to control the NMOS switch tube Ms to be turned off, the clamping circuit 200 uses the input voltage as a reference to clamp the gate of the NMOS switch tube Ms at a voltage that makes the NMOS switch tube Ms in the off state. At this time, the gate voltage is greater than or equal to the input voltage, that is, the gate-source voltage is greater than or equal to 0. Since the NMOS switch tube Ms is turned off, the drain does not output a voltage. When it is necessary to control the NMOS switch tube Ms to be turned on, the clamping circuit 200 stops clamping the gate of the NMOS switch tube Ms, and the charge pump 100 charges the gate of the NMOS switch tube Ms with a turn-on current (that is, charging the parasitic capacitance Cpar of the gate), so that the gate-source voltage is greater than the turn-on threshold of the NMOS switch tube Ms, so as to control the NMOS switch tube Ms to be turned on, thereby outputting an output voltage, that is, the voltage at the input end is provided to the output end through the NMOS switch tube Ms, and then the output voltage is provided to the subsequent circuit, for example, a battery connected to the input end is supplied to the subsequent circuit at the output end through the NMOS switch tube Ms.

[0034] Figure 2It is a curve diagram showing the relationship between the parasitic capacitance Cpar of the gate of the NMOS switch Ms and different gate-source voltages Vgs. It can be seen from the figure that when the gate-source voltage is near 0, the parasitic capacitance Cpar of the gate reaches the minimum, and the amount of charge required to charge the gate from a certain gate-source voltage to another gate-source voltage is the area enclosed by the vertical line, the curve and the horizontal coordinate where the two voltages are located. In this embodiment, the gate-source voltage when the NMOS switch Ms is turned on is recorded as Vg (for example, the size is 2*Vth, where Vth is the turn-on threshold of the NMOS switch Ms, that is, the gate-source voltage required for critical conduction), and the amount of charge charged to the gate by the charge pump 100 is approximately the shaded area within the range of L1; and in the conventional known technology, since the gate potential is set to 0 when the NMOS is turned off, its gate-source voltage is approximately -Vin (for example -5V). When the NMOS switch Ms needs to be turned on, the amount of charge that the charge pump should charge to the gate is greater than The shaded area is approximately within the range of L2; it can be seen that, compared with the known technology, in this embodiment, the amount of charge transferred by the charge pump 100 to the gate of the NMOS switch tube Ms is greatly reduced, so the NMOS switch tube Ms can be quickly turned on, which is very suitable for applications in scenarios where the NMOS switch tube Ms needs to be quickly turned on; for example, the NMOS switch tube Ms connected to vsys and vbat in the NVDC architecture, this embodiment can quickly control the NMOS switch tube Ms to open, thereby avoiding vsys voltage drop, or even more serious system downtime.

[0035] Figure 3 It is a switch circuit of an NMOS switch tube according to another embodiment of the present invention, and the switch circuit further includes a control module 300; the clamp circuit 200 includes a clamp unit 210 and a clamp switch S2; when it is necessary to control the NMOS switch tube Ms to be turned off, the control module 300 controls the clamp switch S2 to be turned on, and the charge pump 100 charges the gate of the NMOS switch tube Ms with a maintenance current, so that the voltage of the gate of the NMOS switch tube Ms is sufficient to turn on the clamp unit 210, that is, the clamp circuit 200 is turned on, so that the clamp circuit 200 clamps the gate of the NMOS switch tube Ms. When it is necessary to control the NMOS switch tube Ms to be turned on, the control module 300 controls the clamp switch S2 to be turned off, so that the clamp unit 210 is turned off, that is, the clamp circuit 200 is turned off, so that the clamp circuit 200 stops clamping the gate of the NMOS switch tube Ms. In this embodiment, the control module 300 can be composed of a logic circuit, for example, including an inverter. Since the conduction states of the NMOS switch tube Ms and the clamp switch S2 are exactly opposite, for example, when the NMOS switch tube Ms is turned on, the clamp switch S2 is turned off (or when the NMOS switch tube Ms is turned off, the clamp switch S2 is turned on), the control signal of the NMOS switch tube Ms can be inverted to obtain a signal that is used as a control signal for controlling the clamp switch S2.

[0036] Figure 4 is Figure 3 A more specific embodiment based on the embodiment, in the switching circuit of this embodiment, the clamping unit 210 includes a clamping diode D, and the clamping diode D and the clamping switch S2 are connected in series to form the clamping circuit 200; for example, the anode of the clamping diode D is connected to the gate of the NMOS switch tube Ms, and the cathode is connected to the source of the NMOS switch tube Ms through the clamping switch S2. When it is necessary to control the NMOS switch tube Ms to be turned off, the control module 300 controls the clamp switch S2 to be turned on, and the charge pump 100 charges the gate of the NMOS switch tube Ms with a maintenance current, so that the voltage of the gate of the NMOS switch tube Ms is sufficient to turn on the clamp diode D, that is, the clamp circuit 200 is turned on, so that the clamp circuit 200 clamps the gate of the NMOS switch tube Ms; since the voltage at the output end of the charge pump 100 is sufficient to turn on the clamp diode D, the clamp diode D is turned on, and the gate of the NMOS switch tube Ms is clamped at a certain voltage based on the input voltage, such as Vin+Vd, where Vd is the conduction voltage drop of the clamp diode D. When it is necessary to control the NMOS switch tube Ms to be turned on, the control module 300 controls the clamp switch S2 to be turned off, so that the clamp diode D is disconnected, that is, the clamp circuit 200 is disconnected, so that the clamp circuit 200 stops clamping the gate of the NMOS switch tube Ms.

[0037] In one embodiment, when the clamping circuit 200 clamps the gate of the NMOS switch tube Ms, the clamping circuit 200 clamps the gate of the NMOS switch tube Ms at a voltage equal to the input voltage, that is, the gate-source voltage is equal to 0. Since the NMOS switch tube Ms is turned on only when the gate-source voltage of the NMOS switch tube Ms is greater than Vth, this embodiment can ensure that the NMOS switch tube Ms will not be turned on during clamping, and the circuit is easy to implement.

[0038] Figure 5 is Figure 3A more specific embodiment based on the embodiment, in the switch circuit of this embodiment, the clamp unit 210 includes a clamp PMOS tube Mclp and a voltage source V1, the source of the clamp PMOS tube Mclp is connected to the gate of the NMOS switch tube Ms, the gate of the clamp PMOS tube Mclp is connected to the source of the NMOS switch tube Ms through the voltage source, and the drain of the clamp PMOS tube Mclp is grounded through the clamp switch S2 220; wherein the voltage source is used to provide a voltage equal to the difference between the input voltage and the turn-on threshold of the clamp PMOS tube Mclp, that is, Vin-Vth, to the gate of the clamp PMOS tube Mclp based on the input voltage; the voltage provided by the output end of the charge pump 100 is sufficient to turn on the clamp PMOS tube Mclp, that is, greater than the sum of the voltage of the voltage source and the turn-on threshold of the clamp PMOS tube Mclp. When it is necessary to control the NMOS switch tube Ms to be turned off, the control module 300 controls the clamp switch S2 to be turned on, and the charge pump 100 charges the gate of the NMOS switch tube Ms with a maintaining current, so that the voltage of the gate of the NMOS switch tube Ms is sufficient to turn on the clamped PMOS tube Mclp, that is, the clamp circuit 200 is turned on, so that the clamp circuit 200 clamps the gate of the NMOS switch tube Ms; since the voltage at the output end of the charge pump 100 is sufficient to turn on the clamped PMOS tube Mclp, the clamped PMOS tube Mclp is turned on, and the gate of the clamped PMOS tube Mclp is clamped at the sum of the voltage of the voltage source and the turn-on threshold of the clamped PMOS tube Mclp, that is: V1+Vth; since V1=Vin-Vth, the clamped PMOS tube Mclp is clamped at (Vin-Vth)+Vth, that is, Vin. When the NMOS switch tube Ms needs to be turned on, the control module 300 controls the clamp switch S2 to turn off, so that the clamp PMOS tube Mclp is disconnected, that is, the clamp circuit 200 is disconnected, so that the clamp circuit 200 stops clamping the gate of the NMOS switch tube Ms.

[0039] Figure 6It is a switch circuit of an NMOS switch tube according to another embodiment of the present invention. The charge pump 100 includes an output capacitor Ccp 120 and a charge generating circuit 110. The output capacitor 120 is connected across the output end of the charge generating circuit 110 and the source of the NMOS switch tube Ms, that is, one end of the output capacitor 120 is connected to the output end of the charge generating circuit 110, and the other end is connected to the input end Vin. The charge generating circuit 110 is used to adjust the charge amount of the output capacitor 120 so that the output capacitor 120 maintains a predetermined voltage difference on the basis of the input voltage; the predetermined voltage difference is recorded as △V, and the target voltage Vt of the output capacitor 120 can be expressed as: Vt=Vin+△V; the voltage of the output end of the charge generating circuit 110 can be obtained by feedback, and then the charge generating circuit 110 adjusts the voltage of the output end of the charge generating circuit 110 to maintain it at the target voltage by comparing the target voltage with the voltage obtained by feedback. In this embodiment, the output end of the charge generating circuit 110 maintains a predetermined voltage difference on the basis of the input voltage. Since the voltage of the source of the NMOS switch tube Ms is the input voltage, the predetermined voltage difference △V can be used to turn on the NMOS switch tube Ms, so that the voltage difference output by the charge generating circuit 110 can be minimized on the basis of ensuring that the NMOS switch tube Ms is turned on. In addition, even if the input voltage Vin changes, it is only necessary to maintain the predetermined voltage difference on the basis of the input voltage, which will not affect the effect of clamping or turning on the NMOS switch tube Ms.

[0040] Figure 7It is a switching circuit of an NMOS switch tube according to another embodiment of the present invention. The switching circuit also includes an opening degree detection circuit 400 for detecting the voltage of the gate of the NMOS switch tube Ms. When it is necessary to control the NMOS switch tube Ms to be turned on, the opening degree detection circuit 400 starts to detect the voltage of the gate of the NMOS switch tube Ms. If the opening degree detection circuit 400 detects that the voltage of the gate of the NMOS switch tube Ms is greater than the gate voltage threshold, the charge pump 100 changes from charging the gate of the NMOS switch tube Ms with a turn-on current to charging the gate of the NMOS switch tube Ms with a maintenance current to maintain the NMOS switch tube Ms to remain turned on; wherein the maintenance current is less than the turn-on current; the gate voltage threshold is a voltage that can turn on the NMOS switch tube Ms. Since the voltage of the source of the NMOS switch tube Ms is the input voltage, the gate voltage threshold is an input voltage plus an offset voltage, for example, the offset voltage can be twice the turn-on threshold Vth of the NMOS switch tube Ms. In this embodiment, since the start-up current is relatively large, the gate of the NMOS switch tube Ms can be charged in a relatively short time, thereby turning on the NMOS switch tube Ms more quickly; and after turning on the NMOS switch tube Ms, the conduction of the NMOS switch tube Ms is maintained with a smaller maintenance current, thereby reducing the power consumption of the circuit. In other words, this embodiment takes into account both the turn-on speed and the power consumption of the NMOS switch tube Ms. In this embodiment, after the opening degree detection circuit 400 detects whether the gate voltage of the NMOS switch tube Ms is greater than the gate voltage threshold, it can send a corresponding signal to the control module 300, so that the control module 300 controls the charge pump 100 to output the start-up current or the maintenance current accordingly.

[0041] Figure 8It is a switch circuit of an NMOS switch tube according to another embodiment of the present invention, wherein the opening degree detection circuit 400 includes an opening degree detection unit and a detection switch S3. When it is necessary to control the NMOS switch tube Ms to be turned off, the detection switch S3 is turned off, so that the opening degree detection circuit 400 is turned off and stops detecting the voltage of the gate of the NMOS switch tube Ms. When it is necessary to control the NMOS switch tube Ms to be turned on, the detection switch S3 is turned on to turn on the opening degree detection circuit 400 and start to detect the voltage of the gate of the NMOS switch tube Ms; if the gate of the NMOS switch tube Ms is charged to a voltage less than the gate voltage threshold, the detection switch S3 remains turned on to control the opening degree detection circuit 400 to keep detecting the voltage of the gate of the NMOS switch tube Ms; if the gate of the NMOS switch tube Ms is charged to a voltage greater than the gate voltage threshold, the opening degree detection circuit 400 can also stop detecting the voltage of the gate of the NMOS switch tube Ms; for example, the control module 300 controls the detection switch S3 to be turned off, so that the opening degree detection circuit 400 is turned off, and then the opening degree detection circuit 400 stops detecting the voltage of the gate of the NMOS switch tube Ms. In this way, on the basis of realizing the opening degree detection, the power consumption of the switch circuit can also be reduced.

[0042] Fig. 9It is a switch circuit of an NMOS switch tube in another embodiment of the present invention, in which an opening degree detection circuit 400 includes a first detection PMOS tube Mp3, a second detection PMOS tube Mp4 and a detection resistor Rs; the source of the first detection PMOS tube Mp3 is connected to the gate of the NMOS switch tube Ms, the drain of the first detection PMOS tube Mp3 is respectively connected to its own gate and the source of the second detection PMOS tube Mp4, the gate of the second detection PMOS tube Mp4 is connected to the source of the NMOS switch tube Ms, and the drain is grounded through the detection resistor Rs. In this embodiment, the opening thresholds of the first detection PMOS tube Mp3 and the second detection PMOS tube Mp4 are the same, both are Vth, and are the same as the opening threshold of the NMOS switch tube Ms, so the gate voltage threshold can be expressed as 2*Vth. When the voltage of the gate of the NMOS switch tube Ms exceeds the gate voltage threshold 2*Vth, the first detection PMOS tube Mp3 and the second detection PMOS tube Mp4 are turned on, and the current flows through the detection resistor Rs via the gate of the NMOS switch tube Ms, the first detection PMOS tube Mp3 and the second detection PMOS tube Mp4, so the voltage on the detection resistor Rs is high level; therefore, if the voltage of the detection resistor Rs is detected to be high level, it can be determined that the voltage of the gate of the NMOS switch tube Ms is greater than the gate voltage threshold. When the voltage of the gate of the NMOS switch tube Ms is less than the gate voltage threshold 2*Vth, the first detection PMOS tube Mp3 and the second detection PMOS tube Mp4 are turned off, and no current flows through the detection resistor Rs, so the voltage on the detection resistor Rs is low level; therefore, if the voltage of the detection resistor Rs is detected to be low level, it can be determined that the voltage of the gate of the NMOS switch tube Ms is less than the gate voltage threshold.

[0043] exist Fig. 9 In an alternative embodiment of the switch tube, the first detection PMOS tube Mp3 can be replaced by a detection diode. In this alternative embodiment, the anode of the detection diode is connected to the gate of the NMOS switch tube Ms, and the cathode is connected to the source of the second detection PMOS tube Mp4. In addition, the gate voltage threshold in this alternative embodiment is Vth+Vd, where Vd is the conduction threshold of the detection diode.

[0044] Fig.10 yes Fig. 9In a more specific embodiment based on the switch circuit of the embodiment, in the switch circuit of the embodiment, the opening degree detection circuit 400 also includes a detection switch S3, which is connected in series with the detection resistor Rs and connected between the drain of the second detection PMOS tube Mp4 and the ground. For example, the drain of the second detection PMOS tube Mp4 is connected to the ground through the detection switch S3 and the detection resistor Rs in sequence; the control module 300 controls the on and off of the opening degree detection circuit 400 by controlling the on and off of the detection switch S3. For example, when the NMOS switch tube Ms needs to be turned on, the control module 300 controls the detection switch S3 to be turned on, so that the opening degree detection circuit 400 starts to detect the gate voltage of the NMOS switch tube Ms. If the opening degree detection circuit 400 detects that the gate of the NMOS switch tube Ms is charged to a voltage greater than the gate voltage threshold, the control module 300 controls the detection switch S3 to be turned off, so that the opening degree detection circuit 400 stops detecting the gate voltage of the NMOS switch tube Ms to save power consumption.

[0045] Fig.11It is a switch circuit of an NMOS switch tube according to another embodiment of the present invention, and the switch circuit also includes a current source 500, which is a mirror current source, and a charge pump 100 is used to provide the required current to the current source 500; the current source 500 includes a first reference branch 510 for providing a first reference current, a second reference branch 520 for providing a second reference current, and an output branch 530; wherein the first reference current is less than the second reference current. When it is necessary to control the NMOS switch tube Ms to turn off, the output branch 530 copies the first reference current as a holding current to provide the clamping circuit 200 with the current required for clamping, or the gate voltage of the NMOS switch tube Ms required for clamping. When it is necessary to control the NMOS switch tube Ms to be turned on, if the voltage of the gate of the NMOS switch tube Ms is less than the gate voltage threshold (for example, the opening degree detection circuit 400 detects that the voltage of the gate is less than the gate voltage threshold), the output branch 530 copies the sum of the first reference current and the second reference current as the turn-on current, so that the gate of the NMOS switch tube Ms can be charged to a voltage greater than the gate voltage threshold at a faster speed, thereby quickly turning on the NMOS switch tube Ms. If the gate of the NMOS switch tube Ms is charged to a voltage greater than the gate voltage threshold (for example, the opening degree detection circuit 400 detects that the voltage of the gate is greater than the gate voltage threshold), the output branch 530 only copies the first reference current as the holding current to keep the NMOS switch tube Ms turned on, which can save power consumption. In this embodiment, the first reference current and the second reference current are output through the first reference branch 510 and the second reference branch 520, so that the output branch 530 can copy the output holding current and the start-up current, so that the charge pump 100 can accurately control the gate charging current of the NMOS switch tube Ms, and then accurately control the conduction or maintenance of conduction, and disconnection of the NMOS switch.

[0046] Fig.12It is a switch circuit of an NMOS switch tube according to another embodiment of the present invention. The switch circuit also includes a current source 500, which is a mirror current source. The control module 300 includes an RS trigger 310, and the charge pump 100 is used to provide the required current to the current source 500. The current source 500 includes a first reference branch 510 for providing a first reference current, a second reference branch 520 for providing a second reference current, a reference current switch S1 for controlling the on and off of the second reference branch 520, and an output branch 530; wherein the first reference current is less than the second reference current; the reset end and the set end of the RS trigger 310 are used to respectively input the voltage of the detection resistor Rs and the control signal on_slot of the RS trigger 310, and the output end is used to control the reference current switch S1 and the detection switch S3, wherein the control signal of the RS trigger 310 is a rising edge extraction signal of the switching signal of the NMOS switch tube Ms, that is, when the switching signal of the NMOS switch tube Ms is a rising edge, the rising edge extraction signal is a high level of a set width, and in other states of the switching signal of the NMOS switch tube Ms, such as a stable level or a falling edge, the rising edge extraction signal is a low level. When it is necessary to control the NMOS switch tube Ms to be turned off, the switching signal of the NMOS switch tube Ms is a turn-off signal, and the output end of the RS trigger 310 outputs a trigger turn-off signal to control the reference current switch S1 and the detection switch S3 to be turned off, so that the output branch 530 copies the first reference current as a holding current, so that the voltage of the gate of the NMOS switch tube Ms is sufficient to turn on the clamping unit 210, and the opening degree detection circuit 400 stops detecting the voltage of the gate of the NMOS switch tube Ms. When it is necessary to control the NMOS switch tube Ms to be turned on, the switch signal of the NMOS switch tube Ms is a turn-on signal, and the rising edge of the turn-on signal serves as the control signal of the RS trigger 310. The control signal prompts the output end of the RS trigger 310 to output a trigger turn-on signal, thereby controlling the reference current switch S1 and the detection switch S3 to be turned on, so that the output branch 530 copies the sum of the first reference current and the second reference current as the turn-on current, so as to quickly charge the gate of the NMOS switch tube Ms, and enable the opening degree detection circuit 400 to start detecting the voltage of the gate of the NMOS switch tube Ms; in this way, the charge pump 100 starts to charge the gate of the NMOS switch tube Ms with the turn-on current, and the voltage of the gate will gradually increase. When the gate of the NMOS switch tube Ms is less than the gate voltage threshold, the first detection PMOS tube Mp3 and the second detection PMOS tube Mp4 are not turned on, and no current flows through the detection resistor Rs. Therefore, the voltage of the detection resistor Rs is at a low level, causing the output end of the RS trigger 310 to still maintain the output trigger turn-on signal, so the reference current switch S1 and the detection switch S3 continue to remain turned on.When the gate of the NMOS switch tube Ms is greater than the gate voltage threshold, the first detection PMOS tube Mp3 and the second detection PMOS tube Mp4 are turned on, and current flows through the detection resistor Rs. Therefore, the voltage of the detection resistor Rs is at a high level, prompting the output end of the RS trigger 310 to output a trigger shutdown signal, controlling the reference current switch S1 and the detection switch S3 to be turned off, so that the output branch 530 copies the first reference current as a holding current to maintain the conduction of the NMOS switch tube Ms, and the opening degree detection circuit 400 stops detecting the voltage of the gate of the NMOS switch tube Ms.

[0047] Fig.13 It is a switch circuit of an NMOS switch tube according to another embodiment of the present invention. In the switch circuit, the current source 500 includes a first PMOS tube Mp1, a first reference branch 510, a second reference branch 520 and an output branch 530; wherein the first reference branch 510 includes a reference constant current source Ib, the second reference branch 520 includes a reference resistor Rq and a reference current switch S1, the reference resistor Rq is connected in series with the reference current switch S1, and then connected in parallel with the reference constant current source Ib; the output branch 530 includes a second PMOS tube Mp2; the source of the first PMOS tube Mp1 is connected to the output terminal VCP of the charge generating circuit 110, the gate is connected to its own drain, and the gate and drain of the second PMOS tube Mp2 are grounded through the reference constant current source Ib; the source of the second PMOS tube Mp2 is connected to the output terminal VCP of the charge generating circuit 110, and the drain is connected to the gate of the NMOS switch tube Ms. When the control current source 500 outputs the startup current, the RS trigger 310 controls the reference current switch S1 to turn on, and the second reference branch 520 outputs the second reference current, so that the first PMOS tube Mp1 flows through the sum of the first reference current and the second reference current, and therefore, the second PMOS tube Mp2 copies (or is called a mirror) the sum of the first reference current and the second reference current, and charges the NMOS switch tube Ms. When the control current source 500 outputs the holding current, the RS trigger 310 controls the reference current switch S1 to turn off, and the second reference branch 520 stops outputting the second reference current, so that the first PMOS tube Mp1 only flows through the first reference current, and therefore, the second PMOS tube Mp2 copies (or is called a mirror) the first reference current, and charges the NMOS switch tube Ms.

[0048] exist Fig.13In the switch circuit, the RS trigger 310 includes a first NOR gate 311 and a second NOR gate 312; the first input terminal 311a of the first NOR gate 311 inputs the voltage of the detection resistor Rs, the second input terminal 311b is connected to the output terminal 312c of the second NOR gate 312, the output terminal 311c serves as the output terminal of the RS trigger 310 and is connected to the first input terminal 312a of the second NOR gate 312; the second input terminal 312b of the second NOR gate 312 inputs the control signal on_slot of the RS trigger 310. Fig.14 yes Fig.13 The waveform diagram of the switch circuit of the embodiment under certain conditions. Fig.14As shown, on, on_b, fullon, on_slot and on_fast respectively represent the switch signal of the NMOS switch tube Ms, the control signal of the clamp switch S2, the voltage of the detection resistor Rs, the control signal of the RS trigger 310, and the output signal of the RS trigger 310; wherein, the control signal on_slot of the RS trigger 310 is the rising edge extraction signal of the switch signal of the NMOS switch tube Ms; the control signal on_b of the clamp switch S2 is the inversion of the switch signal of the NMOS switch tube Ms. When it is necessary to control the NMOS switch tube Ms to be disconnected, the on signal is low level, on_b, fullon, on_slot and on_fast are high, low, low and low levels respectively, therefore, the clamp switch S2 is turned on, and the clamp circuit 200 clamps the NMOS switch tube Ms; the reference current switch S1 and the detection switch S3 are turned off, and the output branch 530 only copies the first reference current to charge the gate of the NMOS switch tube Ms to maintain the voltage of the gate of the NMOS switch tube Ms required for the clamp circuit 200 to be turned on. When it is necessary to control the NMOS switch tube Ms to be turned on, the on signal changes from a low level to a high level, and the rising edge extraction signal on_b is a high level pulse of a set width. The rising edge extraction signal on_b prompts the output end of the RS trigger 310 to output a trigger turn-on signal, that is, on_fast becomes a high level, the reference current switch S1 and the detection switch S3 are turned on, and the output branch 530 copies the sum of the first reference current and the second reference current as the turn-on current to charge the gate of the NMOS switch tube Ms; before the gate voltage of the NMOS switch tube Ms reaches the gate threshold voltage, the voltage fullon of the detection resistor Rs is a low level, so on_fast maintains a high level, that is, the reference current switch S1 and the detection switch S3 are maintained turned on. When the gate voltage of the NMOS switch tube Ms is greater than the gate threshold voltage, due to the current flowing through the detection resistor Rs, its voltage fullon becomes a high level, prompting the output end of the RS trigger 310 to output a trigger shutdown signal, that is, on_fast becomes a low level, the reference current switch S1 and the detection switch S3 are disconnected, and the output branch 530 only copies the first reference current as a holding current to charge the gate of the NMOS switch tube Ms.

[0049] Those skilled in the art will appreciate that, without conflict, the above-mentioned preferred solutions can be freely combined and superimposed.

[0050] It should be understood that the above-mentioned embodiments are merely illustrative and not restrictive. Without departing from the basic principles of the present invention, various obvious or equivalent modifications or substitutions that can be made by those skilled in the art to the above-mentioned details will all be included in the scope of the claims of the present invention.

Claims

1. A switching circuit of an NMOS switch tube, comprising a charge pump and an NMOS switch tube, characterized in that: It also includes a clamping circuit, an opening degree detection circuit and a control module, wherein the clamping circuit includes a clamping switch; The source of the NMOS switch tube is connected to the input end for inputting an input voltage, and the drain is connected to the output end for outputting an output voltage; one end of the clamp circuit is connected to the gate of the NMOS switch tube, and the other end is connected to the input end; the opening degree detection circuit includes a detection switch, a first detection PMOS tube, a second detection PMOS tube and a detection resistor; the source of the first detection PMOS tube is connected to the gate of the NMOS switch tube, the drain of the first detection PMOS tube is respectively connected to its own gate and the source of the second detection PMOS tube, the gate of the second detection PMOS tube is connected to the source of the NMOS switch tube, and the drain is connected to one end of the detection resistor through the detection switch, and the other end of the detection resistor is grounded; When it is necessary to control the NMOS switch tube to be turned off, the control module controls the clamp switch to be turned on, and the charge pump charges the gate of the NMOS switch tube with a maintenance current to turn on the clamp circuit. The clamp circuit uses the input voltage as a reference to clamp the gate of the NMOS switch tube at a voltage that makes the NMOS switch tube in a turned-off state; When it is necessary to control the NMOS switch tube to be turned on, the control module controls the clamp switch to be turned off so that the clamp circuit is turned off, the clamp circuit stops clamping the gate of the NMOS switch tube, and the charge pump charges the gate of the NMOS switch tube with a turn-on current to control the NMOS switch tube to be turned on, thereby outputting the output voltage; Wherein, the holding current is smaller than the start current.

2. The switch circuit according to claim 1, characterized in that: During clamping, the clamping circuit clamps the gate of the NMOS switch tube at a voltage equal to the input voltage.

3. The switch circuit according to claim 2, characterized in that: The clamp circuit comprises a clamp PMOS tube, the source of the clamp PMOS tube is connected to the gate of the NMOS switch tube, and the gate of the clamp PMOS tube is connected to the source of the NMOS switch tube through a voltage source; The voltage source is used to provide a voltage equal to the difference between the input voltage and the turn-on threshold of the clamp PMOS tube to the gate of the clamp PMOS tube based on the input voltage.

4. The switch circuit according to claim 1, characterized in that: The charge pump includes an output capacitor and a charge generating circuit, wherein the output capacitor is connected across the output end of the charge generating circuit and the source of the NMOS switch tube, and the charge generating circuit is used to adjust the charge amount of the output capacitor so that the output capacitor maintains a predetermined voltage difference based on the input voltage.

5. The switch circuit according to claim 1, characterized in that: When it is necessary to control the conduction of the NMOS switch tube, if the opening degree detection circuit detects that the voltage of the gate of the NMOS switch tube is greater than the gate voltage threshold, the charge pump changes from charging the gate of the NMOS switch tube with the opening current to charging the gate of the NMOS switch tube with a maintenance current to keep the NMOS switch tube turned on.

6. The switch circuit according to claim 5, characterized in that: When the NMOS switch tube needs to be controlled to be turned off, the detection switch is turned off, so that the opening degree detection circuit is turned off and stops detecting the voltage of the gate of the NMOS switch tube; When it is necessary to control the NMOS switch tube to be turned on, the detection switch is turned on to turn on the opening degree detection circuit and start detecting the voltage of the gate of the NMOS switch tube. If the gate of the NMOS switch tube is charged to a voltage less than the gate voltage threshold, the detection switch remains turned on to control the opening degree detection circuit to keep detecting the voltage of the gate of the NMOS switch tube. If the gate of the NMOS switch tube is charged to a voltage greater than the gate voltage threshold, the detection switch is turned off to control the opening degree detection circuit to stop detecting the voltage of the gate of the NMOS switch tube.

7. The switch circuit according to claim 6, characterized in that: If the gate of the NMOS switch tube is charged to a voltage greater than the gate voltage threshold, the opening degree detection circuit stops detecting the voltage of the gate of the NMOS switch tube.

8. The switch circuit according to claim 7, characterized in that: If the voltage of the detection resistor is at a high level, it is determined that the gate voltage of the NMOS switch tube is greater than the gate voltage threshold. If the voltage of the detection resistor is at a low level, it is determined that the gate voltage of the NMOS switch tube is less than the gate voltage threshold.

9. The switch circuit according to claim 5, characterized in that: Also includes a current source, the charge pump is used to provide the required current to the current source; The current source comprises a first reference branch for providing a first reference current, a second reference branch for providing a second reference current, and an output branch, wherein the first reference current is smaller than the second reference current; When it is necessary to control the NMOS switch tube to be turned off, the output branch copies the first reference current as the holding current to provide the clamping circuit with the current required for clamping; When it is necessary to control the NMOS switch tube to be turned on, if the voltage of the gate of the NMOS switch tube is less than the gate voltage threshold, the output branch copies the sum of the first reference current and the second reference current as the turn-on current; if the gate of the NMOS switch tube is charged to a voltage greater than the gate voltage threshold, the output branch copies the first reference current as the holding current to maintain the NMOS switch tube turned on.

10. The switch circuit according to claim 8, characterized in that: It also includes a current source, the control module includes an RS trigger, and the charge pump is used to provide the required current to the current source; The current source comprises a first reference branch for providing a first reference current, a second reference branch for providing a second reference current, a reference current switch for controlling the on and off of the second reference branch, and an output branch; wherein the first reference current is smaller than the second reference current; The reset terminal and the set terminal of the RS trigger are used to input the voltage of the detection resistor and the control signal of the RS trigger respectively, and the output terminal is used to control the reference current switch and the detection switch; wherein the control signal of the RS trigger is a rising edge extraction signal of the switch signal of the NMOS switch tube; When it is necessary to control the NMOS switch tube to be turned off, the switch signal of the NMOS switch tube is a turn-off signal, the output end of the RS trigger outputs a trigger turn-off signal, controls the reference current switch and the detection switch to be turned off, so that the output branch copies the first reference current as the holding current, and the opening degree detection circuit stops detecting the voltage of the gate of the NMOS switch tube; When it is necessary to control the NMOS switch tube to be turned on, the switch signal of the NMOS switch tube is a turn-on signal, and the output end of the RS trigger outputs a trigger turn-on signal to control the reference current switch and the detection switch to be turned on, so that the output branch copies the sum of the first reference current and the second reference current as the turn-on current, and the opening degree detection circuit starts to detect the voltage of the gate of the NMOS switch tube. If the voltage of the detection resistor is at a high level, the output end of the RS trigger outputs a trigger turn-off signal to control the reference current switch and the detection switch to be turned off, so that the output branch copies the first reference current as the holding current, and the opening degree detection circuit stops detecting the voltage of the gate of the NMOS switch tube.

11. The switch circuit according to claim 9 or 10, characterized in that: The first reference branch includes a reference constant current source, and the second reference branch includes a reference resistor, and the reference resistor and the reference constant current source are connected in parallel.

12. The switch circuit according to claim 10, characterized in that: The RS trigger includes a first NOR gate and a second NOR gate; The first input terminal of the first NOR gate inputs the voltage of the detection resistor, the second input terminal is connected to the output terminal of the second NOR gate, and the output terminal serves as the output terminal of the RS trigger and is connected to the first input terminal of the second NOR gate; The second input terminal of the second NOR gate inputs the control signal of the RS trigger; When the NMOS switch tube needs to be controlled to be turned on, a control signal of the RS trigger is generated according to the rising edge of the switch signal of the NMOS switch tube, so that the output end of the RS trigger outputs a trigger turn-on signal.

13. A method for controlling a switch circuit of an NMOS switch tube, wherein the switch circuit comprises a charge pump and an NMOS switch tube, characterized in that: The switch circuit also includes a clamp circuit, an opening degree detection circuit and a control module, wherein the clamp circuit includes a clamp switch; the source of the NMOS switch tube is connected to the input end for inputting an input voltage, and the drain is connected to the output end for outputting an output voltage; the opening degree detection circuit includes a detection switch, a first detection PMOS tube, a second detection PMOS tube and a detection resistor; the source of the first detection PMOS tube is connected to the gate of the NMOS switch tube, the drain of the first detection PMOS tube is respectively connected to its own gate and the source of the second detection PMOS tube, the gate of the second detection PMOS tube is connected to the source of the NMOS switch tube, the drain is connected to one end of the detection resistor through the detection switch, and the other end of the detection resistor is grounded; The control method comprises the following steps: When it is necessary to control the NMOS switch tube to be turned off, the control module controls the clamp switch to be turned on, and the charge pump charges the gate of the NMOS switch tube with a maintenance current to turn on the clamp circuit. The clamp circuit uses the input voltage as a reference to clamp the gate of the NMOS switch tube at a voltage that makes the NMOS switch tube in a turned-off state; When it is necessary to control the NMOS switch tube to be turned on, the control module controls the clamp switch to be turned off so that the clamp circuit is turned off, the clamp circuit stops clamping the gate of the NMOS switch tube, and the charge pump charges the gate of the NMOS switch tube with a turn-on current to control the NMOS switch tube to be turned on, thereby outputting the output voltage; Wherein, the holding current is smaller than the start current.

14. A chip, characterized in that: A switch circuit comprising an NMOS switch tube as claimed in any one of claims 1 to 12.

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