A rapid thermal analysis method for chips based on advanced process packaging structure

Abstract

The present invention relates to integrated circuit thermal analysis technology, and proposes a fast thermal analysis method for chips based on advanced process packaging structure, including the following steps: Step 1: discretize the integrated circuit packaging structure first, and then build a thermal analysis system; Step 2: use LR-ADI to perform decomposition calculation; Step 3: perform SVD decomposition; Step 4: calculate the state space transfer matrix; Step 5: truncation processing; Step 6: construct a reduced-order thermal analysis model; Step 7: solve a group of differential equations; Step 8: calculate the core temperature of the chip. The present invention uses a model reduction method to perform thermal simulation, which effectively improves the operating efficiency while ensuring a certain accuracy, and achieves the purpose of temperature prediction and closed-loop simulation.

Description

Technical Field

[0001] The present invention relates to integrated circuit thermal analysis technology, which can be applied to EDA and dynamic temperature control management of chips. Background Art

[0002] Temperature is an important factor affecting chip performance. In a chip, when current flows through a conductor, Joule heat is inevitably generated. If the heat accumulation cannot be dissipated normally and in time, the temperature of the chip will rise sharply. If the temperature is too high, the high-energy carriers excited by overheating during operation of the integrated circuit will increase the probability of transistor breakdown and short circuit; transistor performance will change with temperature, and high temperature will cause some circuits to not work properly due to performance changes; high temperature increases electromigration, resulting in a decrease in the working life of the wire.

[0003] Contemporary 3D packaging technology and other innovative integrated packaging methods bring advantages while also raising some important thermal analysis issues, including thermal coupling effects, uneven temperature distribution, design restrictions on heat dissipation paths, selection of thermally conductive materials, and so on.

[0004] In order to ensure that the IC system will not damage the hardware structure due to high temperature during operation, dynamic thermal management technology is particularly important. In dynamic thermal management technology, power consumption, temperature, and dynamic control algorithms are integrated as a whole. The thermal analysis algorithm will perform rapid thermal simulation calculations based on real-time power consumption data at different locations, predict the temperature changes of various parts of the chip in the future, and then adjust the DVFS strategy for components that are about to exceed the temperature threshold in advance, thereby achieving the purpose of protecting the chip.

[0005] Recently, many integrated circuit thermal analysis methods have emerged in the field of thermal simulation, including steady-state and transient thermal analysis methods, especially thermal analysis methods for three-dimensional chips and system packaging. These methods can be mainly divided into two categories: analytical / semi-analytical methods and numerical methods.

[0006] Analytical / semi-analytical methods calculate the temperature distribution of integrated circuits by constructing a simplified thermal resistance network. Although the calculation complexity is lower, the accuracy is also lower.

[0007] The numerical method discretizes the integrated circuit heat conduction equation through the finite element method, finite volume method, finite difference method, etc., and then solves the discretized ordinary differential equations through direct method, iterative method and other methods. In practice, the numerical method is very accurate but the computational complexity is also high. This is usually caused by the excessive number of grids in the discretization process to ensure accuracy. But in fact, for the dynamic thermal temperature control process, only a few points in the chip, called hotspots, are concerned, and the temperature of all positions on the chip is not concerned. This gives the model reduction method a place to play.

[0008] There are two major categories of model reduction methods, the balance method based on singular value decomposition (SVD) and the moment matching method based on Krylov subspace theory. The moment matching method based on Krylov subspace theory has the advantages of small computational complexity and fast speed in the process of reducing the order of large dynamic systems, and can match several moments of the original system transfer function at a certain point. Through moment matching, the complexity of the system can be effectively reduced. However, this method has some defects. The most important one is that the stability of the reduced-order system cannot be guaranteed, and it is difficult to obtain the error range between the reduced-order system and the original system. The balance method is an order reduction method based on the concept of linear system theory. Its advantages are that it can maintain the structural characteristics of the reduced-order model and can perform truncation and reduction according to the size of the system singular values. Through the balance method, global error constraints can be set to control the accuracy of the reduced-order model. However, the balance method also has some disadvantages, especially when dealing with large dynamic systems, because it needs to solve two high-order Lyapunov equations, the computational complexity is high, and the computer memory requirements are also high. Summary of the invention

[0009] In order to solve the problem that the traditional numerical method is used for chip thermal simulation, the equation scale is too large and cannot be calculated quickly and effectively, and a fast thermal analysis method of the chip based on the advanced process packaging structure is proposed.

[0010] Technical solution:

[0011] A rapid thermal analysis method for a chip based on an advanced process packaging structure comprises the following steps:

[0012] Step 1: Discrete the integrated circuit packaging structure first, then build a thermal analysis system;

[0013] Step 2: Use LR-ADI to perform decomposition calculation;

[0014] Step 3: Perform SVD decomposition;

[0015] Step 4: Calculate the state space transfer matrix;

[0016] Step 5: truncation processing;

[0017] Step 6: Construct a reduced-order thermal analysis model;

[0018] Step 7: Solve the differential equations;

[0019] Step 8: Calculate the chip core temperature.

[0020] The present invention uses a model reduction method to perform thermal simulation, which effectively improves the operating efficiency while ensuring a certain accuracy, and achieves the purpose of temperature prediction and simulation closed loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The figure is a flow chart of a method according to an embodiment of the present invention.

[0022] Figure 2 These are some eigenvalues ​​used in the error analysis of the balanced truncation method in the test example of the present invention.

[0023] Figure 3 This is a temperature comparison diagram of the original system and the reduced-order system in the test example of the present invention. DETAILED DESCRIPTION

[0024] The present invention discloses a rapid thermal analysis method for a chip based on an advanced process packaging structure. On the basis of using the finite volume method, the packaging structure under the advanced process is further reduced in order, that is, the state space transfer matrix is ​​solved by the balanced truncation method. According to the error theory analysis, under the existing accuracy and speed constraints, the original RC network is projected to a low-order space by truncating the eigenvalue, so as to achieve model reduction and accelerate the operation.

[0025] The technical solution provided by the present application will be further described below in conjunction with specific embodiments and accompanying drawings. The advantages and features of the present application will become more apparent with the following description.

[0026] Example

[0027] A fast thermal analysis method for chips based on advanced process packaging structure, such as Figure 1 As shown, the steps are as follows:

[0028] Step 1: Discrete the integrated circuit package structure first, then build a thermal analysis system

[0029] Step 1.1 Use the finite volume method (FVM) to spatially discretize the packaging structure of the integrated circuit and obtain the following formula:

[0030]

[0031] Among them, G∈R n×n is the thermal conductivity matrix, symmetric and positive definite, which includes the equivalent thermal conductivity with respect to the boundary, x∈R n Represents the temperature of the entire field node, C∈R n×n is a matrix composed of the geothermal heat capacity, u(t)∈R p is the vector of current heat sources, E∈R n×p is the correlation matrix between the input heat sources and the node temperatures.

[0032] Note: Among them,

[0033] n represents the dimension of the system state space, that is, the number of summary points of the system after the chip is spatially discretized;

[0034] m represents the dimension of the output vector, that is, the number of hotspots;

[0035] p represents the dimension of the input vector, that is, the number of current heat source nodes.

[0036] For hotspots, the conversion can be performed as follows:

[0037] y(t)=Lx(t)

[0038] Where y∈R m Composed of the hotspot temperature, L∈R m×n is the association matrix between the state and the hotspot temperature.

[0039] Step 1.2 converts it into a "linear time-invariant" system equation (Linear Time-invariant, LTI) to construct a thermal analysis system, as shown in the following equation:

[0040]

[0041] Where A=-C -1 G, B = C -1 E.

[0042] Step 2: Decomposition calculation using LR-ADI

[0043] The balanced truncation method is used to specifically analyze the observation Gramian matrix Q and the arrival Gramian matrix P. First, the transformation projection of the state space is performed. Its solution is equivalent to solving the Lyapunov matrix equation, as follows:

[0044] AP+PA T +BB T =0,A T Q+QA+L T L=0

[0045] We further use the LR-ADI (Low Rank-Alternative Direction Implicit) method to solve the Lyapunov matrix equation and low-rank decomposition, that is, to solve P≈SS T With Q≈RR T .

[0046] Specifically, step 2 includes:

[0047] Step 2.1 Solve P≈SS T .

[0048] Step 2.1.1 Specify a set of shift parameters α1,…, With the residual tol.

[0049] Step 2.1.2 Initialize temporary variables S0=[], W0=B, i=1.

[0050] Step 2.1.3 Set the loop condition ‖W i-1 ‖2≥tol:

[0051] Step 2.1.4 Solve (A+α i I)V i =W i-1

[0052] Step 2.1.5 Let W i =W i-1 -2Re(α i )V i

[0053] Step 2.1.6:

[0054] Step 2.1.7 Let i = i + 1

[0055] Loop through steps 2.1.4-2.1.7 until the loop condition is no longer satisfied, that is, ‖W i-1 ‖2 <tol。

[0056] When i=s, the loop terminates and S is obtained. s .

[0057] Step 2.1.8 Let S = S s .

[0058] Step 2.2 Solve Q≈RR T .

[0059] Step 2.2.1 Specify a set of shift parameters α1,…, With the residual tol.

[0060] Step 2.2.2 Initialize temporary variables R0=[], W0=L, i=1.

[0061] Step 2.2.3 Set the loop condition ‖W i-1 ‖2≥tol:

[0062] Step 2.2.4 Solve (A+α i I)V i =W i-1

[0063] Step 2.2.5 Let W i =W i-1 -2Re(α i )V i

[0064] Step 2.2.6:

[0065] Step 2.2.7 Let i = i + 1

[0066] Loop through steps 2.2.4-2.2.7 until the loop condition is no longer satisfied, that is, ‖W i-1 ‖2 <tol。

[0067] When i=s, the loop ends and we get R s .

[0068] Step 2.2.8 Let R = R s .

[0069] Step 3: Perform SVD decomposition

[0070] Calculate the eigenvalue decomposition (SVD) with R T S=U∑V T , where Σ=diag(σ1,σ2,…,σ n ), σ i are the Hankel eigenvalues ​​(HSVs), which are important values ​​for error estimation in the balanced truncation method.

[0071] Step 4: Calculate the state space transfer matrix

[0072] The state space transfer matrix is ​​obtained Through the transfer matrix, the new system can be obtained The observation and arrival matrix

[0073] To perform a balanced conversion:

[0074] Step 5: Truncation Process

[0075] According to the error, truncation is performed to remove the states that are inconvenient to observe and control, and the projection matrix V is obtained. BT With W BT .

[0076]

[0077] I r Represents the identity matrix of order r

[0078] Step 6: Build a Reduced Order Thermal Analysis Model

[0079] The reduced order model (ROM) can be obtained. and

[0080] That is, the reduced-order system can be expressed as:

[0081]

[0082] in,

[0083] Step 7: Solve the differential equations

[0084] For solving the differential equations Directly using analytical solutions is not cost-effective in transient calculations in actual application scenarios. First, each moment of interest needs to be recalculated, which will consume a lot of computing resources. Second, the analytical solution requires the chip to reach a steady-state temperature value. In the scenario of dynamic temperature control, the temperature needs to be predicted based on the current different power consumption prediction values, which limits the application of analytical solutions. Therefore, the backward Euler method in the numerical solution is selected in the embodiment for solution.

[0085]

[0086] Here, Δt represents the time step.

[0087] For power density, by appropriately dividing the subdomains (time steps) on the time axis, its changes are limited to two cases, including u(t) remaining unchanged in the interval [t0, t0+Δt] and u(t) remaining unchanged in the interval [t0, t0+Δt). For these two cases, the integral results are the same, so the above formula is simplified as follows:

[0088]

[0089] The discrete iteration format is as follows:

[0090]

[0091] Solving the above linear equations, we can get the corresponding time

[0092] Step 8: Calculate Chip Core Temperature

[0093] The chip core temperature is

[0094] Test Case

[0095] This embodiment is further tested using MATLAB 2017b.

[0096] After using the finite volume method to spatially discretize the industrial integrated circuit example, a 59472-order thermal analysis system is formed, with 284 source terms. The order is reduced through the balanced truncation method and the LR-ADI method. The reduced-order thermal analysis system is 100-order, and 12 outputs are selected, all of which are core heat sources. Excluding the calculation preparation time, the time acceleration ratio is 182 times using the iterative method.

[0097] Figure 2 Indicates the Hankel eigenvalue used in the error analysis of this test case using the balanced truncation method;

[0098] Figure 3 The temperature comparison diagram of the original system and the reduced-order system shows that the average error is -0.6918%, which meets the analysis requirements.

[0099] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any changes or modifications made by any person skilled in the art based on the above disclosed technical contents shall be deemed as equivalent effective embodiments and shall fall within the scope of protection of the technical solution of the present application.

Claims

1. A rapid thermal analysis method for chips based on advanced process packaging structure, characterized in that: Includes steps: Step 1: Discrete the integrated circuit packaging structure first, then build a thermal analysis system; Step 2: Use LR-ADI to perform decomposition calculation; Step 3: Perform SVD decomposition; Step 4: Calculate the state space transfer matrix; Step 5: truncation processing; Step 6: Construct a reduced-order thermal analysis model; Step 7: Solve the differential equations; Step 8: Calculate the chip core temperature; The step 1 comprises: Step 1.1: Use the finite volume method FVM to spatially discretize the integrated circuit packaging structure and obtain the following formula: Among them, G∈R n×n is the thermal conductivity matrix, symmetric and positive definite, which includes the equivalent thermal conductivity with respect to the boundary, x∈R n Represents the temperature of the entire field node, C∈R n×n is a matrix composed of the geothermal heat capacity, u(t)∈R p is the vector of current heat sources, E∈R n×p is the correlation matrix between input heat sources and node temperatures; n represents the dimension of the system state space, that is, the number of summary points of the system after the chip is spatially discretized; m represents the dimension of the output vector, that is, the number of hotspots; p represents the dimension of the input vector, that is, the number of current heat source nodes; For hotspot, the conversion is performed as follows: y(t)=Lx(t) Where y∈R m Composed of the hotspot temperature, L∈R m×n is the association matrix between state and hotspot temperature; Step 1.2 converts it into a "linear time-independent" system equation to construct a thermal analysis system, as shown below: Where A=-C -1 G, B = C -1 E; Step 2: The balanced truncation method is used to specifically analyze the observation Gramian matrix Q and the arrival Gramian matrix P. First, the transformation projection of the state space is performed. Its solution is equivalent to solving the Lyapunov matrix equation, as follows: AP+PA T +BB T =0,A T Q+QA+L T L=0 The LR-ADI method is further used to solve the Lyapunov matrix equation and low-rank decomposition, that is, to solve P≈SS T With Q≈RR T ; Step 3: Calculate the eigenvalue decomposition SVD, with R T S=U∑V T , where Σ=diag(σ1,σ2,…,σ n ), σ i is the Hankel eigenvalue, which is an important value for error estimation in the balanced truncation method; Step 4: State Space Transfer Matrix Through the transfer matrix, we get the new system The observation and arrival matrix To perform a balanced conversion: Step 5: According to the error, truncation is performed to remove the states that are inconvenient to observe and control, and the projection matrix V is obtained. BT With W BT ; Where Ir represents the unit matrix of order r; Step 6: Downgrade system ROM, and That is, the reduced-order system is expressed as: in, Step 7: For solving the differential equations We choose to use the backward Euler method in the numerical solution to solve the problem. Among them, Δt represents the time step; For power consumption density, by appropriately dividing the sub-domain time steps on the time axis, its changes are limited to two cases, including u(t) remaining unchanged in the interval [t0, t0+Δt] and u(t) remaining unchanged in the interval [t0, t0+Δt); for these two cases, the integral results are consistent, so the above formula is simplified as follows: The discrete iteration format is as follows: Solve the above linear equations and get the corresponding time Step 8: The chip core temperature is 2. The method according to claim 1, characterized in that The step 2 comprises: Step 2.1 Solve P≈SS T Step 2.1.1 Specify a set of shift parameters and residual tol; Step 2.1.2 Initialize temporary variables S0 = [], W0 = B, o = 1; Step 2.1.3 Set the loop condition ‖W i-1 ‖2≥tol: Step 2.1.4 Solve (A+α i I)V i =W i-1 ; Step 2.1.5 Let W i =W i-1 -2Re(α i )V i ; Step 2.1.6: Step 2.1.7 Let o = o + 1 Loop through steps 2.1.4-2.1.7 until the loop condition is no longer satisfied, that is, ‖W i-1 ‖2 <tol; When i=s, the loop terminates and S is obtained. s ; Step 2.1.8 Let S = S s ; Step 2.2 Solve Q≈RR T Step 2.2.1 Specify a set of shift parameters and residual tol; Step 2.2.2 Initialize temporary variables R0 = [], W0 = L, i = 1; Step 2.2.3 Set the loop condition ‖W -1 ‖2≥tol: Step 2.2.4 Solve (A+α i I)V i =W i-1 ; Step 2.2.5 Let W i =W i-1 -2Re(α i )V i ; Step 2.2.6: Step 2.2.7 Let i = i + 1 Loop through steps 2.2.4-2.2.7 until the loop condition is no longer satisfied, that is, ‖W i-1 ‖2 <tol; When i=s, the loop ends and we get R s ; Step 2.2.8 Let R = R s .

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