Analog-to-digital converter and reference voltage providing circuit and processor thereof

Abstract

The present invention discloses an analog-to-digital converter and a reference voltage providing circuit and a processor thereof, wherein the reference voltage providing circuit comprises: a voltage providing unit, adapted to provide a first reference voltage; a buffer unit, adapted to buffer the first reference voltage and output a second reference voltage; a switching unit, configured to switch the second reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the high-order capacitor group of the analog-to-digital converter is switched, and to switch the first reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the low-order capacitor group of the analog-to-digital converter is switched. The circuit will not cause a significant drop in the voltage on the off-chip capacitor, and therefore will not cause a drop in the accuracy of the ADC.

Description

Technical Field

[0001] The present application relates to the technical field of analog-to-digital converters, and in particular to an analog-to-digital converter and a reference voltage providing circuit and a processor thereof. Background Art

[0002] ADC (Analog to Digital Converter), especially SAR ADC (Successive-Approximation Register ADC), is widely used in industry, measurement, automobile and other fields due to its low power consumption, high speed and high precision.

[0003] SAR ADC quantizes the input voltage by switching capacitors. During the capacitor switching process, the reference voltage needs to be accurate enough to ensure the accuracy of the SAR ADC successive approximation. However, during each capacitor switching process, the reference voltage will be disturbed. Therefore, in practical applications, high-precision ADC circuits usually need to use an off-chip capacitor (on the order of 10uF) to provide transient charge when the capacitor is switched, and the reference voltage providing circuit provides average current. When the capacitor is switched, the voltage on the off-chip capacitor drops, and the reference voltage providing circuit takes a long time to replenish the charge to the off-chip capacitor, which causes the reference voltage to drop, resulting in a decrease in the accuracy of the ADC. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art to at least a certain extent. To this end, the first purpose of the present invention is to provide a reference voltage providing circuit for an analog-to-digital converter, since each ADC sampling channel is provided with a redundant bit capacitor, the reference voltage does not need to be very accurate, when the high-bit capacitor group is switched, the buffer unit provides charge to the ADC sampling channel, and when the low-bit capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel, which will not cause a significant drop in the voltage on the off-chip capacitor, and therefore will not cause a decrease in the accuracy of the ADC.

[0005] A second objective of the present invention is to provide an analog-to-digital converter.

[0006] The third objective of the present invention is to provide a processor.

[0007] To achieve the above-mentioned purpose, according to an embodiment of the first aspect of the present invention, a reference voltage providing circuit of an analog-to-digital converter is proposed, comprising: a voltage providing unit, suitable for providing a first reference voltage; a buffer unit, suitable for buffering the first reference voltage and outputting a second reference voltage; a switching unit, configured to switch the second reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the high-order capacitor group of the analog-to-digital converter is switched, and to switch the first reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the low-order capacitor group of the analog-to-digital converter is switched.

[0008] The reference voltage providing circuit of the analog-to-digital converter according to the embodiment of the present invention comprises a voltage providing unit, a buffer unit and a switching unit, wherein the switching unit is configured to switch the second reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the high-order capacitor group of the analog-to-digital converter is switched, and switch the first reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the low-order capacitor group of the analog-to-digital converter is switched. Therefore, since each ADC sampling channel is provided with redundant position capacitors, when the high-order capacitor group is switched, the reference voltage does not need to be very accurate, and the buffer unit provides charge to the ADC sampling channel, and when the low-order capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel. Since the capacitance of the low-order capacitor group is small, the charge required by the low-order capacitor group is small, and the voltage on the off-chip capacitor will not be greatly reduced, so the accuracy of the ADC will not be reduced.

[0009] According to one embodiment of the present invention, the switching unit includes: a first switching switch and a second switching switch, the first end of the first switching switch is connected to the output end of the buffer unit, the first end of the second switching switch is connected to the output end of the voltage providing unit, and the second end of the first switching switch is connected to the second end of the second switching switch to form a first node, and the first node is the output end of the reference voltage providing circuit.

[0010] According to one embodiment of the present invention, when the first switching switch is closed and the second switching switch is open, the second reference voltage provides charge to the ADC sampling channel; when the first switching switch is open and the second switching switch is closed, the first reference voltage provides charge to the ADC sampling channel.

[0011] According to one embodiment of the present invention, the buffer unit includes: a buffer, a first input end of the buffer is connected to the output end of the voltage providing unit, a second input end of the buffer is connected to the output end of the buffer, and the output end of the buffer serves as the output end of the buffer unit.

[0012] According to one embodiment of the present invention, a voltage providing unit includes: a bandgap reference; a first resistor, one end of which is connected to the bandgap reference; an off-chip capacitor, one end of which is grounded, and the other end of which is connected to the other end of the first resistor and serves as the output end of the voltage providing unit.

[0013] According to an embodiment of the present invention, when there are multiple ADC sampling channels, there are multiple switching units and multiple buffer units, and each ADC sampling channel corresponds to one switching unit and one buffer unit.

[0014] According to an embodiment of the present invention, the bandgap reference, the first resistor, each switching unit and each buffer unit are respectively integrated into a chip of the analog-to-digital converter.

[0015] According to one embodiment of the present invention, the analog-to-digital converter also includes an auxiliary ADC sampling channel, and the auxiliary ADC sampling channel corresponds to an auxiliary capacitor array. After the auxiliary ADC sampling channel obtains a comparison result based on capacitor switching of the auxiliary capacitor array, the comparison result is loaded into the ADC sampling channel as a high-bit comparison result of the ADC sampling channel.

[0016] According to one embodiment of the present invention, in the process of the auxiliary ADC sampling channel loading the comparison result into the ADC sampling channel, the second reference voltage provides charge to the ADC sampling channel.

[0017] According to an embodiment of the present invention, the capacitance value of the auxiliary capacitor array is smaller than the capacitance value of the capacitor array of the analog-to-digital converter.

[0018] According to an embodiment of the present invention, the capacitance of the redundant capacitor of the analog-to-digital converter is between the capacitance of the last capacitor in the high-order capacitor group and the capacitance of the first capacitor in the low-order capacitor group.

[0019] To achieve the above objective, an analog-to-digital converter is provided according to a second aspect of the present invention, comprising a reference voltage providing circuit according to any one of the above embodiments.

[0020] According to the analog-to-digital converter of the embodiment of the present invention, by adopting the above-mentioned reference voltage providing circuit, since each ADC sampling channel is provided with redundant position capacitors, the reference voltage does not need to be very accurate. When the high-order capacitor group is switched, the buffer unit provides charge to the ADC sampling channel, and when the low-order capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel, which will not cause a significant drop in the voltage on the off-chip capacitor, and therefore will not cause a decrease in the accuracy of the ADC.

[0021] To achieve the above objective, a processor is proposed according to a third aspect of the present invention, comprising the aforementioned analog-to-digital converter.

[0022] According to the processor of the embodiment of the present invention, by adopting the above-mentioned analog-to-digital converter, since each ADC sampling channel is provided with redundant position capacitors, the reference voltage does not need to be very precise. When the high-order capacitor group is switched, the buffer unit provides charge to the ADC sampling channel, and when the low-order capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel, which will not cause a significant drop in the voltage on the off-chip capacitor, and therefore will not cause a decrease in the accuracy of the ADC.

[0023] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a circuit diagram of a SAR ADC in the related art;

[0025] Figure 2 Schematic diagram of voltage on the upper plate of the capacitor array of the SAR ADC in the related art;

[0026] Figure 3 is a circuit diagram of a reference voltage circuit of a SAR ADC in the related art;

[0027] Figure 4 is a curve showing a voltage variation across an off-chip capacitor of a SAR ADC in the related art;

[0028] Figure 5 is a schematic diagram of the ringing of a SAR ADC in the related art;

[0029] Figure 6 is a circuit diagram of an analog-to-digital converter according to an embodiment of the present invention;

[0030] Figure 7 is a schematic structural diagram of a reference voltage providing circuit according to an embodiment of the present invention;

[0031] Figure 8 is a circuit diagram of a buffer unit and a switching unit according to an embodiment of the present invention;

[0032] Fig. 9 is a schematic structural diagram of a voltage providing unit and a plurality of ADC sampling channels according to an embodiment of the present invention;

[0033] Fig.10 is a circuit diagram of an auxiliary ADC sampling channel according to an embodiment of the present invention;

[0034] Fig.11 is a circuit diagram of an auxiliary ADC sampling channel and an ADC sampling channel according to an embodiment of the present invention;

[0035] Fig.12 is a system schematic diagram of an analog-to-digital converter according to an embodiment of the present invention;

[0036] Fig.13 is a system diagram of a processor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0038] It should be noted that this application is made based on the inventor's understanding and research of the following issues:

[0039] like Figure 1 As shown, the SAR ADC includes a capacitor array 10, wherein the capacitors C1:C2:C3:...:Cn in the capacitor array 10 are equal to 1024:512:256:...:1, and the lower plate of the capacitor array 10 is connected to a reference voltage vref or a ground gnd. By switching each capacitor in the capacitor array 10 to connect to the reference voltage vref or the ground gnd, the voltage of the upper plate of the capacitor array 10 is changed as follows: Figure 2 As shown in the change, the MSB (Most Significant Bit) is the highest bit capacitor, that is, capacitor C1, and the MSB-1 is the second highest bit capacitor, that is, capacitor C2, and so on, thereby generating a quantization result.

[0040] Therefore, during the capacitor switching process, the reference voltage vref needs to be accurate enough to ensure the accuracy of the SAR ADC successive approximation. In actual applications, each capacitor switching will cause a disturbance to the reference voltage vref. Usually, this disturbance needs to be restored in the next comparison. For example, it needs to be restored to within the voltage range of 1 lsb within 10ns. For a 16-bit ADC, taking the reference voltage vref as 4.4V as an example, the reference voltage vref needs to be restored to 4.4V / 2 within 10ns. 16 = 67uV. Currently, few amplifiers can achieve such a high bandwidth (or the power consumption needs to be very large) to allow the reference voltage vref to be established to a sufficient accuracy in the order of 10ns.

[0041] Therefore, high-precision ADC circuits in practical applications, such as Figure 3As shown, an off-chip capacitor C (on the order of 10uF) is usually required to provide transient charge when the capacitor is switched; the reference voltage circuit 40 is usually a buffer that provides average current, and its output impedance R needs to be small enough to avoid slow recovery of the reference voltage during the successive approximation conversion process.

[0042] Although the off-chip capacitor C can provide transient current during the successive approximation process, the capacitance of the off-chip capacitor C cannot be infinite. In the successive approximation ADC, the capacitance of the high-order capacitor is relatively large, so during the high-order capacitor switching process, more transient current will be drawn from the off-chip capacitor C, causing the voltage on the capacitor to drop. The buffer bandwidth in the reference voltage circuit 40 is limited, and its output impedance R cannot be infinitely small. It takes a long time to replenish the charge to the off-chip capacitor C.

[0043] Assuming that the capacitor switched by the ADC is C_ADC, after the switching is completed, the voltage VC across the off-chip capacitor C is calculated according to the following formula (1):

[0044]

[0045] like Figure 4 As shown, assuming that the off-chip capacitor C is 10uF, if the capacitance of the MSB (i.e., capacitor C1) is 20pF, when the first capacitor C1 is switched, C_ADC=20pF, and the voltage VC across the off-chip capacitor C will drop to 99.9998% of the reference voltage vref. For multiple ADC sampling channels 100 switched at the same time, the voltage VC across the off-chip capacitor C will drop more proportionally; and, for multiple ADC sampling channels 100, since different channels will be connected to different input signals vin, the flipping of the highest-order capacitor is different, which will cause the voltage VC across the off-chip capacitor C to drop differently. Therefore, different channels will interfere with each other due to the change of the voltage VC across the off-chip capacitor C, and since the routing from each channel to the off-chip capacitor C is also different, the gain error on each channel is also different.

[0046] In addition, when the off-chip capacitor C is connected to the chip, there will be the effect of parasitic capacitance caused by chip bonding. When the capacitor is switched, the on-chip voltage will produce Figure 5 The larger the capacitance being switched, the greater the amplitude of the ringing will be and the longer it will take to stabilize.

[0047] Therefore, in the related art, the reference voltage circuit of the SAR ADC uses an off-chip capacitor to provide transient charge, and the reference voltage circuit provides average current. When the capacitor is switched, the voltage on the off-chip capacitor will drop, and the bandwidth of the reference voltage circuit is small, so it takes a long time to replenish the off-chip capacitor, resulting in a decrease in the accuracy of the final ADC; and when the high-order capacitor is switched, the internal voltage will also produce ringing, which will also cause a decrease in ADC accuracy. When the ADC has multiple channels, interference will occur between channels due to the gain error of each channel.

[0048] Based on this, an embodiment of the present invention provides an analog-to-digital converter and a reference voltage providing circuit and processor thereof. Since each ADC sampling channel is provided with redundant position capacitors, the reference voltage does not need to be very precise. When the high-order capacitor group is switched, the buffer unit provides charge to the ADC sampling channel, and when the low-order capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel, which will not cause a significant drop in the voltage on the off-chip capacitor, and therefore will not cause a decrease in the accuracy of the ADC.

[0049] The analog-to-digital converter and its reference voltage providing circuit and processor according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0050] Figure 6 is a circuit diagram of an analog-to-digital converter according to an embodiment of the present invention. Figure 6 As shown, the analog-to-digital converter includes at least one ADC sampling channel 100 , each ADC sampling channel 100 is provided with a capacitor array 10 and a redundant capacitor Cr, and the redundant capacitor Cr is suitable for dividing the capacitor array 10 into a high-order capacitor group 11 and a low-order capacitor group 12 .

[0051] Specifically, the ratio of the capacitors in the capacitor array 10 is 2. Figure 6 As shown in the figure, for example, a redundant capacitor Cr is added between the fifth capacitor C5 and the sixth capacitor C6, the upper plates of the capacitor array 10 and the redundant capacitor Cr are connected to the positive input terminal of the comparator 20, the upper plates of the capacitor array 10 and the redundant capacitor Cr are connected to the reference voltage vref or the ground gnd, and the capacitors C1-C5 of the high-order capacitor group 11 are also suitable for connecting the input signal vin. The negative input terminal of the comparator 20 is suitable for inputting the common mode voltage vcm, the positive input terminal and the negative input terminal of the comparator 20 are provided with a switch S, and the output terminal of the comparator 20 is connected to the control unit 30. The control unit 30 is configured to switch the capacitors C1-Cn in the capacitor array 10 and the redundant capacitor Cr to connect the reference voltage vref or the ground gnd, so that the voltage of the upper plate of the capacitor array 10 changes.

[0052] In the sampling phase, the switch S is closed, the capacitors C1-C5 of the high-order capacitor group 11 are connected to the input signal vin, and the remaining capacitors are connected to the ground gnd. It should be noted that when sampling is performed, it is not limited to the following. Figure 6 The sampling method shown can also connect all capacitors C1-Cn in the capacitor array 10 to the input signal vin. After the sampling is completed, the switch S is turned off, and the connection between the capacitors of the high-order capacitor group 11 and the input signal vin is disconnected.

[0053] In the conversion stage, first, the lower plate of the MSB capacitor (i.e., capacitor C1) is connected to the reference voltage vref, and the lower plates of the remaining capacitors are grounded to gnd. The voltage of the upper plate of the capacitor array 10 is vcm-vin+vref / 2, the positive input voltage of the comparator 20 is vcm-vin+vref / 2, and the negative input voltage of the comparator 20 is vcm. If vcm-vin+vref / 2-vcm>0, the output result of the comparator 20 is 1, and the control unit 30 switches the lower plate of the MSB capacitor (i.e., capacitor C1) to the ground gnd, so the first bit is 0; if vcm-vin+vref / 2-vcm≤0, the output result of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the MSB capacitor (i.e., capacitor C1) connected to the reference voltage vref, so the first bit is 1.

[0054] Then the lower plate of the capacitor of MSB-1 (i.e., capacitor C2) is connected to the reference voltage vref. If the lower plate of the capacitor of MSB (i.e., capacitor C1) is grounded to gnd, the voltage of the upper plate of the capacitor array 10 is vcm-vin+vref / 4, and the negative input voltage of the comparator 20 is vcm. If vcm-vin+vref / 4-Vcm>0, the output result of the comparator 20 is 1, and the control unit 30 switches the lower plate of the capacitor of MSB-1 (i.e., capacitor C2) to the ground gnd, so the second bit is 0; if vcm-vin+vref / 4-vcm≤0, the output result of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the capacitor of MSB-1 (i.e., capacitor C2) connected to the reference voltage vref, so the second bit is 0. If the lower plate of the MSB capacitor (i.e., capacitor C1) is connected to the reference voltage vref, the voltage of the upper plate of the capacitor array 10 is vcm-vin+vref / 2+vref / 4, and the negative input voltage of the comparator 20 is vcm. If vcm-vin+vref / 2+vref / 4-vcm>0, the output result of the comparator 20 is 1, and the control unit 30 switches the lower plate of the MSB-1 capacitor (i.e., capacitor C2) to ground gnd, so the second bit is 0; if vcm-vin+vref / 2+vref / 4-vcm≤0, the output result of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the MSB-1 capacitor (i.e., capacitor C2) connected to the reference voltage vref, so the second bit is 0. The comparison process of the latter capacitors is the same as the comparison process of the MSB capacitor (i.e., capacitor C1) and the MSB-1 capacitor (i.e., capacitor C2), and will not be repeated here.

[0055] A redundant capacitor Cr is added to the ADC sampling channel 100 so that the ratio of the capacitors in the capacitor array 10 is less than 2. After adding the redundant capacitor Cr, if there is a problem in the conversion process of the high-order capacitor group 11, the redundant capacitor Cr can remedy the result to obtain a correct output.

[0056] For example, there is no redundant bit capacitor Cr in the capacitor array 10, and there are four capacitors in the capacitor array 10, and the weights of the four capacitors are 8, 4, 2, and 1. If the digital code output by the control unit 30 according to the comparison result of the comparator 20 is 1000, it is restored to the value 1*8+0*4+0*2+0*1=8 after digital conversion. When the first digital code is wrong, the output digital code will become 0111, and it is restored to the value 0*8+1*4+1*2+1*1=7 after digital conversion. Therefore, the numerical value after digital conversion differs by 1, and the result output by the control unit 30 is wrong. There is a redundant capacitor Cr in the capacitor array 10, and the redundant capacitor Cr is located between the second capacitor C2 and the third capacitor C3. When the capacitance of the redundant capacitor Cr is the second capacitor C2, the weights of the five capacitors are 8, 4, 4, 2, and 1. When there is no error in the conversion process, the digital code output by the control unit 30 is 10000, which is restored to the value 1*8+0*4+0*4+0*2+0*1=8 after digital conversion. When the first digital code is wrong, the output digital code will become 01111, which is restored to the value 0*8+1*4+1*4+0*2+0*1=8 after digital conversion. Therefore, the numerical values ​​after digital conversion are the same, and the control unit 30 can obtain the correct result.

[0057] It should be noted that the position of the redundant capacitor Cr is not limited to Figure 6 The number of redundant capacitors Cr is not limited to one, but may be multiple, and the multiple redundant capacitors Cr are located at different positions. For example, there are two redundant capacitors Cr, one of which is located between the fifth capacitor C5 and the sixth capacitor C6, and the other is located between the n-1 capacitor Cn-1 and the n-th capacitor Cn. The more redundant capacitors Cr in the capacitor array 10, the greater the redundancy of the ADC, and the greater the fault tolerance, which can be set according to actual conditions. After adding the redundant capacitors Cr, the weights of the capacitor array 10 and the redundant capacitors Cr are not limited to binary, but may be other values, which are not specifically limited here.

[0058] In the above embodiment, after adding redundant bit capacitors, a value has different digital codes, thereby achieving the function of error correction. Therefore, after adding redundant bit capacitors, when the capacitors in the high-bit capacitor group are switched, the reference voltage does not need to be very accurate.

[0059] Figure 7 FIG. 1 is a schematic diagram of a reference voltage providing circuit according to an embodiment of the present invention. Figure 7 As shown, the reference voltage providing circuit 200 includes: a voltage providing unit 50 , a buffer unit 60 and a switching unit 70 .

[0060] Among them, the voltage providing unit 50 is suitable for providing a first reference voltage vref1; the buffer unit 60 is suitable for buffering the first reference voltage vref1 and outputting a second reference voltage vref2; the switching unit 70 is configured to switch the second reference voltage vref2 to provide charge to the ADC sampling channel 100 of the analog-to-digital converter when the high-order capacitor group 11 of the analog-to-digital converter is switched, and to switch the first reference voltage vref1 to provide charge to the ADC sampling channel 100 of the analog-to-digital converter when the low-order capacitor group 12 of the analog-to-digital converter is switched.

[0061] Specifically, the buffer unit 60 can also provide charge to the ADC sampling channel 100, but the bandwidth of the buffer unit 60 is limited, and the charge provided by the buffer unit 60 cannot meet the actual needs of the ADC sampling channel 100. Therefore, when the buffer unit 60 provides charge, the reference voltage vref will change. However, since the redundant position capacitor Cr is provided in the capacitor array 10, when the capacitors in the high-position capacitor group 11 are switched, the reference voltage vref does not need to be very accurate, so the second reference voltage vref2 can be switched to provide charge to the ADC sampling channel 100. When the low-position capacitor group 12 is switched, there is no redundant position capacitor Cr, so a precise reference voltage vref is required, so the first reference voltage vref1 is switched to provide charge to the ADC sampling channel 100, but the capacitance of the low-position capacitor group 12 is small, so the charge required by the low-position capacitor group 12 is small, and the voltage on the off-chip capacitor C will not drop significantly.

[0062] It should be noted that when the redundant bit capacitor Cr is switched, the switching unit 70 switches the first reference voltage vref1 to provide charges to the ADC sampling channel 100 .

[0063] For example, Figure 6As shown in the example, if the redundant bit capacitance Cr is equal to the fifth capacitance C5, in the conversion phase, when the first capacitance C1-fifth capacitance C5 are switched, the switching unit 70 switches the second reference voltage vref2 to provide charge to the ADC sampling channel 100. First, the lower plate of the MSB capacitor (i.e., capacitor C1) is connected to the second reference voltage vref2, and the lower plates of the remaining capacitors are grounded to gnd. The voltage of the upper plate of the capacitor array 10 is vcm-vin+vref / 2, the positive input voltage of the comparator 20 is vcm-vin+vref / 2, and the negative input voltage of the comparator 20 is vcm. If vcm-vin+vref / 2-vcm>0, the output result of the comparator 20 is 1, and the control unit 30 switches the lower plate of the MSB capacitor (i.e., capacitor C1) to the ground gnd, so the first bit is 0; if vcm-vin+vref / 2-vcm≤0, the output result of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the MSB capacitor (i.e., capacitor C1) connected to the second reference voltage vref2, so the first bit is 1. The switching process of the second capacitor C5-fifth capacitor is similar to the switching process of the first capacitor C1, and will not be repeated here.

[0064] When the redundant capacitor Cr and the capacitors in the low-order capacitor group 12 are switched, the switching unit 70 switches the first reference voltage vref1 to provide charge to the ADC sampling channel 100. First, the lower plate of the MSB capacitor (i.e., capacitor C1) is connected to the first reference voltage vref1, and the lower plates of the remaining capacitors are grounded to gnd. The voltage of the upper plate of the capacitor array 10 is the voltage of the fifth capacitor C5 after comparison plus vref / 2. 5 If the output result of the comparator 20 is 1, the control unit 30 switches the lower plate of the redundant bit capacitor Cr to the ground gnd. If the output result of the comparator 20 is 0, the control unit 30 keeps the lower plate of the redundant bit capacitor Cr connected to the first reference voltage vref1. The subsequent switching process is similar to the switching process of the redundant bit capacitor Cr, which will not be repeated here.

[0065] In the above embodiment, since each ADC sampling channel is provided with redundant capacitors, when the high-order capacitor group is switched, the reference voltage does not need to be very precise, and the second reference voltage provides charge to the ADC sampling channel, and when the low-order capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel. Since the capacitance of the low-order capacitor group is smaller, the charge required for the low-order capacitor group is less, which will not cause a significant drop in the voltage on the off-chip capacitor, and therefore will not cause a decrease in the accuracy of the ADC.

[0066] In some embodiments, Figure 8As shown, the switching unit 70 includes: a first switching switch SW1 and a second switching switch SW2, the first end of the first switching switch SW1 is connected to the output end of the buffer unit 60, the first end of the second switching switch SW2 is connected to the output end of the voltage providing unit 50, and the second end of the first switching switch SW1 is connected to the second end of the second switching switch SW2 to form a first node J1, and the first node J1 is the output end of the reference voltage providing circuit 200.

[0067] It can be understood that the switching unit 70 can change the states of the first switch SW1 and the second switch SW2 according to the comparison process, thereby switching the output of the first reference voltage vref1 or the second reference voltage vref2.

[0068] Further, in some embodiments, when the first switching switch SW1 is closed and the second switching switch SW2 is open, the second reference voltage vref2 provides charge to the ADC sampling channel 100; when the first switching switch SW1 is open and the second switching switch SW2 is closed, the first reference voltage vref1 provides charge to the ADC sampling channel 100.

[0069] Specifically, when the capacitors in the high-order capacitor group 11 are switched, the first switching switch SW1 is closed and the second switching switch SW2 is disconnected, the output end of the buffer unit 60 is connected to the first node J1, and the second reference voltage vref2 provides charge to the ADC sampling channel 100; when the capacitors in the low-order capacitor group 12 are switched, the first switching switch SW1 is disconnected and the second switching switch SW2 is closed, the output end of the voltage providing unit 50 is connected to the first node J1, and the first reference voltage vref1 provides charge to the ADC sampling channel 100 to achieve an accurate comparison process.

[0070] In the above embodiment, by changing the switch states of the first switch and the second switch in the switching unit, the switching buffer unit or the voltage supply unit is connected to the ADC sampling channel, thereby providing charge to the ADC sampling channel using different reference voltages.

[0071] In some embodiments, Figure 8 As shown, the buffer unit 60 includes: a buffer 61, a first input end of the buffer 61 is connected to the output end of the voltage providing unit 50, a second input end of the buffer 61 is connected to the output end of the buffer 61, and the output end of the buffer 61 serves as the output end of the buffer unit 60.

[0072] Specifically, the first input terminal of the buffer 61 is suitable for inputting the first reference voltage vref1. When the first switch SW1 is closed and the second switch SW2 is open, the buffer 61 generates the second reference voltage vref2 according to the first reference voltage vref1 and provides the second reference voltage vref2 to the ADC sampling channel 100.

[0073] In some embodiments, Fig. 9 As shown, the voltage providing unit 50 includes: a bandgap reference 51, a first resistor R1 and an off-chip capacitor C, wherein one end of the first resistor R1 is connected to the bandgap reference 51; one end of the off-chip capacitor C is grounded gnd, and the other end of the off-chip capacitor C is connected to the other end of the first resistor R1 and serves as the output end of the voltage providing unit 50.

[0074] Specifically, since there is no redundant capacitor Cr after the low-order capacitor group 12, when the capacitors in the low-order capacitor group 12 of the ADC sampling channel 100 are switched, the off-chip capacitor C is still required to provide charge, thereby improving the accuracy of the reference voltage. When the first switching switch SW1 is disconnected and the second switching switch SW2 is closed, the off-chip capacitor C provides charge to the ADC sampling channel 100.

[0075] In the above embodiment, when the capacitors in the high-order capacitor group are switched, charges are provided by the second reference voltage of the buffer unit without using off-chip capacitors, and therefore, no ringing occurs; and when the capacitors in the low-order capacitor group are switched, because the capacitors in the low-order capacitor group are smaller, the voltage across the off-chip capacitor drops less, and the amplitude of the ringing is also smaller, thereby further improving the accuracy of the ADC.

[0076] In some embodiments, Fig. 9 As shown, when there are multiple ADC sampling channels 100 , there are multiple switching units 70 and multiple buffer units 60 , respectively, and each ADC sampling channel 100 corresponds to one switching unit 70 and one buffer unit 60 .

[0077] It can be understood that each ADC sampling channel 100 corresponds to a switching unit 70 and a buffer unit 60, so that each ADC sampling channel 100 uses the charge provided by the corresponding buffer unit 60 when performing capacitor switching. Therefore, multiple ADC sampling channels 100 will not interfere with each other, thereby further improving the accuracy of the ADC.

[0078] In some embodiments, Fig. 9 As shown, the bandgap reference 51 , the first resistor R1 , each switching unit 70 , and each buffer unit 60 are respectively integrated in the chip 300 of the analog-to-digital converter.

[0079] That is, except for the off-chip capacitor C, the remaining circuits are integrated in the chip 300 of the analog-to-digital converter. Therefore, when the second reference voltage vref2 provides charges to the ADC sampling channel 100, the buffer unit 60 will not generate ringing.

[0080] In some embodiments, Fig.10 and Fig.11 As shown, the analog-to-digital converter also includes an auxiliary ADC sampling channel 400, and the auxiliary ADC sampling channel 400 corresponds to an auxiliary capacitor array 80. After the auxiliary ADC sampling channel 400 obtains a comparison result based on the capacitor switching of the auxiliary capacitor array 80, the comparison result is loaded into the ADC sampling channel 100 as a high-bit comparison result of the ADC sampling channel 100.

[0081] Specifically, the auxiliary ADC sampling channel 400 has a similar structure to the ADC sampling channel 100, except that the auxiliary capacitor array 80 of the auxiliary ADC sampling channel 400 only has high-order capacitors C1s-C5s. Figure 7 As shown in the figure, the redundant capacitor Cr is set between the fifth capacitor C5 and the sixth capacitor C6. Fig.10 As shown, the auxiliary capacitor array 80 has only five capacitors. The auxiliary ADC sampling channel 400 and the ADC sampling channel 100 work in the same manner.

[0082] It should be noted that the auxiliary ADC sampling channel 400 also corresponds to a switching unit 60 and a buffer unit 70 , so that the auxiliary ADC sampling channel 400 will not interfere with the ADC sampling channel 100 when the capacitor is switched.

[0083] In the sampling phase, the auxiliary ADC sampling channel 400 and the ADC sampling channel 100 are sampled at the same time, that is, the switch S of the auxiliary ADC sampling channel 400 and the switch S of the ADC sampling channel 100 are closed at the same time, the lower plate of the auxiliary capacitor array 80 is connected to the input signal vin, and the capacitors C1-C5 or the capacitor array 10 in the high-order capacitor group 11 in the ADC sampling channel 100 are connected to the input signal vin for sampling. After the sampling is completed, the switch S of the auxiliary ADC sampling channel 400 and the switch S of the ADC sampling channel 100 are opened at the same time, the lower plate of the auxiliary capacitor array 80 is disconnected from the input signal vin, and the capacitors C-C5 or the capacitor array 10 in the high-order capacitor group 11 in the ADC sampling channel 100 are disconnected from the input signal vin.

[0084] During the conversion phase, the auxiliary ADC sampling channel 400 works in the same manner as the ADC sampling channel 100. The first switch SW1 of the switching unit 70 is closed and the second switch SW2 is open, and the second reference voltage vref2 provides charge to the auxiliary ADC sampling channel 400. First, the lower plate of the MSB capacitor (i.e., capacitor C1s) is connected to the second reference voltage vref2, and the lower plates of the remaining capacitors C2s-C5s are grounded. The voltage of the upper plate of the auxiliary capacitor array 80 is vcm-vin+vref / 2, the positive input voltage of the comparator is vcm-vin+vref / 2, and the negative input voltage of the comparator is vcm. If vcm-vin+vref / 2-vcm>0, the comparator output result is 1, and the control unit switches the lower plate of the MSB capacitor (i.e., capacitor C1s) to the ground gnd, so the first bit is 0; if vcm-vin+vref / 2-vcm≤0, the comparator output result is 0, and the control unit keeps the lower plate of the MSB capacitor (i.e., capacitor C1s) connected to the second reference voltage vref2, so the first bit is 1. Then the lower plate of the capacitor of MSB-1 (i.e., capacitor C2) is connected to the second reference voltage vref2. If the lower plate of the capacitor of MSB (i.e., capacitor C1) is grounded to gnd, the voltage of the upper plate of the capacitor array 10 is vcm-vin+vref / 4, and the negative input voltage of the comparator 20 is vcm. If vcm-vin+vref / 4-Vcm>0, the output result of the comparator 20 is 1, and the control unit 30 switches the lower plate of the capacitor of MSB-1 (i.e., capacitor C2) to the ground gnd, so the second bit is 0; if vcm-vin+vref / 4-vcm≤0, the output result of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the capacitor of MSB-1 (i.e., capacitor C2s) connected to the second reference voltage vref2, so the second bit is 0. If the lower plate of the capacitor of the MSB (i.e., capacitor C1s) is connected to the second reference voltage vref2, the voltage of the upper plate of the capacitor array 10 is vcm-vin+vref / 2+vref / 4, and the voltage of the negative input terminal of the comparator 20 is vcm. If vcm-vin+vref / 2+vref / 4-vcm>0, the output result of the comparator 20 is 1, and the control unit 30 switches the lower plate of the capacitor of MSB-1 (i.e., capacitor C2s) to ground gnd, so the second bit is 0; if vcm-vin+vref / 2+vref / 4-vcm≤0, the output result of the comparator 20 is 0, and the control unit 30 keeps the lower plate of the capacitor of MSB-1 (i.e., capacitor C2s) connected to the second reference voltage vref2, so the second bit is 0.The subsequent capacitor comparison process is the same as the comparison process of the MSB capacitor (ie, capacitor C1s) and the MSB-1 capacitor (ie, capacitor C2s), and will not be repeated here. This process is repeated in the same way until all capacitors C1s-C5s in the auxiliary capacitor array 80 are switched.

[0085] After all the capacitors C1s-C5s in the auxiliary capacitor array 80 are switched, the auxiliary ADC sampling channel 400 loads all the comparison results to the ADC sampling channel 100 as the high-order comparison result of the ADC sampling channel 100. For example, if the comparison result of the auxiliary ADC sampling channel 400 is 10000, the lower plate of the first capacitor C1s of the auxiliary capacitor array 80 is connected to the second reference voltage vref2, the lower plates of the second capacitor C2s-fifth capacitor C5s are all grounded to gnd, and the high-order capacitor group 11 of the ADC sampling channel 100 switches the capacitor connections in the high-order capacitor group 11 according to the comparison result, the lower plate of the first capacitor C1 is connected to the first reference voltage vref1, and the lower plates of the second capacitor C2-fifth capacitor C5 are all grounded to gnd.

[0086] The first switch SW1 of the switching unit 70 is disconnected, and the second switch SW2 is closed, and the first reference voltage vref1 provides charge to the ADC sampling channel 100. The ADC sampling channel 100 starts to convert from the redundant bit capacitor Cr, connects the lower plate of the redundant bit capacitor Cr to the first reference voltage vref1, and the lower plate of the capacitor in the low-order capacitor group 12 is grounded gnd. If the comparator output result is 1, the control unit switches the lower plate of the redundant bit capacitor Cr to the ground gnd, and connects the lower plate of the first capacitor C6 in the low-order capacitor group 12 to the first reference voltage vref1 for the next comparison; if the comparator output result is 0, the control unit keeps the lower plate of the redundant bit capacitor Cr connected to the first reference voltage vref1, and connects the lower plate of the first capacitor C6 in the low-order capacitor group 12 to the first reference voltage vref1 for the next comparison.

[0087] In an optional embodiment, if Fig.11 As shown, the auxiliary ADC sampling channel 400 directly loads the comparison result of the auxiliary capacitor array 80 onto the high-order capacitor group 11 of the ADC sampling channel 100 to control whether the lower plate of the capacitor in the high-order capacitor group 11 is connected to the first reference voltage vref1 or the ground gnd. The auxiliary ADC sampling channel 400 can also send the comparison result to the control unit 30 of the ADC sampling channel 100 through the control unit of the auxiliary ADC sampling channel 400, and the control unit 30 of the ADC sampling channel 100 controls whether the lower plate of the capacitor in the high-order capacitor group 11 is connected to the first reference voltage vref1 or the ground gnd according to the comparison result.

[0088] In some embodiments, during the process of the auxiliary ADC sampling channel 400 loading the comparison result into the ADC sampling channel 100 , the second reference voltage vref2 provides charges to the ADC sampling channel 100 .

[0089] Specifically, in the process of the auxiliary ADC sampling channel 400 loading the comparison result into the ADC sampling channel 100, the capacitors in the high-order capacitor group 11 need to be switched, which will affect the voltage VC across the off-chip capacitor C. Therefore, the second reference voltage vref2 is switched to provide charge to the ADC sampling channel 100. When the voltage VC across the off-chip capacitor C is stable, the first reference voltage vref1 is switched to provide charge to the ADC sampling channel 100. Since the redundant capacitor Cr and the low-order capacitor group 12 are both relatively small, a large voltage drop or severe ringing will not be generated on the off-chip capacitor.

[0090] In some embodiments, the capacitance of the auxiliary capacitor array 80 is smaller than the capacitance of the capacitor array 10 of the analog-to-digital converter.

[0091] That is to say, the capacitance value of the auxiliary capacitor array 80 is relatively small, so the capacitors of the auxiliary capacitor array 80 require less charge when switching, thereby further reducing the error of the second reference voltage vref2, thereby further improving the accuracy of the ADC.

[0092] In some embodiments, the capacitance of the redundant capacitor Cr of the analog-to-digital converter is between the capacitance of the last capacitor in the high-order capacitor group 11 and the capacitance of the first capacitor in the low-order capacitor group 12 .

[0093] It can be understood that the larger the value of the redundant capacitor Cr is, the greater the redundancy is. When the capacitance of the redundant capacitor Cr is the capacitance of the last capacitor in the high-order capacitor group 11, the redundancy is the weight corresponding to the last capacitor in the high-order capacitor group 11; when the capacitance of the redundant capacitor Cr is the capacitance of the first capacitor in the low-order capacitor group 12, the redundancy is the weight corresponding to the first capacitor in the low-order capacitor group 12.

[0094] For example, taking the capacitor array 10 having four capacitors and the redundant capacitor Cr being located between the second capacitor C2 and the third capacitor C3, if the redundant capacitor Cr has the same capacitance as the second capacitor C2, the redundancy is 4; if the redundant capacitor Cr has the same capacitance as the third capacitor C3, the redundancy is 2.

[0095] In summary, the reference voltage providing circuit of the analog-to-digital converter according to an embodiment of the present invention includes a voltage providing unit, a buffer unit and a switching unit, wherein the switching unit is configured to switch the second reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the high-order capacitor group of the analog-to-digital converter is switched, and to switch the first reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the low-order capacitor group of the analog-to-digital converter is switched. Therefore, since each ADC sampling channel is provided with redundant capacitors, when the high-order capacitor group is switched, the reference voltage does not need to be very accurate, and the buffer unit provides charge to the ADC sampling channel, and when the low-order capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel. Since the capacitance of the low-order capacitor group is small, the charge required by the low-order capacitor group is small, and the voltage on the off-chip capacitor will not drop significantly, so the accuracy of the ADC will not be reduced; and when the capacitors in the high-order capacitor group are switched, the charge is provided by the second reference voltage of the buffer unit without using the off-chip capacitor, and no ringing will be generated. When the capacitors in the low-order capacitor group are switched, because the capacitance in the low-order capacitor group is small, the voltage at both ends of the off-chip capacitor drops less, and the amplitude of the ringing is also small, thereby further improving the accuracy of the ADC. In addition, each ADC sampling channel corresponds to a switching unit and a buffer unit, so that each ADC sampling channel uses the charge provided by the corresponding buffer unit when switching the capacitor, so multiple ADC sampling channels will not interfere with each other.

[0096] Corresponding to the above embodiment, an embodiment of the present invention further provides an analog-to-digital converter. Fig.12 As shown, the analog-to-digital converter 1000 includes the reference voltage providing circuit 200 of any of the aforementioned embodiments.

[0097] According to the analog-to-digital converter of the embodiment of the present invention, by adopting the above-mentioned reference voltage providing circuit, since each ADC sampling channel is provided with redundant position capacitors, the reference voltage does not need to be very accurate. When the high-order capacitor group is switched, the buffer unit provides charge to the ADC sampling channel, and when the low-order capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel, which will not cause a significant drop in the voltage on the off-chip capacitor, and therefore will not cause a decrease in the accuracy of the ADC.

[0098] Corresponding to the above embodiment, the embodiment of the present invention further provides a processor. Fig.13 As shown, the processor 2000 includes the aforementioned analog-to-digital converter 1000 .

[0099] According to the processor of the embodiment of the present invention, by adopting the above-mentioned analog-to-digital converter, since each ADC sampling channel is provided with redundant position capacitors, the reference voltage does not need to be very precise. When the high-order capacitor group is switched, the buffer unit provides charge to the ADC sampling channel, and when the low-order capacitor group is switched, the first reference voltage provides charge to the ADC sampling channel, which will not cause a significant drop in the voltage on the off-chip capacitor, and therefore will not cause a decrease in the accuracy of the ADC.

[0100] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0101] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0102] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0103] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0104] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0105] In the present invention, unless otherwise clearly specified or limited in the embodiments, the terms "installed", "connected", "connected" and "fixed" etc. in the embodiments should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integrated connection. It can be understood that it can also be a mechanical connection, an electrical connection, etc.; of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific implementation situation.

[0106] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0107] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A reference voltage providing circuit for an analog-to-digital converter, characterized in that: The analog-to-digital converter includes at least one ADC sampling channel, each of the ADC sampling channels is provided with a capacitor array and a redundant capacitor, the redundant capacitor is suitable for dividing the capacitor array into a high-order capacitor group and a low-order capacitor group, and the reference voltage providing circuit includes: A voltage providing unit, adapted to provide a first reference voltage; a buffer unit, adapted to perform buffering processing on the first reference voltage and output a second reference voltage; The switching unit is configured to switch the second reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the high-order capacitor group of the analog-to-digital converter is switched, and to switch the first reference voltage to provide charge to the ADC sampling channel of the analog-to-digital converter when the low-order capacitor group of the analog-to-digital converter is switched.

2. The reference voltage providing circuit according to claim 1, characterized in that: The switching unit includes: a first switching switch and a second switching switch, the first end of the first switching switch is connected to the output end of the buffer unit, the first end of the second switching switch is connected to the output end of the voltage providing unit, and the second end of the first switching switch is connected to the second end of the second switching switch to form a first node, and the first node is the output end of the reference voltage providing circuit.

3. The reference voltage providing circuit according to claim 2, characterized in that: When the first switch is closed and the second switch is open, the second reference voltage provides charge to the ADC sampling channel; When the first switch is opened and the second switch is closed, the first reference voltage provides charges to the ADC sampling channel.

4. The reference voltage providing circuit according to claim 1, characterized in that: The buffer unit includes: a buffer, a first input end of the buffer is connected to the output end of the voltage providing unit, a second input end of the buffer is connected to the output end of the buffer, and the output end of the buffer serves as the output end of the buffer unit.

5. The reference voltage providing circuit according to any one of claims 1 to 4, characterized in that: The voltage providing unit comprises: Bandgap reference; a first resistor, one end of which is connected to the bandgap reference; An off-chip capacitor, one end of which is grounded, and the other end of which is connected to the other end of the first resistor and serves as an output end of the voltage providing unit.

6. The reference voltage providing circuit according to any one of claims 1 to 4, characterized in that: When there are multiple ADC sampling channels, there are multiple switching units and multiple buffer units, respectively, and each ADC sampling channel corresponds to one switching unit and one buffer unit.

7. The reference voltage providing circuit according to claim 5, characterized in that: The bandgap reference, the first resistor, each of the switching units and each of the buffer units are respectively integrated into a chip of the analog-to-digital converter.

8. The reference voltage providing circuit according to claim 1, characterized in that: The analog-to-digital converter also includes an auxiliary ADC sampling channel, and the auxiliary ADC sampling channel corresponds to an auxiliary capacitor array. After the auxiliary ADC sampling channel obtains a comparison result based on the capacitor switching of the auxiliary capacitor array, the comparison result is loaded into the ADC sampling channel as a high-bit comparison result of the ADC sampling channel.

9. The reference voltage providing circuit according to claim 8, characterized in that: In the process that the auxiliary ADC sampling channel loads the comparison result to the ADC sampling channel, the second reference voltage provides charge to the ADC sampling channel.

10. The reference voltage providing circuit according to claim 8, characterized in that: The capacitance value of the auxiliary capacitor array is smaller than the capacitance value of the capacitor array of the analog-to-digital converter.

11. The reference voltage providing circuit according to claim 1, characterized in that: The capacitance of the redundant capacitor of the analog-to-digital converter is between the capacitance of the last capacitor in the high-order capacitor group and the capacitance of the first capacitor in the low-order capacitor group.

12. An analog-to-digital converter, characterized in that: The invention comprises a reference voltage providing circuit according to any one of claims 1 to 11.

13. A processor, characterized in that: Comprising an analog-to-digital converter according to claim 12.

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