A current-mode neural stimulator for implantable bidirectional brain-computer interface
The current-mode neural stimulator designed through low-voltage process uses NMOS and PMOS current mirrors and stacked MOS tubes to achieve dual-phase current output, and the problem of integration difficulty of neural stimulators under high-voltage process is solved through passive charge balance circuit, achieving high integration and safety to ensure effective charge balance in multi-channel scenarios.
Patent Information
- Application Number
- CN202311251032.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-26
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2043-09-26
AI Technical Summary
Neural stimulators implemented by existing high-voltage processes are not conducive to large-scale integration, especially in multi-channel electrical stimulation scenarios, hundreds or even thousands of electrical stimulation modules are required, resulting in increased integration difficulty.
The current-mode neural stimulator designed using low-voltage process, including the current-mode drive circuit and the passive charge balance circuit, uses the NMOS current mirror, PMOS current mirror and stacked MOS tube to achieve the dual-phase current output, and passes through the level shifter and low-voltage comparator. Charge balance is performed with the exchange switch to ensure charge balance is achieved under different stimulus currents.
Achieving high integration and safety of a neural stimulator with single-electrode biphasic current output, avoiding the limitations of high-voltage processes, can be integrated under low-voltage power supply conditions, and clearing the residual charge of the electrode through a passive charge balance circuit to protect neurons .
Smart Images
Figure CN117258147B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of analog integrated circuits, and specifically provides a current mode neural stimulator applied to an implantable bidirectional brain-computer interface. Background Art
[0002] Electrical stimulation has attracted much attention for its potential to alleviate neurological disorders such as Parkinson's disease, dystonia, epilepsy, etc., and deep brain stimulation (DBS)-based treatments have been widely used in the field of hearing, vision, bladder control and muscle function loss, as well as prostheses for controlling chronic pain.
[0003] Considering safety and implementation difficulty, current-mode neurostimulators are usually used; since the equivalent impedance of the electrode is large, the voltage on the electrode is very high when a large current is output, so a high-voltage process is required; and in order to better perform subsequent charge balance operations, a dual-electrode structure is usually used; however, the dual-electrode current-mode neurostimulator consumes a relatively large area, which is not conducive to large-scale integration. To address this problem, researchers have proposed many single-electrode current-mode neurostimulators, such as Figure 1 , Figure 2 The schematic diagram and switch timing diagram of a single-electrode positive and negative biphasic current output neurostimulator are shown. DAC,a and I DAC,c They are positive and negative biphase current sources respectively. When the switch S a When the switch Sc is closed and the switch Sc is open, a positive current pulse is applied; when the switch S a When the switch S2 is disconnected and the switch Sc is closed, a negative current pulse stimulation is performed; after a stimulation cycle, the cause-based offset compensation circuit (Cause based Offset Compensation) starts working first, the switch S2 is closed and the switch S3 is disconnected, and OTA2 collects the voltage V on the electrode E and reference voltage V CM , and convert it into the corresponding integral current I int / 2 , current I int / 2 The resistor R CMOS and C int Integrate it and convert it into voltage V int , and then converted into the voltage V on the electrode through OTA3 E and reference voltage V CMAfter the cause-based offset compensation circuit completes the current compensation, the result-based inter-pulse charge control circuit (Consequence based Inter-Pulse Charge Control) starts to work, the switch S1 is closed, and the output of the subtraction circuit composed of resistors R1, R2 and OTA1 is V in =V CM +R2 / R1(V CM -V E ); If the voltage V on the electrode E Greater than the reference voltage V CM At this time, PMOS tube M p Conducting, NMOS tube M n Cut off, extract part of the current from the electrode, making V E Reduce until it is approximately equal to the reference voltage V CM It can be seen that after a stimulation cycle, the traditional single-electrode positive and negative biphasic current output neurostimulator can achieve a good charge balance through the offset compensation circuit and the pulse-to-pulse charge control circuit. However, the entire circuit is implemented using a high-voltage process. In the application scenario of multi-channel electrical stimulation, it is usually necessary to integrate hundreds or even thousands of electrical stimulation modules. The neurostimulator implemented using a high-voltage process is not conducive to large-scale integration. Summary of the invention
[0004] The purpose of the present invention is to provide a current mode neurostimulator for use in an implantable bidirectional brain-computer interface in order to address the problem in the prior art that neurostimulators implemented by high voltage processes are not conducive to large-scale integration. The present invention adopts a current mode neurostimulator implemented by a low voltage process, which can achieve a very good charge balance effect under different stimulation currents while outputting a biphasic current normally.
[0005] To achieve the above object, the technical solution adopted by the present invention is:
[0006] A current mode neural stimulator for implantable bidirectional brain-computer interface, comprising: a current mode driving circuit, a passive charge balancing circuit and a current DAC; characterized in that:
[0007] The current mode driving circuit comprises: an NMOS current mirror, a PMOS current mirror and two stacked MOS tubes, the current DAC provides a stimulation current input to the input end of the NMOS current mirror, the NMOS current mirror outputs a first mirror current and a second mirror current of 1:1, wherein the first mirror current is connected to the first port of the first stacked MOS tube, the second port of the first stacked MOS tube is connected to the input end of the PMOS current mirror, the PMOS current mirror outputs a third mirror current to the second port of the second stacked MOS tube, the second mirror current is connected to the first port of the second stacked MOS tube, the third port of the second stacked MOS tube is connected to the electrode model, and the third port of the first stacked MOS tube is suspended;
[0008] The passive charge balancing circuit includes: a level shifter, a low voltage comparator, a switching switch, a subtraction circuit, a voltage-to-current conversion circuit and an output current driving circuit. The voltage Ve_h on the electrode and the reference voltage Vcm_h are used as inputs of the level shifter. The level shifter converts the inputs into low voltages Ve and Vcm and outputs them to the low voltage comparator. The output control signal Voutp of the comparator is sent to the switching switch S1. When Ve is less than Vcm, Voutp is 0, and the low voltages Ve and Vcm are directly input to the subtraction circuit after passing through the switching switch. When Ve is greater than Vcm, Voutp is 1, and the low voltages Ve and Vcm are exchanged through the switching switch and then input to the subtraction circuit. The output of the subtraction circuit is converted into current through the voltage-to-current conversion circuit and input to the output current driving circuit, and the output current driving circuit outputs the compensation current to the electrode.
[0009] Furthermore, in the current mode driving circuit, the second mirror current in the NMOS current mirror is controlled by the switching signal SC. When the switching signal SC is equal to the low bias voltage, the NMOS current mirror outputs the second mirror current; the third mirror current in the PMOS current mirror is controlled by the switching signal SA. When the switching signal SA is equal to the high bias voltage, the PMOS current mirror outputs the third mirror current; the switching signal SC and the switching signal SA control the second mirror current and the third mirror current to be output at different times.
[0010] Furthermore, the first stacked MOS tube and the second stacked MOS tube adopt the same structure, and are composed of PMOS tubes M1, M3, M5, M7, M9 and NMOS tubes M2, M4, M6, M8, M10, the source of M4 is used as the first port, the gate of M4 is connected to the drain of M3 and connected to the low bias voltage, the gate of M3 is connected to the drain of M4 and the source of M10, the source of M3 is connected to the gate of M10 and the drain of M9, the gate of M9 is connected to M The drain of M10 is connected to the source of M8, the source of M9 is connected to the gate of M8, the gate of M7, and the source of M6, the drain of M8 is connected to the drain of M7 and serves as the third port, the source of M7 is connected to the gate of M6 and the drain of M5, the drain of M6 is connected to the gate of M5 and the source of M2, the source of M5 is connected to the gate of M2 and the drain of M1, the drain of M2 is connected to the gate of M1 and connected to a high bias voltage, and the source of M1 serves as the second port.
[0011] Furthermore, in the passive charge balancing circuit, the output current driving circuit includes: an NMOS current mirror, a PMOS current mirror, two stacked MOS tubes and a switch pair, the switch pair is composed of switches S2 and S3, the NMOS current mirror, the PMOS current mirror, the two stacked MOS tubes and the current mode driving circuit in the output current driving circuit adopt the same structure, the switch signal SC is equal to the low bias voltage and the switch signal SA is equal to the high bias voltage; the switch S2 is set at the first port of the first stacked MOS tube, and the switch S3 is set at the first port of the second stacked MOS tube. When Ve is less than Vcm, the switch S2 is closed, and when Ve is greater than Vcm, the switch S3 is closed, and the switches S2 and S3 are not opened at the same time.
[0012] Based on the above technical solution, the beneficial effects of the present invention are:
[0013] 1. The present invention discloses a single-electrode biphasic current output neural stimulator, which is implemented by a low-voltage process without the need for a high-voltage process, so that the stimulator can be integrated with a low-voltage power supply circuit module. Ultimately, the present invention has the advantage of high integration.
[0014] 2. The current mode driving circuit in the present invention adopts stacked MOS tubes, and adaptively adjusts the bias voltage of the gate of the stacked transistor on the output branch, so that the voltage difference on each transistor is within a safe range. Ultimately, the present invention has the advantage of high safety.
[0015] 3. The present invention adopts a passive charge balancing circuit, so that after a stimulation cycle is completed, a charge balancing operation is performed to clear the residual charge on the electrode and prevent excessive residual charge from damaging neurons. Ultimately, the present invention has the advantage of high safety. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1The circuit schematic diagram of an existing single-electrode positive and negative biphasic current output neurostimulator.
[0017] Figure 2 This is a timing diagram of the switch of an existing single-electrode positive and negative biphasic current output neurostimulator.
[0018] Figure 3 This is a circuit schematic diagram of the current mode neural stimulator used in the implantable bidirectional brain-computer interface of the present invention.
[0019] Figure 4 This is a circuit schematic diagram of the current mode driving circuit in the current mode neural stimulator of the present invention.
[0020] Figure 5 It is a circuit schematic diagram of stacked MOS tubes in the current mode driving circuit of the present invention. DETAILED DESCRIPTION
[0021] In order to make the purpose, technical scheme and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.
[0022] This embodiment provides a current mode neural stimulator for implantable bidirectional brain-computer interface, the structure of which is as follows: Figure 3 As shown; specifically, it is a single-electrode two-phase current output neural stimulator implemented by a low-voltage process, which has the advantages of small area and is conducive to large-scale integration; moreover, the current-mode drive circuit does not require high-voltage devices, and uses stacked MOS tubes to adaptively adjust the bias voltage of the stacked transistor gates on the output branch, so that the voltage difference on each transistor is within a safe range, ensuring that the MOS tube does not break down, and has the advantage of high safety.
[0023] The above-mentioned current mode neural stimulator applied to the implantable bidirectional brain-computer interface includes: a current mode driving circuit 1, a passive charge balancing circuit 2 and a 7-bits current DAC 3; the details are as follows:
[0024] (1) Current mode drive circuit
[0025] The current mode driving circuit is as follows Figure 4As shown, it includes an NMOS current mirror, a PMOS current mirror and two stacked MOS tubes, a 7-bit current DAC provides stimulation currents of different ranges to the input end of the NMOS current mirror, and the NMOS current mirror outputs a first mirror current and a second mirror current of 1:1, wherein the first mirror current is connected to the first port of the first stacked MOS tube, the second port of the first stacked MOS tube is connected to the input end of the PMOS current mirror, the PMOS current mirror outputs a third mirror current to the second port of the second stacked MOS tube, the second mirror current is connected to the first port of the second stacked MOS tube, the third port of the second stacked MOS tube is connected to the electrode model, and the third port of the first stacked MOS tube is suspended; the second mirror current in the NMOS current mirror is controlled by a switch signal SC, and when the switch signal SC is equal to a low bias voltage (2.5V), the NMOS current mirror outputs the second mirror current; the third mirror current in the PMOS current mirror is controlled by a switch signal SA, and when the switch signal SA is equal to a high bias voltage (7.5V), the PMOS current mirror outputs the third mirror current; the switch signal SC and the switch signal SA control the second mirror current and the third mirror current to be output at different times;
[0026] The first stacked MOS tube and the second stacked MOS tube have the same structure, such as Figure 5 As shown, it is composed of PMOS tubes M1, M3, M5, M7, M9 and NMOS tubes M2, M4, M6, M8, M10, the source of M4 is used as the first port, the gate of M4 is connected to the drain of M3 and connected to a low bias voltage (2.5V), the gate of M3 is connected to the drain of M4 and the source of M10, the source of M3 is connected to the gate of M10 and the drain of M9, and the gate of M9 is connected to the drain of M10 and the source of M8 , the source of M9 is connected to the gate of M8, the gate of M7, and the source of M6, the drain of M8 is connected to the drain of M7 and serves as the third port, the source of M7 is connected to the gate of M6 and the drain of M5, the drain of M6 is connected to the gate of M5 and the source of M2, the source of M5 is connected to the gate of M2 and the drain of M1, the drain of M2 is connected to the gate of M1 and connected to a high bias voltage (7.5V), and the source of M1 serves as the second port.
[0027] In terms of working principle: the current mode drive circuit is used to copy the output current Iout from the current DAC in the low voltage domain, and the bias voltage of the stacked transistor gate on the output branch is adaptively adjusted by stacking MOS tubes, so that the voltage difference on each transistor is within a safe range, and finally the positive and negative bi-phase current pulses are output; the circuit schematic diagram is shown in Figure 4As shown, the working process is as follows: MN1, MN3 and MN5 are a group of NMOS current mirrors with a mirror ratio of 1:1:1, which are used to copy the output current Iout from the current DAC; NMOS tube MN6 is a switch tube, and when its gate control signal SC is 2.5V, MN6 is turned on, and a negative current pulse is output at this time, that is, the current is drawn from the electrode; NMOS tubes MN2 and MN4 are used to keep the source terminal potential of the current mirror group MN1, MN3 and MN5 consistent, so as to improve the accuracy of current mirror copying; The working principle of the stacked MOS tube is as follows: When the source terminal of M4 is pulled down to a low potential, the gate of M4 is supplied by a 2.5V voltage source, so the M4 tube is turned on. When the M4 tube is turned on, the gate terminal of the M3 tube is pulled down to a low potential, and the M3 tube is also turned on. Therefore, the gate of M10 is short-circuited to the 2.5V voltage source, and M10 is also turned on. Similarly, M8 and M9 are also turned on, and the voltage difference on each transistor is within the safe range; at the same time, in order to reduce the impact of the body effect on the circuit, the source and body of the PMOS tube are connected, and the NMOS tube uses a deep N-well MOS tube, and the source and body of the NMOS tube are connected. PMOS tubes MP2 and MP4 are a group of PMOS current mirrors, which are used to copy the current from the low-voltage domain current DAC. PMOS tube MP3 is a switch tube. When its gate control signal SA is 7.5V, MP3 is turned on, and a positive current pulse is output at this time, that is, current is injected into the electrode. Switch tubes MP3 and MN6 will not be turned on at the same time.
[0028] (2) Passive charge balancing circuit
[0029] The passive charge balancing circuit includes: a level shifter, a low voltage comparator (CMP), a switching switch S1, a subtraction circuit, a voltage to current (VI) conversion circuit and an output current driving circuit. The voltage Ve_h and the reference voltage Vcm_h on the electrode model are used as inputs of the level shifter. The level shifter converts the inputs into low voltages Ve and Vcm and outputs them to the low voltage comparator. The output Voutp of the comparator (CMP) is sent to the switching switch S1. The subtraction circuit includes a resistor R1, a resistor R2 and an operational amplifier OP. When Ve is less than Vcm, Voutp is 0. The low voltages Ve and Vcm are directly input into the subtraction circuit after passing through the switching switch. The output of the subtraction circuit is R2 / R1×(Vcm-Ve). When Ve is greater than Vcm, Voutp is 1. The low voltages Ve and Vcm are exchanged through the switching switch and then input into the subtraction circuit. The subtraction circuit The output is R2 / R1×(Ve-Vcm); the output of the subtraction circuit is converted into current through a voltage-to-current conversion circuit and input into an output current driving circuit; the output current driving circuit includes an NMOS current mirror, a PMOS current mirror, two stacked MOS tubes and a switch pair, the switch pair is composed of switches S2 and S3, the NMOS current mirror, the PMOS current mirror, the two stacked MOS tubes and the current mode driving circuit in the output current driving circuit adopt the same structure, the switch signal SC is equal to the low bias voltage (2.5V) and the switch signal SA is equal to the high bias voltage (7.5V); the switch S2 is set at the first port of the first stacked MOS tube, the switch S3 is set at the first port of the second stacked MOS tube, when Ve is less than Vcm, the switch S2 is closed, when Ve is greater than Vcm, the switch S3 is closed, and the switches S2 and S3 are not opened at the same time;
[0030] From the working principle: the role of the passive charge balancing circuit is to output a certain amount of compensation current Ie according to the voltage difference between the voltage Ve_h on the electrode and the reference voltage Vcm_h after a complete stimulation cycle. Its working process is as follows: after a stimulation cycle, the level shifter first converts the voltage Ve_h on the electrode and the reference voltage Vcm_h (both are high voltage) into low voltage Ve and Vcm, and the low voltage comparator (CMP) compares the size of Ve and Vcm; resistors R1, R2 and operational amplifier OP form a subtraction circuit, S1 is a set of switches, and the outputs Voutp and Voutn of the comparator (CMP) control whether Ve and Vcm are exchanged;
[0031] If Ve is less than Vcm, no exchange is required, and the output of the subtraction circuit is R2 / R1×(Vcm-Ve). The voltage-to-current (VI) circuit converts the residual voltage into a current and transmits it to the NMOS current mirror. Because Ve is less than Vcm, it means that the voltage Ve_h on the electrode is less than the reference voltage Vcm_h. A certain current needs to be injected into the electrode to increase Ve_h so that Ve_h is equal to Vcm_h. Therefore, the switch S2 is closed to allow the current to pass through the first stacked MOS tube, the PMOS current mirror and the second stacked MOS tube to charge the output electrode. The compensation current is Ie, and finally there is no voltage difference between Ve_h and Vcm_h, achieving charge balance.
[0032] If Ve is greater than Vcm, an exchange occurs, and the output of the subtraction circuit is R2 / R1×(Ve-Vcm). The voltage-to-current (VI) circuit converts the residual voltage into a current and transmits it to the NMOS current mirror. Because Ve is greater than Vcm, it means that the voltage Ve_h on the electrode is greater than the reference voltage Vcm_h. It is necessary to draw a certain amount of current from the electrode to reduce Ve_h so that Ve_h is equal to Vcm_h. Therefore, the switch S3 is closed to allow the current to discharge the output electrode through the second stacked MOS tube and the NMOS current mirror. The compensation current is Ie, and finally there is no voltage difference between Ve_h and Vcm_h, achieving charge balance.
[0033] (3) 7-bit current DAC
[0034] The 7-bit current DAC outputs stimulation currents of different ranges under the control of a 7-bit control switch, wherein the reference current is 20 nA, and the current range output by the current DAC is 20 nA-2.54 uA.
[0035] (4) Electrode model
[0036] The electrode model is an abstract model for simulating neuron load. The size of capacitor C1 is about tens of nF, the size of resistor R5 is about 500k ohms, and the size of resistor R4 is about 10k.
[0037] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.
Claims
1. A current mode neural stimulator for an implantable bidirectional brain-computer interface, comprising: Current mode driving circuit, passive charge balancing circuit and current DAC; characterized in that, The current mode driving circuit comprises: an NMOS current mirror, a PMOS current mirror and two stacked MOS tubes, the current DAC provides a stimulation current input to the input end of the NMOS current mirror, the NMOS current mirror outputs a first mirror current and a second mirror current of 1:1, wherein the first mirror current is connected to the first port of the first stacked MOS tube, the second port of the first stacked MOS tube is connected to the input end of the PMOS current mirror, the PMOS current mirror outputs a third mirror current to the second port of the second stacked MOS tube, the second mirror current is connected to the first port of the second stacked MOS tube, the third port of the second stacked MOS tube is connected to the electrode model, and the third port of the first stacked MOS tube is suspended; The passive charge balancing circuit includes: a level shifter, a low voltage comparator, a switching switch, a subtraction circuit, a voltage-to-current conversion circuit and an output current driving circuit. The voltage Ve_h on the electrode and the reference voltage Vcm_h are used as inputs of the level shifter. The level shifter converts the inputs into low voltages Ve and Vcm and outputs them to the low voltage comparator. The output control signal Voutp of the comparator is sent to the switching switch S1. When Ve is less than Vcm, Voutp is 0, and the low voltages Ve and Vcm are directly input to the subtraction circuit after passing through the switching switch. When Ve is greater than Vcm, Voutp is 1, and the low voltages Ve and Vcm are exchanged through the switching switch and then input to the subtraction circuit. The output of the subtraction circuit is converted into current through the voltage-to-current conversion circuit and input to the output current driving circuit, and the output current driving circuit outputs the compensation current to the electrode. In the current mode driving circuit, the second mirror current in the NMOS current mirror is controlled by the switch signal SC. When the switch signal SC is equal to the low bias voltage, the NMOS current mirror outputs the second mirror current; the third mirror current in the PMOS current mirror is controlled by the switch signal SA. When the switch signal SA is equal to the high bias voltage, the PMOS current mirror outputs the third mirror current; the switch signal SC and the switch signal SA control the second mirror current and the third mirror current to be output at different times; The first stacked MOS tube and the second stacked MOS tube adopt the same structure, and are composed of PMOS tubes M1, M3, M5, M7, M9 and NMOS tubes M2, M4, M6, M8, M10. The source of M4 is used as the first port, the gate of M4 is connected to the drain of M3 and connected to a low bias voltage, the gate of M3 is connected to the drain of M4 and the source of M10, the source of M3 is connected to the gate of M10 and the drain of M9, and the gate of M9 is connected to M10. The drain of M0 is connected to the source of M8, the source of M9 is connected to the gate of M8, the gate of M7, and the source of M6, the drain of M8 is connected to the drain of M7 and serves as the third port, the source of M7 is connected to the gate of M6 and the drain of M5, the drain of M6 is connected to the gate of M5 and the source of M2, the source of M5 is connected to the gate of M2 and the drain of M1, the drain of M2 is connected to the gate of M1 and connected to a high bias voltage, and the source of M1 serves as the second port.
2. The current mode neural stimulator for implantable bidirectional brain-computer interface according to claim 1, characterized in that: In the passive charge balancing circuit, the output current driving circuit includes: an NMOS current mirror, a PMOS current mirror, two stacked MOS tubes and a switch pair, the switch pair is composed of switches S2 and S3, the NMOS current mirror, the PMOS current mirror, the two stacked MOS tubes and the current mode driving circuit in the output current driving circuit adopt the same structure, the switch signal SC is equal to the low bias voltage and the switch signal SA is equal to the high bias voltage; the switch S2 is set at the first port of the first stacked MOS tube, the switch S3 is set at the first port of the second stacked MOS tube, when Ve is less than Vcm, the switch S2 is closed, when Ve is greater than Vcm, the switch S3 is closed, and the switches S2 and S3 are not opened at the same time.