Long short-term memory neural network control circuit and method

Abstract

The application relates to a long-short memory neural network control circuit and method, the circuit comprising: an input gate circuit, a forget gate circuit, a unit state configuration control circuit and a reconfigurable unit, the input gate circuit processes an input signal and outputs a current signal to the reconfigurable unit, and the reconfigurable unit converts the current signal into a voltage signal; after a first switch between the forget gate circuit and the reconfigurable unit is closed, the current signal is converted into the voltage signal and then loaded to a transistor, and the current flowing through the transistor is adjusted to discharge the capacitor of the reconfigurable unit; the unit state configuration control circuit determines reconfiguration parameters of the reconfigurable unit module according to task requirements; and the reconfigurable unit obtains current time output parameters and unit state parameters after being reconfigured based on the task requirements, the voltage signal and the reconfiguration parameters. Thus, the problems of long delay and high power consumption of a current general hardware platform running a long-short artificial neural network are solved, and the processing speed of information is effectively accelerated and the system power consumption is reduced.

Description

Technical Field

[0001] This application relates to the field of neural network technology, and in particular to a control circuit and method for a long short-range memory neural network. Background Technology

[0002] With the emergence of various network architectures and algorithms, artificial neural networks have demonstrated remarkable achievements in current information processing. Because traditional information processing hardware platforms that separate storage and computation are not well-integrated with artificial neural networks capable of parallel data processing, dedicated acceleration chips for artificial neural networks, such as TrueNoth, Loihi, and TianjiC, as well as operating platforms such as TPUs (Tensor Processing Units) and GPUs (Graphics Processing Units), have emerged, further promoting the application and development of artificial neural networks.

[0003] Long Short Term Memory (LSTM) artificial neural networks are a type of network model specifically designed for processing temporal information. Because the current input data needs to interact with the processing results from the previous time step, the latency and power consumption of LSTM artificial neural networks running on current general-purpose platforms increase dramatically due to the repeated caching, reading, and stacking of data.

[0004] Therefore, there is a great need for dedicated hardware circuits and operating platforms designed for neural networks that process complex information. Summary of the Invention

[0005] This application provides a control circuit and method for long and short-range memory neural networks to solve the problems of large latency and high power consumption when running long and short-range artificial neural networks on current general-purpose hardware platforms. It proposes a hardware circuit architecture for long and short-range memory neural networks with adjustable and reconfigurable unit states, which effectively accelerates information processing speed and reduces system power consumption.

[0006] A first aspect of this application provides a long-short-range memory neural network control circuit, comprising: an input gate circuit, a forget gate circuit, a cell state configuration control circuit, and a reconfigurable cell, wherein...

[0007] The input gate circuit is used to process at least one encoded input signal using an input gate memristor array and output a first current signal to the reconfigurable unit, so that the first current signal can be converted into a first voltage signal through the reconfigurable unit.

[0008] The forget gate circuit is used to process the at least one input signal using a forget gate memristor array after closing the first switch between the forget gate circuit and the reconfigurable unit, and output a second current signal. The second current signal is then converted into a second voltage signal using a current-to-voltage conversion circuit and applied to the transistor so as to discharge the capacitor of the reconfigurable unit by adjusting the current flowing through the transistor.

[0009] The unit state configuration control circuit is used to determine the reconfiguration parameters of the reconfigurable unit module according to the current task requirements; and

[0010] The reconfigurable unit is used to reconstruct the current output parameters and the current unit state parameters based on the current task requirements, according to the first voltage signal and the reconfiguration parameters.

[0011] Optionally, in some embodiments, the forget gate circuit includes: the first switch, the forget gate memristor array, the first operational amplifier, and the transistor, wherein,

[0012] The forget gate memristor array is formed by connecting multiple forget gate memristors in parallel. The input terminal of the forget gate memristor array is used to input the at least one input signal, and the output terminal of the forget gate memristor array is connected to the non-inverting input terminal of the first operational amplifier.

[0013] The inverting input terminal of the first operational amplifier is connected to a first power supply, wherein the first power supply is used to provide a first reference voltage, and the output terminal of the first operational amplifier is connected to the base of the transistor.

[0014] The emitter of the transistor is grounded, and the collector of the transistor is connected to the reconfigurable unit through the first switch.

[0015] Optionally, in some embodiments, the cell state configuration control circuit includes: configuring a memristor array and a second operational amplifier, wherein,

[0016] The configuration memristor array is formed by connecting multiple configuration memristors in parallel. The input terminal of the configuration memristor array is used to input the at least one input signal, and the output terminal of the configuration memristor array is connected to the non-inverting input terminal of the second operational amplifier.

[0017] The inverting input of the second operational amplifier is connected to a second power supply, which provides a second reference voltage. The output of the second operational amplifier is connected to the reconfigurable unit.

[0018] Optionally, in some embodiments, the reconfigurable unit includes:

[0019] A capacitor array formed by arranging multiple capacitors in parallel;

[0020] A switching circuit obtained by connecting multiple switches in parallel;

[0021] The third operational amplifier has its non-inverting input terminal connected to one end of the capacitor array and the output terminal of the input gate circuit, its inverting input terminal connected to the third power supply, and its output terminal connected to one end of the switching circuit as the output terminal of the reconfigurable unit.

[0022] The third power source is used to provide a third reference voltage.

[0023] Optionally, in some embodiments, the capacitors of the capacitor array are connected one-to-one with the switches of the switching circuit.

[0024] Optionally, in some embodiments, the input gate memristor array consists of a plurality of input gate memristors connected in parallel, the input gate memristor array being used to input at least one encoded input signal.

[0025] Optionally, in some embodiments, the reconfigurable unit is further configured to store the current time output parameters and the current time state parameters.

[0026] Optionally, in some embodiments, the input signal includes at least one of the current input parameters, the previous output parameters, and the previous reconfigurable cell state parameters.

[0027] A second aspect of this application provides a long-short-range memory neural network control method, employing a long-short-range memory neural network control circuit as described in any of the preceding embodiments, wherein the method includes the following steps:

[0028] The input gate circuit processes at least one encoded input signal using an input gate memristor array and outputs a first current signal to the reconfigurable unit, so that the reconfigurable unit can convert the first current signal into a first voltage signal.

[0029] After the first switch between the forget gate circuit and the reconfigurable unit is closed, the at least one input signal is processed by the forget gate memristor array and a second current signal is output. The second current signal is then converted into a second voltage signal by a current-to-voltage conversion circuit and applied to the transistor so as to discharge the capacitor of the reconfigurable unit by adjusting the current flowing through the transistor.

[0030] The reconfigurable unit module's reconfiguration parameters are determined by the unit state configuration control circuit based on the current task requirements.

[0031] The reconfigurable unit reconstructs the current output parameters and the current unit state parameters based on the current task requirements, according to the first voltage signal and the reconfiguration parameters.

[0032] Optionally, in some embodiments, after obtaining the current time output parameters and the current time unit state parameters by reconstructing based on the first voltage signal, the third voltage signal, and the reconstruction parameters according to the current task requirements, the method further includes: storing the current time output parameters and the current time state parameters.

[0033] Therefore, this application utilizes the memristor array of the input gate circuit to process the encoded input signal and output a first current signal to the reconfigurable unit. The reconfigurable unit converts the first current signal into a first voltage signal. After the first switch between the forget gate circuit and the reconfigurable unit is closed, the input signal is processed by the memristor array of the forget gate circuit to output a second current signal. The second current signal is then converted into a second voltage signal using a current-to-voltage conversion circuit and applied to a transistor. The capacitor of the reconfigurable unit is discharged by adjusting the current flowing through the transistor. The reconfigurable unit module's reconstruction parameters are determined by the unit state configuration control circuit according to the current task requirements. The reconfigurable unit reconstructs the current output parameters and unit state parameters based on the first voltage signal and reconstruction parameters according to the current task requirements. This solves the problems of high latency and high power consumption when running long- and short-range artificial neural networks on current general-purpose hardware platforms. It proposes a hardware circuit architecture for long- and short-range memory neural networks with adjustable and reconfigurable unit states, effectively accelerating information processing speed and reducing system power consumption.

[0034] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0035] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0036] Figure 1 This is a schematic diagram of a long-short-range memory neural network control circuit provided according to an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of the input-output of a long short-range memory neural network according to a specific embodiment of this application;

[0038] Figure 3 This is a schematic diagram illustrating the control circuit principle of a long-short-range memory neural network according to a specific embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the configuration of the control circuit of a long short-range memory neural network according to a specific embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the control circuit structure of a long-short-range memory neural network according to a specific embodiment of this application;

[0041] Figure 6 This is a flowchart of a long short-range memory neural network control method provided according to an embodiment of this application. Detailed Implementation

[0042] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0043] The following describes a long-short-range memory neural network control circuit and method according to embodiments of this application with reference to the accompanying drawings. Addressing the issues of high latency and high power consumption when running long-short-range artificial neural networks on current general-purpose hardware platforms, as mentioned in the background art, this application provides a long-short-range memory neural network control circuit. In this circuit, an input gate circuit processes at least one encoded input signal using an input gate memristor array and outputs a first current signal to a reconfigurable unit, which then converts the first current signal into a first voltage signal. A forget gate circuit, after closing the first switch between the forget gate circuit and the reconfigurable unit, processes at least one input signal using a forget gate memristor array and outputs a second current signal. A current-to-voltage conversion circuit converts the second current signal into a second voltage signal, which is then applied to a transistor to regulate the current flowing through the transistor and discharge the capacitor of the reconfigurable unit. A unit state configuration control circuit determines the reconfiguration parameters of the reconfigurable unit module based on current task requirements. The reconfigurable unit, based on current task requirements, reconfigures the first voltage signal and the reconfiguration parameters to obtain the current-time output parameters and the current-time unit state parameters. This solves the problems of high latency and high power consumption when running long and short-range artificial neural networks on current general-purpose hardware platforms. It proposes a hardware circuit architecture for long and short-range memory neural networks with adjustable and reconfigurable unit states, which effectively accelerates information processing speed and reduces system power consumption.

[0044] Before introducing the long and short range memory neural network control circuit of the embodiments of this application, let's first introduce the relevant content of long and short range memory neural networks.

[0045] Specifically, Long Short-Range Memory (LSM) artificial neural networks are network models specifically designed for processing temporal information. During computation, the current input needs to interact with the output from the previous time step and the state of the current computation unit. Therefore, the hardware platform needs to calculate and store the output from the previous time step and the state of the computation unit. At the current computation time, the stored information from the previous time step is read from the storage unit, interactively calculated, and then written back to the storage unit, awaiting the next computation time step for the next round of interactive processing. Because the interactive process is more complex than that of non-temporal information processing network models such as convolutional artificial neural networks, commonly used hardware computing platforms experience very high latency and power consumption costs when operating LSM artificial neural networks.

[0046] Therefore, to address the aforementioned issues, this application proposes a long-short-range memory (LSM) artificial neural network control circuit capable of storing the computing unit state internally and providing an adjustable and reconfigurable computing unit. This circuit accelerates information processing and reduces system power consumption by minimizing the amount and frequency of data transfer between the storage and processing units during iteration. The LSM control circuit provided in this application will be described in detail below.

[0047] Specifically, Figure 1 This is a schematic diagram of the long-short-range memory neural network control circuit provided in an embodiment of this application.

[0048] like Figure 1 As shown, the long-short-range memory neural network control circuit 10 includes: an input gate circuit 100, a forget gate circuit 200, a unit state configuration control circuit 300, and a reconfigurable unit 400.

[0049] The input gate circuit 100 is used to process at least one encoded input signal using an input gate memristor array and output a first current signal to the reconfigurable unit 400, so that the first current signal can be converted into a first voltage signal by the reconfigurable unit 400.

[0050] The forget gate circuit 200 is used to process at least one input signal using a forget gate memristor array after the first switch between the closed forget gate circuit 200 and the reconfigurable unit 400 is closed, and output a second current signal. The second current signal is then converted into a second voltage signal using a current-to-voltage conversion circuit and applied to a transistor so as to discharge the capacitor of the reconfigurable unit 400 by adjusting the current flowing through the transistor.

[0051] The unit state configuration control circuit 300 is used to determine the reconfiguration parameters of the reconfigurable unit module according to the current task requirements;

[0052] The reconfigurable unit 400 is used to reconstruct the current output parameters and the current unit state parameters based on the current task requirements, according to the first voltage signal and the reconfiguration parameters.

[0053] Optionally, in some embodiments, the input signal includes at least one of the current input parameters, the previous output parameters, and the previous reconfigurable cell state parameters.

[0054] It is understood that the inputs and outputs of the long-short-range memory neural network model included in the long-short-range memory neural network control circuit of this application embodiment are as follows: Figure 2 As shown, the input of a network cell includes the current input x. t The output h from the previous time step t-1 and the state parameters C of the cell at the previous time step t-1 In terms of hardware implementation, it involves taking the output h from the previous moment. t-1 and the state parameters C of the cell at the previous time step t-1 The result is first temporarily stored in the storage module. When calculating at the current time, the temporary result is read from the storage module to obtain the output h at the current time. t and unit state parameter C t They are then written to the storage module, awaiting use in the next computation.

[0055] Therefore, the input gate circuit 100 of this application embodiment utilizes the input signal received by the input gate memristor, which includes at least one of the current input parameters, the previous output parameters, and the previous reconfigurable cell state parameters, and the input signal must be encoded before flowing into the input gate circuit 100.

[0056] The following will describe in detail the structure and implementation principle of the long-short-range memory neural network control circuit of this application, with reference to the accompanying drawings and examples.

[0057] Specifically, Figure 3 This is a schematic diagram of a long-short-range memory neural network control circuit structure according to a specific embodiment of this application, combined with... Figure 1 and Figure 3 As shown, the long-short-range memory neural network control circuit 10 of this application embodiment includes an input gate circuit 100, a forget gate circuit 200, a unit state configuration control circuit 300, and a reconfigurable unit 400.

[0058] Alternatively, in some embodiments, such as Figure 3 As shown, the input gate memristor array 101 consists of multiple input gate memristors connected in parallel. The input gate memristor array 101 is used to input at least one encoded input signal.

[0059] It is understandable that, such as Figure 3As shown, the input gate circuit 100 in this embodiment of the application is used to receive an input signal, process the input signal, and output the processed input signal to the reconfigurable unit 400. The input gate circuit 100 in this embodiment of the application consists of an input gate memristor array 101, the size of which is related to the task to be performed.

[0060] Specifically, in this embodiment, the input gate circuit 100 multiplies the input signal voltage signal and the conductance value of the input gate memristor array 101 to obtain the output current of the unit device. The current is collected through wires to realize the addition operation. The output of the input gate circuit 100 is the current after the multiplication and addition operation.

[0061] Alternatively, in some embodiments, such as Figure 3 As shown, the forget gate circuit 200 includes: a first switch FGT, a forget gate memristor array 201, a first operational amplifier OP1, and a transistor M. f .

[0062] The forget-gate memristor array 201 is formed by multiple forget-gate memristors connected in parallel. The input terminal of the forget-gate memristor array 201 is used to input at least one input signal, and the output terminal of the forget-gate memristor array 201 is connected to the non-inverting input terminal of the first operational amplifier OP1. The inverting input terminal of the first operational amplifier OP1 is connected to a first power supply, which provides a first reference voltage V. bf The output of the first operational amplifier OP1 is connected to transistor M. f The base of transistor M is connected; f The emitter is grounded, transistor M f The collector is connected to the reconfigurable unit 400 via the first switch FGT.

[0063] Optionally, the forget gate circuit 200 in this embodiment includes, in addition to, a forget gate memristor array 201, a first operational amplifier OP1 (op-amp circuit), and a transistor M. f (Control transistors) can also be used to set up switching circuits, i.e. Figure 3 The first switch FGT in the middle.

[0064] It should be noted that the first operational amplifier OP1 in this embodiment is a current-to-voltage conversion circuit used to convert current signals into voltage signals.

[0065] Specifically, the input signal is applied to the forget gate memristor array 201, and the output current is converted into voltage by a current-to-voltage conversion circuit and then applied to transistor M. f On the gate, thus controlling the flow through transistor M f The magnitude of the current flowing through transistor M. fThe current discharges the capacitor in the reconfigurable cell 400 to realize the forgetting function of the cell state.

[0066] It should be noted that, as Figure 3 As shown, the output current of the input gate circuit 100 is integrated across the capacitor of the reconfigurable unit 400 and converted into a voltage signal. During this process, the forget gate circuit 200 converts the input signal and the weights stored in the forget gate memristor array 201 into a voltage after performing a multiplication-addition operation. This voltage is then applied to the transistor M. f On the gate, by adjusting the flow through transistor M f The current discharges the capacitor of the reconfigurable unit 400 to realize the forgetting function. At this time, the first switch FGT of the forgetting gate circuit 200 is closed.

[0067] Alternatively, in some embodiments, such as Figure 3 As shown, the unit state configuration control circuit 300 includes: a configuration memristor array 301 and a second operational amplifier OP2.

[0068] The configuration memristor array 301 is formed by multiple configuration memristors connected in parallel. The input terminal of the configuration memristor array 301 is used to input at least one input signal, and the output terminal of the configuration memristor array 301 is connected to the non-inverting input terminal of the second operational amplifier OP2. The inverting input terminal of the second operational amplifier OP2 is connected to a second power supply, which provides a second reference voltage V. bc The output of the second operational amplifier OP2 is connected to the reconfigurable unit 400.

[0069] In some embodiments, the unit state configuration control circuit 300 of this application includes, in addition to configuring the memristor array 301 and the second operational amplifier OP2, a switching circuit may also be provided.

[0070] Specifically, the main function of the unit state configuration control circuit 300 in this embodiment is to select the number of capacitors to be connected according to task requirements. In actual execution, unit state configuration weights can also be added, and by training the weights, the reconfigurability of the unit circuit can be achieved.

[0071] Therefore, the long and short range memory neural network control circuit of this application can be reconfigured and configured through the unit state configuration control circuit to meet the application requirements of different tasks.

[0072] Alternatively, in some embodiments, such as Figure 3 As shown, the reconfigurable unit 400 includes: a capacitor array C formed by multiple capacitors arranged in parallel. int The switching circuit SEL is obtained by connecting multiple switches in parallel; the third operational amplifier OP3, the non-inverting input of the third operational amplifier OP3 is connected to the capacitor array C.int One end of the input gate circuit 100 is connected to the output of the input gate circuit 100. The inverting input of the third operational amplifier OP3 is connected to the third power supply. The output of the third operational amplifier OP3 is connected to one end of the switching circuit SEL and serves as the output of the reconfigurable unit 400. The third power supply is used to provide the third reference voltage V. bi .

[0073] Optionally, in some embodiments, the capacitor array C int The capacitors are connected one-to-one with the switches in the switching circuit SEL.

[0074] It is understood that the reconfigurable unit 400 is configured according to the current task in this embodiment of the application, mainly through... Figure 3 The switching circuit SEL in the middle is closed or opened to achieve this.

[0075] Specifically, such as Figure 3 As shown, in the reconfigurable unit 400 of this embodiment, the network input is encoded into a voltage signal and applied to the input gate memristor array 101. The output current of the array is in the capacitor array C. int Integrate the components and convert them into a voltage output.

[0076] Optionally, in some embodiments, the reconfigurable unit 400 is also used to store the current output parameters and the current state parameters.

[0077] It is understood that the reconfigurable unit 400 in this application embodiment can be a state storage module of a long short-range memory neural network, where input signals at different times are superimposed within the unit, and the information stored in the unit is selectively discarded through the forget gate circuit 200.

[0078] Specifically, such as Figure 3 As shown, the input gate circuit 100 and the forget gate circuit 200 of this application embodiment configure the current state of the reconfigurable unit 400 and the output of the current system. After the configuration is completed, the first switch FGT and the switch RST are both turned off, and the reconfigurable unit 400 stores the current state and output parameters.

[0079] It should be noted that after all the above calculations are completed, switch RST closes, switch circuit SEL closes, and the capacitor of reconfigurable unit 400 is discharged, returning to zero.

[0080] Based on the above embodiments, the configuration of the long-short-range memory neural network control circuit 10 in this application embodiment can be as follows: Figure 4 As shown, the long-short-range memory neural network control circuit 10 mainly includes input weights, forgetting weights, unit configuration weights, and unit modules, such as... Figure 4 As shown, the input weight W iForgetting weight W f and unit configuration weight W c They are all composed of memristor arrays. The main components of a unit module are a capacitor array and a switching circuit. The switching circuit selects and configures the capacitor array to achieve the purpose of reconfiguring the network unit.

[0081] Therefore, this application can adjust the memristor parameters through neural network training, and realize the function of configuring the weight parameters of each module for different tasks.

[0082] Furthermore, Figure 5 This is a schematic diagram of the long short-range memory neural network control circuit structure according to a specific embodiment of this application. Based on the description of the above embodiment, it can be understood that the architecture of the long short-range memory neural network control circuit 10 of this application mainly includes four parts. Among them, the input gate circuit 100 is used to receive input parameters, adjust the input weights through network training, and then load the input of the module onto the network unit; the forget gate circuit 200, after network training, controls the amount of information that the network unit needs to discard through forget weights; and the unit state configuration control circuit 300, after training, has the function of reconstructing and configuring the hardware parameters of the network unit.

[0083] In addition, such as Figure 5 As shown, in order to pass the calculation result of the current moment to the next moment, the long short-range memory neural network control circuit 10 of this application embodiment can also be set with an output gate circuit 500 to perform the next round of interactive processing.

[0084] Therefore, the long-short-range memory neural network control circuit of this application embodiment can reduce the frequency of data transfer by eliminating the back-and-forth transfer of unit state data between the storage unit and the computing unit, thereby reducing the system's operating latency and power consumption, thus effectively solving the shortcomings of large latency and high power consumption when running long-short-range artificial neural networks on current general-purpose hardware platforms.

[0085] According to the long-short-range memory neural network control circuit proposed in this application, the encoded input signal is processed by the memristor array of the input gate circuit, and a first current signal is output to the reconfigurable unit. The reconfigurable unit converts the first current signal into a first voltage signal. After the first switch between the forget gate circuit and the reconfigurable unit is closed, the input signal is processed by the memristor array of the forget gate circuit and a second current signal is output. The second current signal is converted into a second voltage signal by the current-to-voltage conversion circuit and then loaded onto the transistor. The capacitor of the reconfigurable unit is discharged by adjusting the current flowing through the transistor. The reconfigurable unit module's reconstruction parameters are determined by the unit state configuration control circuit according to the current task requirements. The reconfigurable unit reconstructs the current output parameters and the current unit state parameters based on the first voltage signal and reconstruction parameters according to the current task requirements. This solves the problems of high latency and high power consumption when running long-short-range artificial neural networks on current general-purpose hardware platforms. It proposes a hardware circuit architecture for long-short-range memory neural networks with adjustable and reconfigurable unit states, effectively accelerating information processing speed and reducing system power consumption.

[0086] Next, referring to the accompanying drawings, a long-short-range memory neural network control method according to an embodiment of this application is described, which employs the aforementioned long-short-range memory neural network control circuit 10.

[0087] Figure 6 This is a flowchart of the long short-range memory neural network control method according to an embodiment of this application.

[0088] like Figure 6 As shown, the long short-range memory neural network control method includes the following steps:

[0089] In step S601, at least one encoded input signal is processed by the input gate memristor array through the input gate circuit and a first current signal is output to the reconfigurable unit so that the first current signal is converted into a first voltage signal through the reconfigurable unit.

[0090] In step S602, after the first switch between the closed forget gate circuit and the reconfigurable unit is closed, at least one input signal is processed by the forget gate memristor array and a second current signal is output. The second current signal is converted into a second voltage signal by the current-to-voltage conversion circuit and then applied to the transistor so as to discharge the capacitor of the reconfigurable unit by adjusting the current flowing through the transistor.

[0091] In step S603, the reconfiguration parameters of the reconfigurable unit module are determined by the unit state configuration control circuit according to the current task requirements.

[0092] In step S604, the reconfigurable unit reconstructs the current output parameters and the current unit state parameters based on the current task requirements, according to the first voltage signal and the reconfiguration parameters.

[0093] Optionally, in some embodiments, after obtaining the current output parameters and current unit state parameters by reconstructing based on the first voltage signal, the third voltage signal, and the reconstruction parameters according to the current task requirements, the method further includes: storing the current output parameters and current state parameters.

[0094] It should be noted that the foregoing explanation of the long and short range memory neural network control circuit embodiment also applies to the long and short range memory neural network control method of this embodiment, and will not be repeated here.

[0095] According to the long short-range memory (LSM) neural network control method proposed in this application, an input signal is received through an input gate circuit. The input weights are adjusted through network training, and the input signal is loaded onto the network units. Since the forget gate circuit, after network training, can control the amount of information to be discarded by the network units according to the forgetting weights, the forgetting function of the network can be achieved by discharging the capacitor array of the reconfigurable unit. The reconfigurable unit determines the reconfiguration parameters of the reconfigurable unit module according to the current task requirements through a unit state configuration control circuit. Based on the current task requirements, the reconfigurable unit reconstructs the input signal to obtain the current output parameters and the current unit state parameters. Therefore, the LSM control method proposed in this application realizes the storage of unit states and the selective discarding of information, reducing the back-and-forth movement of various parameters between the storage module and the computing module during network operation, thereby reducing the latency and power consumption of the LSM operation.

[0096] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0097] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0098] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0099] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or more of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (FPGAs), field-programmable gate arrays (FPGAs), etc.

[0100] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0101] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A long-short-range memory neural network control circuit, characterized in that, include: Input gate circuits, forget gate circuits, cell state configuration control circuits, and reconfigurable cells, among which, The input gate circuit is used to process at least one encoded input signal using an input gate memristor array and output a first current signal to the reconfigurable unit, so that the first current signal can be converted into a first voltage signal through the reconfigurable unit. The forget gate circuit is used to process the at least one input signal using a forget gate memristor array after closing the first switch between the forget gate circuit and the reconfigurable unit, and output a second current signal. The second current signal is then converted into a second voltage signal using a current-to-voltage conversion circuit and applied to the transistor so as to discharge the capacitor of the reconfigurable unit by adjusting the current flowing through the transistor. The unit state configuration control circuit is used to determine the reconfiguration parameters of the reconfigurable unit module according to the current task requirements; and The reconfigurable unit is used to reconstruct the current output parameters and the current unit state parameters based on the current task requirements, according to the first voltage signal and the reconfiguration parameters.

2. The long-short-range memory neural network control circuit according to claim 1, characterized in that, The forget gate circuit includes: the first switch, the forget gate memristor array, the first operational amplifier, and the transistor, wherein, The forget gate memristor array is formed by connecting multiple forget gate memristors in parallel. The input terminal of the forget gate memristor array is used to input the at least one input signal, and the output terminal of the forget gate memristor array is connected to the non-inverting input terminal of the first operational amplifier. The inverting input terminal of the first operational amplifier is connected to a first power supply, wherein the first power supply is used to provide a first reference voltage, and the output terminal of the first operational amplifier is connected to the base of the transistor. The emitter of the transistor is grounded, and the collector of the transistor is connected to the reconfigurable unit through the first switch.

3. The long-short-range memory neural network control circuit according to claim 1, characterized in that, The unit state configuration control circuit includes: configuring a memristor array and a second operational amplifier, wherein... The configuration memristor array is formed by connecting multiple configuration memristors in parallel. The input terminal of the configuration memristor array is used to input the at least one input signal, and the output terminal of the configuration memristor array is connected to the non-inverting input terminal of the second operational amplifier. The inverting input of the second operational amplifier is connected to a second power supply, which provides a second reference voltage. The output of the second operational amplifier is connected to the reconfigurable unit.

4. The long-short-range memory neural network control circuit according to claim 3, characterized in that, The reconfigurable unit includes: A capacitor array formed by arranging multiple capacitors in parallel; A switching circuit obtained by connecting multiple switches in parallel; The third operational amplifier has its non-inverting input terminal connected to one end of the capacitor array and the output terminal of the input gate circuit, its inverting input terminal connected to the third power supply, and its output terminal connected to one end of the switching circuit as the output terminal of the reconfigurable unit. The third power source is used to provide a third reference voltage.

5. The long-short-range memory neural network control circuit according to claim 4, characterized in that, The capacitors of the capacitor array are connected one-to-one with the switches of the switching circuit.

6. The long-short-range memory neural network control circuit according to claim 1, characterized in that, The input gate memristor array consists of multiple input gate memristors connected in parallel, and the input gate memristor array is used to input at least one encoded input signal.

7. The long-short-range memory neural network control circuit according to claim 1, characterized in that, The reconfigurable unit is also used to store the current time output parameters and the current time state parameters.

8. The long-short-range memory neural network control circuit according to any one of claims 1-7, characterized in that, The input signal includes at least one of the current input parameters, the previous output parameters, and the state parameters of the reconfigurable cell at the previous time.

9. A long-short-range memory neural network control method, characterized in that, The method employs a long-short-range memory neural network control circuit as described in any one of claims 1-8, wherein the method includes the following steps: The input gate circuit processes at least one encoded input signal using an input gate memristor array and outputs a first current signal to the reconfigurable unit, so that the reconfigurable unit can convert the first current signal into a first voltage signal. After the first switch between the forget gate circuit and the reconfigurable unit is closed, the at least one input signal is processed by the forget gate memristor array and a second current signal is output. The second current signal is then converted into a second voltage signal by a current-to-voltage conversion circuit and applied to the transistor so as to discharge the capacitor of the reconfigurable unit by adjusting the current flowing through the transistor. The reconfigurable unit module's reconfiguration parameters are determined by the unit state configuration control circuit based on the current task requirements; and The reconfigurable unit reconstructs the current output parameters and the current unit state parameters based on the current task requirements, according to the first voltage signal and the reconfiguration parameters.

10. The method according to claim 9, characterized in that, After obtaining the current output parameters and current unit state parameters by reconstructing the data based on the current task requirements, the first voltage signal, the third voltage signal, and the reconstruction parameters, the method further includes: Store the output parameters and the state parameters at the current time.

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