A method for preparing a heterojunction battery

Abstract

The present invention relates to the technical field of solar cells, and specifically to a method for preparing a heterojunction battery, comprising: providing a semiconductor substrate layer; forming a doped semiconductor layer on at least one side of the semiconductor substrate layer; forming a transparent conductive film on the surface of the doped semiconductor layer on the side away from the semiconductor substrate layer, the transparent conductive film comprising an electrode region and a non-electrode region that are alternately arranged in sequence; forming a metal seed layer and an anti-oxidation layer on the surface of the transparent conductive film on the side away from the semiconductor substrate layer in sequence; removing the anti-oxidation layer in the electrode region; forming an electrode on the surface of the metal seed layer in the electrode region on the side away from the semiconductor substrate layer; removing the metal seed layer and the anti-oxidation layer in the non-electrode region. The formed heterojunction battery has a small electrode contact resistance and good adhesion. The use of an etching process can selectively remove the metal seed layer and the anti-oxidation layer in the non-electrode region, so the required pattern can be processed without mold opening, saving mold opening costs, and improving processing accuracy and flatness of the substrate layer.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a heterojunction cell. Background Art

[0002] In heterojunction cells, in order to collect carriers generated by the photoelectric effect, metallized electrodes are generally prepared by screen printing technology. For heterojunction cells, due to the particularity of its process, the curing temperature of the metallization paste cannot exceed 250°C, and is generally 150-200°C, so it is called low-temperature paste. Due to the presence of resin, the line resistivity of low-temperature paste is about 5μΩ·cm-9μΩ·cm; while in the high-temperature sintering paste of other crystalline silicon cells, its resistivity is about 2μΩ·cm-5μΩ·cm. The power loss of heterojunction cells caused by low-temperature metallization electrodes is much greater than that of other conventional high-temperature metallization cells.

[0003] In addition, due to the characteristics of the silver paste itself and the sintering characteristics, there will be holes after the paste forms the electrode, and the contact surface of the particles inside the electrode is not sufficient. Therefore, even if the conductivity of silver is better than that of copper, its high-temperature metallization paste resistivity is still higher than that of pure copper metal. It can be seen that since copper metal has smaller metal wire resistance and contact resistance, matching graphics has less shading area, so the conversion efficiency of heterojunction cells can be improved; in terms of cost, the price of metallic copper is about 1 / 100 of that of silver, which has a high cost-effectiveness, so it has received great attention from photovoltaic personnel. Copper electroplating has low-temperature characteristics, which is consistent with the process requirements of heterojunction cells, and the metallization cost of heterojunction cells accounts for about 50% of the non-silicon cost. Therefore, whether from the perspective of process or cost, copper electroplating and heterojunction cells are a perfect combination.

[0004] In the copper electroplating process of heterojunction batteries, the magnetron sputtering (PVD) method is generally used to prepare a pure copper seed layer. However, pure copper is very easy to oxidize. The oxidized copper seed layer has a very large impact on the efficiency and adhesion of copper electroplating. Even if acid is used to remove the oxide layer before forming the electrode, since the seed layer itself has been oxidized, the electroplating efficiency and adhesion of the electrode will deteriorate after pickling.

[0005] Therefore, it is necessary to provide a new method for preparing a heterojunction battery. Summary of the invention

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the defects of the heterojunction battery in the prior art, that is, the large contact resistance and poor adhesion of the electrode, thereby providing a method for preparing a heterojunction battery.

[0007] The present invention provides a method for preparing a heterojunction battery, comprising providing a semiconductor substrate layer; forming a doped semiconductor layer on at least one side of the semiconductor substrate layer; forming a transparent conductive film on the surface of the doped semiconductor layer on a side away from the semiconductor substrate layer, wherein the transparent conductive film comprises an electrode region and a non-electrode region that are alternately arranged in sequence; forming a stacked metal seed layer and an anti-oxidation layer in sequence on the surface of the transparent conductive film on a side away from the semiconductor substrate layer; removing the anti-oxidation layer in the electrode region; forming an electrode on the surface of the metal seed layer in the electrode region on a side away from the semiconductor substrate layer; and removing the metal seed layer and the anti-oxidation layer in the non-electrode region by an etching process.

[0008] Optionally, the material of the anti-oxidation layer includes one or more combinations of copper, nickel, and chromium, and the material of the metal seed layer includes one or more combinations of copper, nickel, and chromium. The material of the anti-oxidation layer and the material of the metal seed layer are not selected as the same material at the same time.

[0009] Optionally, the thickness of the anti-oxidation layer is 0.2 to 0.5 times the thickness of the metal seed layer.

[0010] Optionally, the thickness of the metal seed layer is 50nm-200nm, and the thickness of the anti-oxidation layer is 10nm-100nm.

[0011] Optionally, the process of forming the electrode includes an electroplating process.

[0012] Optionally, the step of removing the anti-oxidation layer of the electrode area includes: using an etching solution to remove the anti-oxidation layer of the electrode area; the step of removing the metal seed layer and the anti-oxidation layer of the non-electrode area includes: using an etching solution to remove the metal seed layer and the anti-oxidation layer of the non-electrode area; the reaction time of the etching solution with the anti-oxidation layer of the electrode area is less than the reaction time of the etching solution with the metal seed layer and the anti-oxidation layer of the non-electrode area.

[0013] Optionally, the etching solution includes sulfuric acid with a mass fraction of 0.2%-5%; the reaction time of the etching solution with the anti-oxidation layer in the electrode area is 2 seconds-10 seconds, and the reaction time of the etching solution with the metal seed layer and the anti-oxidation layer in the non-electrode area is 20 seconds-60 seconds.

[0014] Optionally, the process of forming the metal seed layer includes a physical vapor deposition process; and the process of forming the anti-oxidation layer includes a physical vapor deposition process.

[0015] Optionally, the metal seed layer and the anti-oxidation layer are formed in the same cavity.

[0016] Optionally, the step of forming the doped semiconductor layer includes: forming a first doped semiconductor layer on one side of the semiconductor substrate layer, and / or forming a second doped semiconductor layer on the other side of the semiconductor substrate layer; the step of forming a transparent conductive film on the surface of the doped semiconductor layer facing away from the semiconductor substrate layer includes: forming a first transparent conductive film on the surface of the first doped semiconductor layer facing away from the semiconductor substrate layer, and / or forming a second transparent conductive film on the surface of the second doped semiconductor layer facing away from the semiconductor substrate layer, the first transparent conductive film includes a first electrode area and a first non-electrode area alternately arranged in sequence, and the second transparent conductive film includes a second electrode area and a second non-electrode area alternately arranged in sequence; the step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the transparent conductive film facing away from the semiconductor substrate layer includes: sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the first transparent conductive film facing away from the semiconductor substrate layer A first metal seed layer and a first anti-oxidation layer are stacked, and / or, a second metal seed layer and a second anti-oxidation layer are stacked in sequence on the surface of the second transparent conductive film on the side away from the semiconductor substrate layer; the step of removing the anti-oxidation layer in the electrode area includes: removing the first anti-oxidation layer in the first electrode area, and / or, removing the second anti-oxidation layer in the second electrode area; the step of forming an electrode on the surface of the metal seed layer in the electrode area on the side away from the semiconductor substrate layer includes: forming a first electrode on the surface of the first metal seed layer in the first electrode area on the side away from the semiconductor substrate layer, and / or, forming a second electrode on the surface of the second metal seed layer in the second electrode area on the side away from the semiconductor substrate layer; the step of removing the metal seed layer and the anti-oxidation layer in the non-electrode area includes: removing the first metal seed layer and the first anti-oxidation layer in the first non-electrode area, and / or, removing the second metal seed layer and the second anti-oxidation layer in the second non-electrode area.

[0017] The technical solution of the present invention has the following advantages:

[0018] The preparation method of the heterojunction battery provided by the present invention comprises: providing a semiconductor substrate layer; forming a doped semiconductor layer on at least one side of the semiconductor substrate layer; forming a transparent conductive film on the surface of the doped semiconductor layer on the side away from the semiconductor substrate layer, the transparent conductive film comprising an electrode area and a non-electrode area arranged alternately in sequence; forming a stacked metal seed layer and an anti-oxidation layer on the surface of the transparent conductive film on the side away from the semiconductor substrate layer in sequence; removing the anti-oxidation layer in the electrode area; forming an electrode on the surface of the metal seed layer in the electrode area on the side away from the semiconductor substrate layer; and removing the metal seed layer and the anti-oxidation layer in the non-electrode area by an etching process. Since the anti-oxidation layer can prevent the metal seed layer from being oxidized, before forming the electrode, the anti-oxidation layer in the electrode area is first removed, and then the electrode is formed on the surface of the metal seed layer in the electrode area on the side away from the semiconductor substrate layer. Because the electrode is directly formed on the surface of the metal seed layer that has not been oxidized, good contact can be formed between the metal seed layer and the electrode, reducing the contact resistance of the heterojunction battery and improving the conductivity of the heterojunction battery. In summary, the heterojunction battery formed by the preparation method of the heterojunction battery has a small contact resistance and good electrode adhesion. The etching process can selectively remove the metal seed layer and the anti-oxidation layer in the non-electrode area, so the required pattern can be processed without mold opening, saving mold opening costs. The etching process can also improve processing accuracy and the flatness of the semiconductor substrate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A flow chart of a method for preparing a heterojunction battery provided in one embodiment of the present invention;

[0021] Figure 2 - Figure 5 A flow chart of a method for preparing a heterojunction battery provided in one embodiment of the present invention.

[0022] Description of reference numerals;

[0023] 1-Semiconductor substrate layer;

[0024] 21-first doped semiconductor layer; 22-second doped semiconductor layer;

[0025] 31 - first passivation layer; 32 - second passivation layer;

[0026] 41 - a first transparent conductive film; 42 - a second transparent conductive film;

[0027] 51 - a first metal seed layer; 52 - a second metal seed layer;

[0028] 61 - first anti-oxidation layer; 62 - second anti-oxidation layer;

[0029] 71 - first electrode; 72 - second electrode;

[0030] M1 – first mask; M2 – second mask. DETAILED DESCRIPTION

[0031] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0033] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] Example 1

[0036] This embodiment provides a method for preparing a heterojunction battery. Figure 1 , including the following steps:

[0037] Step S1: providing a semiconductor substrate layer;

[0038] Step S2: forming a doped semiconductor layer on at least one side of the semiconductor substrate layer;

[0039] Step S3: forming a transparent conductive film on a surface of the doped semiconductor layer facing away from the semiconductor substrate layer, wherein the transparent conductive film comprises electrode regions and non-electrode regions alternately arranged in sequence;

[0040] Step S4: forming a stacked metal seed layer and an anti-oxidation layer in sequence on the surface of the transparent conductive film on the side away from the semiconductor substrate layer;

[0041] Step S5: removing the anti-oxidation layer in the electrode area;

[0042] Step S6: forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer;

[0043] Step S7: using an etching process to remove the metal seed layer and the anti-oxidation layer in the non-electrode area.

[0044] The preparation method of the heterojunction battery provided in this embodiment, since the anti-oxidation layer can prevent the metal seed layer from being oxidized, before forming the electrode, the anti-oxidation layer in the electrode area is first removed, and then the electrode is formed on the surface of the metal seed layer in the electrode area that is away from the semiconductor substrate layer. Because the electrode is directly formed on the surface of the metal seed layer that has not been oxidized, a good contact can be formed between the metal seed layer and the electrode, reducing the contact resistance of the heterojunction battery and improving the conductivity of the heterojunction battery. In summary, the heterojunction battery formed by the preparation method of the heterojunction battery has a small contact resistance and good electrode adhesion. The use of an etching process can selectively remove the metal seed layer and the anti-oxidation layer in the non-electrode area, so the required pattern can be processed without mold opening, saving mold opening costs, and the etching process can improve the processing accuracy and the flatness of the semiconductor substrate layer.

[0045] In step S1, refer to Figure 2 , providing a semiconductor substrate layer 1. Specifically, it also includes texturing the semiconductor substrate layer 1. In one embodiment, the light-receiving surface of the semiconductor substrate layer is texturized, and in other embodiments, both the light-receiving surface and the backlight surface of the semiconductor substrate layer are texturized. The texturing treatment utilizes the difference in the crystal orientation corrosion rate of the semiconductor substrate layer with a high-temperature and low-concentration alkaline solution, so that the surface of the semiconductor substrate layer can form a pyramid velvet light-trapping structure, which is beneficial to increase the reflectivity of the heterojunction battery by 9%-11%.

[0046] In step S2, the step of forming the doped semiconductor layer includes: forming a first doped semiconductor layer on one side of the semiconductor substrate layer, and / or forming a second doped semiconductor layer on the other side of the semiconductor substrate layer. Specifically, the step of forming the doped semiconductor layer includes: forming the first doped semiconductor layer on one side of the semiconductor substrate layer, or forming the second doped semiconductor layer on the other side of the semiconductor substrate layer, or forming the first doped semiconductor layer on one side of the semiconductor substrate layer and forming the second doped semiconductor layer on the other side of the semiconductor substrate layer.

[0047] In one embodiment, continue to refer to Figure 2 The step of forming the doped semiconductor layer includes: forming a first doped semiconductor layer 21 on one side of the semiconductor substrate layer 1 and forming a second doped semiconductor layer 22 on the other side of the semiconductor substrate layer 1 .

[0048] In one embodiment, the process of forming the first doped semiconductor layer 21 includes a plasma enhanced chemical vapor deposition process, and the process of forming the second doped semiconductor layer 22 includes a plasma enhanced chemical vapor deposition process.

[0049] In one embodiment, the material of the first doped semiconductor layer 21 includes amorphous silicon, nanocrystalline silicon, oxygen-doped amorphous silicon, oxygen-doped nanocrystalline silicon, carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon doped with the first conductive ions.

[0050] In one embodiment, the thickness of the first doped semiconductor layer 21 is 5 nm-40 nm, for example, 10 nm, 25 nm, 30 nm or 35 nm.

[0051] In one embodiment, the material of the second doped semiconductor layer 22 includes amorphous silicon, nanocrystalline silicon, oxygen-doped amorphous silicon, oxygen-doped nanocrystalline silicon, carbon-doped amorphous silicon or carbon-doped nanocrystalline silicon doped with the second conductive ions.

[0052] In one embodiment, the thickness of the second doped semiconductor layer 22 is 5 nm-50 nm, for example, 10 nm, 25 nm, 30 nm or 35 nm.

[0053] In one embodiment, before forming the doped semiconductor layer on at least one side of the semiconductor substrate layer, the method further includes: forming a passivation layer on at least one side of the semiconductor substrate layer; the step of forming the passivation layer includes: forming a first passivation layer on one side of the semiconductor substrate layer, and / or forming a second passivation layer on the other side of the semiconductor substrate layer. Specifically, forming the passivation layer on at least one side of the semiconductor substrate layer includes: forming the first passivation layer on one side of the semiconductor substrate layer, or forming the second passivation layer on the other side of the semiconductor substrate layer, or forming the first passivation layer on one side of the semiconductor substrate layer and forming the second passivation layer on the other side of the semiconductor substrate layer. After forming the first doped semiconductor layer, the first passivation layer is located between the semiconductor substrate layer and the first doped semiconductor layer, and after forming the second doped semiconductor layer, the second passivation layer is located between the semiconductor substrate layer and the second doped semiconductor layer.

[0054] In one embodiment, continue to refer to Figure 2 Forming a passivation layer on at least one side of the semiconductor substrate layer includes: forming a first passivation layer 31 on one side of the semiconductor substrate layer 1 and forming a second passivation layer 32 on the other side of the semiconductor substrate layer 1 .

[0055] In one embodiment, the process of forming the first passivation layer 31 includes a plasma enhanced chemical vapor deposition process, and the process of forming the second passivation layer 32 includes a plasma enhanced chemical vapor deposition process.

[0056] In one embodiment, the material of the first passivation layer 31 includes amorphous silicon or nanocrystalline silicon, and the material of the second passivation layer 32 includes amorphous silicon or nanocrystalline silicon.

[0057] In one embodiment, the thickness of the first passivation layer 31 is 1 nm-10 nm, such as 3 nm, 6 nm, 8 nm or 9 nm. The thickness of the second passivation layer 32 is 1 nm-10 nm, such as 3 nm, 6 nm, 8 nm or 9 nm.

[0058] In step S3, the step of forming a transparent conductive film on the surface of the doped semiconductor layer away from the semiconductor substrate layer includes: forming a first transparent conductive film on the surface of the first doped semiconductor layer away from the semiconductor substrate layer, and / or forming a second transparent conductive film on the surface of the second doped semiconductor layer away from the semiconductor substrate layer, the first transparent conductive film includes a first electrode region and a first non-electrode region that are alternately arranged in sequence, and the second transparent conductive film includes a second electrode region and a second non-electrode region that are alternately arranged in sequence. Specifically, the step of forming a transparent conductive film on the surface of the doped semiconductor layer away from the semiconductor substrate layer includes: forming the first transparent conductive film on the surface of the first doped semiconductor layer away from the semiconductor substrate layer, or forming the second transparent conductive film on the surface of the second doped semiconductor layer away from the semiconductor substrate layer, or forming the first transparent conductive film on the surface of the first doped semiconductor layer away from the semiconductor substrate layer and forming the second transparent conductive film on the surface of the second doped semiconductor layer away from the semiconductor substrate layer.

[0059] In one embodiment, continue to refer to Figure 2 The step of forming a transparent conductive film on the surface of the doped semiconductor layer facing away from the semiconductor substrate layer includes: forming a first transparent conductive film 41 on the surface of the first doped semiconductor layer 21 facing away from the semiconductor substrate layer 1 and forming a second transparent conductive film 42 on the surface of the second doped semiconductor layer 22 facing away from the semiconductor substrate layer 1.

[0060] In one embodiment, the process of forming the first transparent conductive film 41 includes a physical vapor deposition process, and the process of forming the second transparent conductive film 42 includes a physical vapor deposition process.

[0061] In one embodiment, the thickness of the first transparent conductive film 41 is 80 nm-90 nm, for example, 85 nm; the thickness of the second transparent conductive film 42 is 90 nm-120 nm, for example, 95 nm.

[0062] In step S4, the step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the side of the transparent conductive film away from the semiconductor substrate layer includes: sequentially forming a stacked first metal seed layer and a first anti-oxidation layer on the surface of the side of the first transparent conductive film away from the semiconductor substrate layer, and / or, sequentially forming a stacked second metal seed layer and a second anti-oxidation layer on the surface of the side of the second transparent conductive film away from the semiconductor substrate layer. Specifically, the step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the side of the transparent conductive film away from the semiconductor substrate layer includes: sequentially forming a stacked first metal seed layer and a first anti-oxidation layer on the surface of the side of the first transparent conductive film away from the semiconductor substrate layer, or sequentially forming a stacked second metal seed layer and a second anti-oxidation layer on the surface of the side of the second transparent conductive film away from the semiconductor substrate layer, or sequentially forming a stacked first metal seed layer and a first anti-oxidation layer on the surface of the side of the first transparent conductive film away from the semiconductor substrate layer and sequentially forming a stacked second metal seed layer and a second anti-oxidation layer on the surface of the side of the second transparent conductive film away from the semiconductor substrate layer.

[0063] In one embodiment, reference Figure 3 The step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on the surface of the transparent conductive film facing away from the semiconductor substrate layer includes: sequentially forming a stacked first metal seed layer 51 and a first anti-oxidation layer 61 on the surface of the first transparent conductive film 41 facing away from the semiconductor substrate layer 1, and sequentially forming a stacked second metal seed layer 52 and a second anti-oxidation layer 62 on the surface of the second transparent conductive film 42 facing away from the semiconductor substrate layer.

[0064] In one embodiment, the process of forming the metal seed layer includes a physical vapor deposition process, and the process of forming the anti-oxidation layer includes a physical vapor deposition process.

[0065] In one embodiment, the thickness of the anti-oxidation layer is 0.2 to 0.5 times, for example, 0.3 times, the thickness of the metal seed layer.

[0066] In one embodiment, the material of the anti-oxidation layer includes one or more of copper, nickel, and chromium. In other embodiments, the material of the metal seed layer may also include other metal elements or mixed metals.

[0067] In one embodiment, the material of the metal seed layer includes one or more of copper, nickel or chromium. The material of the anti-oxidation layer is selected to be different from the material of the metal seed layer. In other embodiments, the material of the metal seed layer may also include other metal elements or mixed metals.

[0068] In one embodiment, the thickness of the metal seed layer is 50nm-200nm, for example, 55nm, 60nm, 70nm, 85nm, 120nm, 180nm; if the thickness of the metal seed layer is less than 50nm, the effect of improving the electrode adhesion and conductivity is not obvious; if the thickness of the metal seed layer is greater than 200nm, it not only wastes resources but also increases the time to form the metal seed layer.

[0069] In one embodiment, the thickness of the anti-oxidation layer is 10nm-100nm, for example 20nm, 25nm, 50nm, 65nm, 75nm, 80nm; if the thickness of the anti-oxidation layer is less than 10nm, the effect of preventing the metal seed layer from oxidizing is not obvious; if the thickness of the anti-oxidation layer is greater than 100nm, resources are wasted.

[0070] In one embodiment, the metal seed layer and the anti-oxidation layer are formed in the same cavity. The specific method is to add a target position in the cavity of the physical vapor deposition process equipment. This is conducive to simplifying the process and improving the efficiency of preparing heterojunction batteries. It is also conducive to isolating oxygen when forming the anti-oxidation layer to avoid oxidation of the metal seed layer due to replacement of the cavity or target material.

[0071] In step S5, the step of removing the anti-oxidation layer of the electrode region includes: removing the first anti-oxidation layer of the first electrode region, and / or removing the second anti-oxidation layer of the second electrode region. Specifically, the step of removing the anti-oxidation layer of the electrode region includes: removing the first anti-oxidation layer of the first electrode region, or removing the second anti-oxidation layer of the second electrode region, or removing the first anti-oxidation layer of the first electrode region and removing the second anti-oxidation layer of the second electrode region.

[0072] In step S5, the step of removing the anti-oxidation layer of the electrode area includes: removing the anti-oxidation layer of the electrode area by using an etching solution. The etching solution includes sulfuric acid, and the mass fraction of the sulfuric acid is 0.2%-5%, such as 1%, 2% or 4%; the reaction time of the etching solution and the anti-oxidation layer of the electrode area is 2 seconds-10 seconds, such as 5 seconds, 7 seconds or 8 seconds.

[0073] In one embodiment, reference Figure 4 , removing the anti-oxidation layer of the electrode area, the steps include: using an etching solution to remove the first anti-oxidation layer of the first electrode area and the second anti-oxidation layer of the second electrode area, the etching solution includes sulfuric acid, the mass fraction of sulfuric acid is 4%, the reaction time of the etching solution with the first anti-oxidation layer of the first electrode area is 8 seconds, and the reaction time of the etching solution with the second anti-oxidation layer of the second electrode area is 8 seconds.

[0074] In step S6, the step of forming an electrode on a side surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer includes: forming a first electrode on a side surface of the first metal seed layer in the first electrode region facing away from the semiconductor substrate layer, and / or forming a second electrode on a side surface of the second metal seed layer in the second electrode region facing away from the semiconductor substrate layer. Specifically, the step of forming an electrode on a side surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer includes: forming a first electrode on a side surface of the first metal seed layer in the first electrode region facing away from the semiconductor substrate layer, or forming a second electrode on a side surface of the second metal seed layer in the second electrode region facing away from the semiconductor substrate layer, or forming a first electrode on a side surface of the first metal seed layer in the first electrode region facing away from the semiconductor substrate layer and forming a second electrode on a side surface of the second metal seed layer in the second electrode region facing away from the semiconductor substrate layer.

[0075] In one embodiment, the process of forming the electrode includes an electroplating process, and the material of the electrode includes copper, which is conducive to forming a good contact between the electrode and the metal seed layer.

[0076] In one embodiment, the width of the electrode is 5 μm-30 μm, for example, 10 μm, 20 μm or 25 μm.

[0077] In one embodiment, the height of the electrode is 5 μm-25 μm, for example, 10 μm, 15 μm or 20 μm.

[0078] In one embodiment, reference Figure 4 , an electrode is formed on a surface of a metal seed layer in an electrode region facing away from the semiconductor substrate layer, the steps comprising: forming a first electrode 71 on a surface of a first metal seed layer 51 in a first electrode region facing away from the semiconductor substrate layer 1, and forming a second electrode 72 on a surface of a second metal seed layer 52 in a second electrode region facing away from the semiconductor substrate layer 1.

[0079] In step S7, the step of removing the metal seed layer and the anti-oxidation layer of the non-electrode area includes: removing the first metal seed layer and the first anti-oxidation layer of the first non-electrode area, and / or removing the second metal seed layer and the second anti-oxidation layer of the second non-electrode area. Specifically, the step of removing the metal seed layer and the anti-oxidation layer of the non-electrode area includes: removing the first metal seed layer and the first anti-oxidation layer of the first non-electrode area, or removing the second metal seed layer and the second anti-oxidation layer of the second non-electrode area, or removing the first metal seed layer and the first anti-oxidation layer of the first non-electrode area and removing the second metal seed layer and the second anti-oxidation layer of the second non-electrode area.

[0080] In one embodiment, an etching solution is used to remove the metal seed layer and the anti-oxidation layer in the non-electrode area, and the reaction time of the etching solution with the anti-oxidation layer in the electrode area is less than the reaction time of the etching solution with the metal seed layer and the anti-oxidation layer in the non-electrode area. The etching solution includes sulfuric acid, and the mass fraction of the sulfuric acid is 0.2%-5%, for example, 1.2%, 2%, 3% or 4%, and the reaction time of the etching solution with the metal seed layer and the anti-oxidation layer in the non-electrode area is 20 seconds to 60 seconds, for example, 30 seconds, 40 seconds or 50 seconds.

[0081] In one embodiment, a photoresist is stacked on the metal seed layer and the anti-oxidation layer in the non-electrode region, the photoresist has a specific shape, and the metal seed layer and the anti-oxidation layer covered by the photoresist are removed by plasma etching, sputtering etching or reactive ion etching.

[0082] In one embodiment, reference Figure 5 , remove the first metal seed layer 51 and the first anti-oxidation layer 61 in the first non-electrode area, and remove the second metal seed layer 52 and the second anti-oxidation layer 62 in the second non-electrode area.

[0083] In one embodiment, the etching solution reacts with the first metal seed layer and the first anti-oxidation layer in the first non-electrode region for 30 seconds; the etching solution reacts with the second metal seed layer and the second anti-oxidation layer in the second non-electrode region for 30 seconds, and the etching solution used includes sulfuric acid, and the mass fraction of the sulfuric acid is 4%. In other embodiments, the etching solution can also be other types of acidic solutions.

[0084] In one embodiment, before removing the anti-oxidation layer in the electrode region, the method further includes: forming a mask on a surface of the anti-oxidation layer in the non-electrode region that is away from the semiconductor substrate layer, wherein the mask exposes the anti-oxidation layer in the electrode region. Figure 4 A first mask M1 is formed on a surface of the first anti-oxidation layer 61 in the first non-electrode region that is away from the semiconductor substrate layer 1 , and a second mask M2 is formed on a surface of the second anti-oxidation layer 62 in the second non-electrode region that is away from the semiconductor substrate layer 1 .

[0085] In one embodiment, the mask is a dry film.

[0086] In another embodiment, the mask is a wet film, and the wet film needs to be dried before forming the electrode.

[0087] In another embodiment, the mask is formed by printing.

[0088] In one embodiment, the width of the pattern of the mask is 5 μm-30 μm, such as 10 μm, 20 μm or 25 μm, and the height of the pattern of the mask is 5 μm-25 μm, such as 10 μm, 15 μm or 20 μm.

[0089] The preparation method of the heterojunction battery also includes: after forming an electrode on the surface of the metal seed layer in the electrode area facing away from the semiconductor substrate layer, and before removing the metal seed layer and the anti-oxidation layer in the non-electrode area, it also includes: removing the mask.

[0090] In one embodiment, the mask is removed by soaking in an alkaline solution, the alkaline solution includes a sodium hydroxide solution or a potassium hydroxide solution, the mass fraction concentration of the alkaline solution is 1%-5%, and the soaking time is 1 min-5 min, for example, 3 min.

[0091] Comparative Example 1

[0092] The preparation method of the heterojunction battery provided in this comparative example is different from the preparation method of the heterojunction battery provided in Example 1 in that the preparation method of the heterojunction battery provided in this comparative example does not include: forming an anti-oxidation layer, and the preparation method of the heterojunction battery provided in this comparative example includes: before forming an electrode in the electrode area, performing hydrogen plasma treatment on the metal seed layer to remove the oxide layer and dirt on the surface of the metal seed layer, and then forming the electrode.

[0093] Comparative Example 2

[0094] The preparation method of the heterojunction battery provided in this comparative example is different from the preparation method of the heterojunction battery provided in Example 1 in that the heterojunction battery provided in this comparative example does not include: forming an anti-oxidation layer, and the preparation method of the heterojunction battery provided in this comparative example includes: before forming an electrode in the electrode area, forming a protective layer on the surface of the metal seed layer away from the semiconductor substrate layer, the material of the protective layer includes a mixture of copper and copper oxide, then removing the copper oxide in the protective layer to form a hollow copper film, and then forming an electrode, and filling the hollow area during the process of forming the electrode.

[0095] Test Example 1

[0096] Although the preparation method of the heterojunction battery provided in Comparative Example 1 can remove the oxide layer and surface dirt on the surface of the metal seed layer, it will also damage the surface of the metal seed layer and pollute the cavity of the plasma processing equipment. After removing the oxide layer on the surface of the metal seed layer, the metal seed layer will also be oxidized. Therefore, it cannot solve the oxidation problem in the long term. For mass production, the plasma processing equipment, process and cost will increase.

[0097] In the preparation method of the heterojunction battery provided in Comparative Example 1, the presence of copper oxide in the protective layer on the surface of the metal seed layer is not conducive to the formation of the electrode, and copper cannot protect the metal seed layer after oxidation. When the copper oxide is removed, the metal seed layer will be destroyed, causing the adhesion and contact resistance of the electrode to deteriorate.

[0098] The method for preparing a heterojunction battery provided in Example 1 can completely prevent the metal seed layer from being oxidized and is very easy to mass produce.

[0099] This test example tests the heterojunction batteries formed in Example 1, Comparative Example 1, and Comparative Example 2. Compared with the heterojunction battery formed in Comparative Example 1, the electroplating efficiency of the electrode formed in the heterojunction battery formed in Example 1 is relatively improved by 10%, and the contact resistance of the heterojunction battery formed in Example 1 is relatively reduced by 50%; compared with the heterojunction battery formed in Comparative Example 2, the contact resistance of the heterojunction battery formed in Example 1 is relatively reduced by 50%.

[0100] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for preparing a heterojunction battery, characterized in that: include: providing a semiconductor substrate layer; forming a doped semiconductor layer on at least one side of the semiconductor substrate layer; Forming a transparent conductive film on a surface of the doped semiconductor layer facing away from the semiconductor substrate layer, wherein the transparent conductive film comprises electrode regions and non-electrode regions alternately arranged in sequence; Forming a stacked metal seed layer and an anti-oxidation layer in sequence on a surface of the transparent conductive film on a side away from the semiconductor substrate layer; removing the anti-oxidation layer of the electrode area; forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer; The metal seed layer and the anti-oxidation layer in the non-electrode area are removed by an etching process; wherein, The material of the anti-oxidation layer includes one or more combinations of copper, nickel, and chromium, the material of the metal seed layer includes one or more combinations of copper, nickel, and chromium, and the material of the anti-oxidation layer is the same as the material of the metal seed layer; The thickness of the anti-oxidation layer is 0.2 to 0.5 times the thickness of the metal seed layer.

2. The method for preparing a heterojunction battery according to claim 1, characterized in that: The thickness of the metal seed layer is 50nm-200nm, and the thickness of the anti-oxidation layer is 10nm-100nm.

3. The method for preparing a heterojunction battery according to claim 1, characterized in that: The process of forming the electrodes includes an electroplating process.

4. The method for preparing a heterojunction battery according to claim 1, characterized in that: The step of removing the anti-oxidation layer of the electrode region comprises: removing the anti-oxidation layer of the electrode region by using an etching solution; The step of removing the metal seed layer and the anti-oxidation layer in the non-electrode area comprises: removing the metal seed layer and the anti-oxidation layer in the non-electrode area by using an etching solution; The reaction time between the etching solution and the anti-oxidation layer in the electrode area is shorter than the reaction time between the etching solution and the metal seed layer and the anti-oxidation layer in the non-electrode area.

5. The method for preparing a heterojunction battery according to claim 4, characterized in that: The etching solution includes sulfuric acid, and the mass fraction of the sulfuric acid is 0.2%-5%; The reaction time between the etching solution and the anti-oxidation layer in the electrode area is 2 seconds to 10 seconds, and the reaction time between the etching solution and the metal seed layer and the anti-oxidation layer in the non-electrode area is 20 seconds to 60 seconds.

6. The method for preparing a heterojunction battery according to claim 1, characterized in that: The process of forming the metal seed layer includes a physical vapor deposition process; the process of forming the anti-oxidation layer includes a physical vapor deposition process.

7. The method for preparing a heterojunction battery according to claim 1, characterized in that: The metal seed layer and the anti-oxidation layer are formed in the same cavity.

8. The method for preparing a heterojunction battery according to claim 1, characterized in that: The step of forming the doped semiconductor layer comprises: forming a first doped semiconductor layer on one side of the semiconductor substrate layer, and / or forming a second doped semiconductor layer on the other side of the semiconductor substrate layer; The step of forming a transparent conductive film on a surface of the doped semiconductor layer facing away from the semiconductor substrate layer comprises: forming a first transparent conductive film on a surface of the first doped semiconductor layer facing away from the semiconductor substrate layer, and / or forming a second transparent conductive film on a surface of the second doped semiconductor layer facing away from the semiconductor substrate layer, wherein the first transparent conductive film comprises a first electrode region and a first non-electrode region which are alternately arranged in sequence, and the second transparent conductive film comprises a second electrode region and a second non-electrode region which are alternately arranged in sequence; The step of sequentially forming a stacked metal seed layer and an anti-oxidation layer on a surface of the transparent conductive film facing away from the semiconductor substrate layer comprises: sequentially forming a stacked first metal seed layer and a first anti-oxidation layer on a surface of the first transparent conductive film facing away from the semiconductor substrate layer, and / or sequentially forming a stacked second metal seed layer and a second anti-oxidation layer on a surface of the second transparent conductive film facing away from the semiconductor substrate layer; The step of removing the anti-oxidation layer of the electrode region comprises: removing the first anti-oxidation layer of the first electrode region, and / or removing the second anti-oxidation layer of the second electrode region; The step of forming an electrode on a surface of the metal seed layer in the electrode region facing away from the semiconductor substrate layer comprises: forming a first electrode on a surface of the first metal seed layer in the first electrode region facing away from the semiconductor substrate layer, and / or forming a second electrode on a surface of the second metal seed layer in the second electrode region facing away from the semiconductor substrate layer; The step of removing the metal seed layer and the anti-oxidation layer in the non-electrode area includes: removing the first metal seed layer and the first anti-oxidation layer in the first non-electrode area, and / or removing the second metal seed layer and the second anti-oxidation layer in the second non-electrode area.

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