Optimization design method, device, medium and terminal of SRAM bit cell based on machine learning

Abstract

The present application provides an optimization design method, device, terminal and medium for SRAM bit cells based on machine learning, which obtains performance parameters by collecting the real parameters of the SRAM bit cells, and arranging and combining the various parameters in the SRAM bit cells and simulating them. A size prediction model is constructed based on the real parameters and performance parameters of the SRAM bit cells to predict the size of the SRAM bit cells. The automated process reduces the possibility of errors in the manual parameter adjustment process, improves the reliability and consistency of the design, and provides an efficient and accurate design tool for the SRAM bit cell design, thereby greatly reducing the time cost, labor cost and economic cost of the design, accelerating the development process of the SRAM bit cell, and improving the flexibility of the SRAM bit cell design.

Description

Technical Field

[0001] The present application relates to the field of chip design, and in particular to an optimization design method, device, medium and terminal for SRAM bit cells based on machine learning. Background Art

[0002] SRAM (Static Random-Access Memory) is a static random access memory used to store and read data. Compared with dynamic random access memory (DRAM), SRAM has faster access speed and lower power consumption. When the SRAM receives a write instruction, the data is written to the target storage unit. The write operation transfers the data to the trigger circuit of the target storage unit through the control line, and the state of the trigger is updated to the written data value. When the data in the storage unit needs to be read, the read operation transfers the data of the target storage unit to the output line through the control line for the external circuit to read. The read operation does not change the content of the storage unit. The input of SRAM includes write data, write address and write enable signal, which are used to write data to the target storage unit. The output includes read data and read enable signal, which are used to read data from the target storage unit.

[0003] The design of the SRAM bit cell is automatically compiled and generated based on the parameters provided by the manufacturer. The parameters designed by the manufacturer include power consumption, speed and other performance, but the parameters of the device itself in the SRAM are not concerned. It is also impossible to set the device parameters of the SRAM in the SPICE model, so the parameter values ​​of the SRAM device cannot be provided. SRAMs from different manufacturers are provided by different IP suppliers, which leads to large differences in the size of the bit cells. In the design process, in order to save area, the bit cells use a large number of minimum sizes in the design rules. However, the parameters of the minimum size are sensitive to process fluctuations. Therefore, each manufacturer uses special process conditions and process control to match the requirements of the SRAM parameters. In particular, when the product is transferred, clear parameter requirements must be put forward for the devices in the SRAM, otherwise the process flow cannot be determined, which greatly increases the complexity of the design and reduces the flexibility of the design. And it cannot meet the personalized needs of users. At the same time, if it is necessary to design the bit cells of the SRAM, human experience tuning will produce a large deviation, thereby reducing the tuning efficiency. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the purpose of the present application is to provide an optimization design method, device, medium and terminal for SRAM bit cells based on machine learning, so as to solve the problems existing in the prior art of SRAM bit cell design, such as complexity, poor flexibility, inability to meet the personalized needs of users, large deviation and low efficiency of manual tuning.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an optimization design method for an SRAM bit cell based on machine learning, comprising: collecting an SRAM bit cell parameter set of a process node; inputting the SRAM bit cell parameter set into simulation software for simulation to generate a performance indicator set; based on a machine learning algorithm, constructing a parameter prediction model through the performance indicator set and the SRAM bit cell parameter set; inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to output an optimized parameter set of the SRAM bit cell to be designed.

[0006] In some embodiments of the first aspect of the present application, based on a machine learning algorithm, a parameter prediction model is constructed using the performance indicator set and the SRAM bit cell parameter set, including: dividing the performance indicator set and the SRAM bit cell parameter set into a training set and a test set; inputting the training set into the parameter prediction model for model training; and inputting the test set into the trained prediction model to evaluate the performance of the prediction model.

[0007] In some embodiments of the first aspect of the present application, the training set is input into the parameter prediction model for model training, including: inputting the performance indicator set in the training set into the parameter prediction model to generate a predicted SRAM bit cell parameter set; constructing a loss function based on the predicted SRAM bit cell parameter set and the SRAM bit cell parameter set corresponding to the performance indicator set in the training set; and training and optimizing the parameter prediction model based on the loss function.

[0008] In some embodiments of the first aspect of the present application, the SRAM bit cell parameter set is input into simulation software for simulation to generate a performance indicator set, including: arranging and combining multiple types of parameters contained in the SRAM bit cell parameter set, and inputting each combination into the simulation software for simulation to generate the performance indicator set consisting of performance indicators of multiple combinations.

[0009] In some embodiments of the first aspect of the present application, the machine learning algorithm includes: K-nearest neighbor algorithm, decision tree algorithm, regression algorithm, support vector machine algorithm and neural network.

[0010] In some embodiments of the first aspect of the present application, the SRAM bit cell parameter set includes at least one of the following parameter types: one or more of process angle parameters, threshold voltage parameters, and transistor size parameters.

[0011] In some embodiments of the first aspect of the present application, the performance indicators in the performance indicator set include: one or more of: read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, and write power consumption.

[0012] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an optimization design device for an SRAM bit cell based on machine learning, including: a data acquisition module: used to collect the SRAM bit cell parameter set of the process node; input the SRAM bit cell parameter set into the simulation software for simulation to generate a performance indicator set; a model building module model building module: used to build a parameter prediction model based on the machine learning algorithm through the performance indicator set and the SRAM bit cell parameter set; an automatic design module: used to input the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to generate an optimized parameter set for the SRAM bit cell to be designed.

[0013] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the machine learning-based SRAM bit cell optimization design method is implemented.

[0014] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides an electronic terminal, including: a processor and a memory; the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the terminal executes the machine learning-based SRAM bit cell optimization design method.

[0015] As described above, the present application relates to an optimization design method, device, medium and terminal for SRAM bit cells based on machine learning in the field of chip design, and has the following beneficial effects: Through the present invention, the reliability and consistency of the SRAM bit cell storage design are improved, while the design time and labor costs are reduced, the development process of the SRAM bit cell is accelerated, the design performance and product competitiveness are improved, and the SRAM bit cell can be customized according to user needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of an embodiment of an optimization design method for an SRAM bit cell based on machine learning in the present application is shown.

[0017] Figure 2 A schematic diagram of the flow of simulation performance data collection in an embodiment of an optimization design method for an SRAM bit cell based on machine learning of the present application is shown.

[0018] Figure 3A flow chart of the model training process in an embodiment of an SRAM bit cell optimization design method based on machine learning of the present application is shown.

[0019] Figure 4 A structural schematic diagram of an embodiment of an optimization design device for an SRAM bit cell based on machine learning in the present application is shown.

[0020] Figure 5 A structural schematic diagram of an electronic terminal embodiment of the present application with an optimized design of an SRAM bit cell based on machine learning is shown. DETAILED DESCRIPTION

[0021] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0022] It should be noted that in the following description, with reference to the accompanying drawings, several embodiments of the present application are described in the accompanying drawings. It should be understood that other embodiments may also be used, and mechanical composition, structure, electrical and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present application is limited only by the claims of the published patents. The terms used here are only for describing specific embodiments and are not intended to limit the present application. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0023] In this application, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix", "hold" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0025] In order to solve the problems in the above-mentioned background technology, the present invention provides a method for solving the problems existing in the prior art in the process of SRAM bit cell design, such as high complexity, poor flexibility, inability to meet the personalized needs of users, large manual tuning deviation, and low efficiency. At the same time, in order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0026] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0027] <1> SRAM (Static Random-Access Memory): Static Random-Access Memory (SRAM) is a type of random access memory. The so-called "static" means that as long as this memory remains powered, the data stored in it can be kept constant. When the power supply stops, the data stored in SRAM will still disappear (called volatile memory).

[0028] <2> SRAM circuit composition: Static Random-Access Memory (SRAM) is a type of random access memory. The so-called "static" means that as long as this memory remains powered, the data stored in it can be kept constant. When the power supply stops, the data stored in SRAM will still disappear (called volatile memory).

[0029] <3> SRAM memory cell: The memory cell of SRAM is usually composed of 6 transistors, 4 of which are transmission gates for storing data, and the other 2 are pass gates for controlling read and write operations. The transmission gate is composed of two complementary MOSFETs (metal oxide semiconductor field effect transistors), which are connected to the two nodes of the memory cell respectively. The pass gate is composed of two MOSFETs, one for read operation and one for write operation.

[0030] <4> Bit unit: In a computer, a bit unit is the smallest storage unit used to store the value of a binary bit (0 or 1).

[0031] <5> Process corner: In semiconductor manufacturing, process corner refers to the angle or edge between different areas or layers on a chip.

[0032] <6> Tube threshold voltage: In semiconductor devices, the tube threshold voltage refers to the voltage threshold that controls the tube to be turned on or off.

[0033] <7> Read / write static noise margin: In memory, read / write static noise margin refers to the degree of noise or interference that the memory cell can tolerate when reading or writing data.

[0034] <8> k-nearest neighbor algorithm: The k-nearest neighbor algorithm is a machine learning algorithm for classification and regression that calculates the distance between samples and selects the k nearest neighbors for prediction or classification.

[0035] The embodiments of the present invention provide an optimization design method for an SRAM bit cell based on machine learning, a system for the optimization design method for an SRAM bit cell based on machine learning, and a storage medium storing an executable program for implementing the optimization design method for an SRAM bit cell based on machine learning. As far as the implementation of the optimization design method for an SRAM bit cell based on machine learning is concerned, the embodiments of the present invention will describe an exemplary implementation scenario of the optimization design of an SRAM bit cell based on machine learning.

[0036] like Figure 1 As shown, a flow chart of an optimization design method of an SRAM bit cell based on machine learning in an embodiment of the present invention is shown. The optimization design method of an SRAM bit cell based on machine learning in this embodiment mainly includes the following steps:

[0037] Step S11: Collecting the SRAM bit cell parameter set of the process node.

[0038] In one embodiment of the present invention, the parameter types included in the SRAM bit cell parameter set include: one or more of process angle parameters, threshold voltage parameters, and transistor size parameters. Specifically, the SRAM bit cells of a specific process node are collected, and multiple sets of sizes are provided for the MOSFET transistors in the driver tube (PU), load tube (PG), and transmission tube (SP). The present invention does not limit the number of collected MOSFET sizes.

[0039] In one embodiment of the present invention, the threshold voltage parameters of the SRAM bit cell of the specific process node are collected from historical data. It is worth noting that setting different threshold voltages in the SRAM cell will affect the reliability and power consumption of the memory. A higher threshold voltage can improve the reliability of the memory and reduce the bit flipping and bit error rate in the memory. However, a higher threshold voltage will also increase the power consumption of the memory. A lower threshold voltage can reduce the power consumption of the memory, but it will reduce the reliability of the memory.

[0040] In an embodiment of the present invention, the SRAM bit cell parameter set includes multiple types of process corners, including but not limited to: SS process corner, TT process corner, FF process corner, SF process corner and FS process corner.

[0041] Step S12: inputting the SRAM bit cell parameter set into simulation software for simulation to generate a performance indicator set.

[0042] In one embodiment of the present invention, the SRAM bit cell parameter set is input into simulation software for simulation to generate a performance indicator set, including: arranging and combining multiple types of parameters contained in the SRAM bit cell parameter set, and inputting each combination into the simulation software for simulation to generate the performance indicator set composed of performance indicators of multiple combinations.

[0043] Furthermore, the performance indicators in the performance indicator set include: one or more of: read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, and write power consumption.

[0044] like Figure 2 It is shown that in one embodiment of the present invention, the collected process angle parameters, threshold voltage parameters, and transistor size parameters are arranged and combined to generate multiple groups of parameter combinations and input them into simulation software for simulation to obtain a performance value indicator set.

[0045] Step S13: Based on the machine learning algorithm, a parameter prediction model is constructed through the performance indicator set and the SRAM bit cell parameter set.

[0046] In one embodiment of the present invention, based on a machine learning algorithm, a parameter prediction model is constructed using the performance indicator set and the SRAM bit cell parameter set, including: dividing the performance indicator set and the SRAM bit cell parameter set into a training set and a test set; inputting the training set into the parameter prediction model for model training; and inputting the test set into the trained prediction model to evaluate the performance of the prediction model.

[0047] Furthermore, the training set is input into the parameter prediction model for model training, including: inputting the performance indicator set in the training set into the parameter prediction model to generate a predicted SRAM bit unit parameter set; constructing a loss function based on the predicted SRAM bit unit parameter set and the SRAM bit unit parameter set corresponding to the performance indicator set in the training set; and training and optimizing the parameter prediction model based on the loss function. The machine learning algorithm includes but is not limited to: K-nearest neighbor algorithm, decision tree algorithm, regression algorithm, support vector machine algorithm, neural network, etc.

[0048] like Figure 3 As shown, an embodiment of the present invention is shown. After the training data is collected, the data is divided into a training set and a test set, and a model is constructed. According to the training process, a model with good clustering effect and free weight adjustment is selected. After multiple iterations of training using the training set, the values ​​of the coefficients in the model are determined. After obtaining the trained model, the test data is input into the prediction model, and the prediction size parameters are input. The predicted size parameters are compared with the actual size parameters to obtain the accuracy of the prediction model.

[0049] Exemplarily, when the K-means clustering algorithm is used, the K sample data closest to the predicted samples in the K distance band are first obtained from the performance indicator set in the training set, and statistics are performed based on the SRAM bit cell parameters corresponding to the K sample data obtained, and the SRAM bit cell parameters with the largest number of corresponding SRAM bit cell parameter types are taken as the prediction results of the currently predicted performance indicator sample.

[0050] Step S14: inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to output an optimized parameter set of the SRAM bit cell to be designed.

[0051] In one embodiment of the present invention, the expected performance parameters of the designed SRAM are obtained according to user needs, wherein the expected performance parameters include but are not limited to: one or more of read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, and write power consumption. The expected performance parameters are input into the parameter prediction model to output an optimized parameter set of the SRAM bit unit to be designed. The obtained optimized parameter set is manually selected to retain the optimized parameter set that can meet the layout design specifications.

[0052] like Figure 4 As shown, a schematic diagram of the structure of an SRAM bit cell optimization design device based on machine learning in an embodiment of the present invention is shown. In this embodiment, the SRAM bit cell optimization design device 400 based on machine learning includes:

[0053] Data acquisition module 401: used for acquiring the SRAM bit cell parameter set of the process node; inputting the SRAM bit cell parameter set into the simulation software for simulation to generate a performance indicator set.

[0054] Model building module 402: used to build a parameter prediction model based on the performance indicator set and the SRAM bit cell parameter set based on a machine learning algorithm.

[0055] Automatic design module 403: used for inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to generate an optimized parameter set of the SRAM bit cell to be designed.

[0056] In one embodiment of the present invention, based on a machine learning algorithm, a parameter prediction model is constructed using the performance indicator set and the SRAM bit cell parameter set, including: dividing the performance indicator set and the SRAM bit cell parameter set into a training set and a test set; inputting the training set into the parameter prediction model for model training; and inputting the test set into the trained prediction model to evaluate the performance of the prediction model.

[0057] In one embodiment of the present invention, the SRAM bit cell parameter set is input into simulation software for simulation to generate a performance indicator set, including: arranging and combining multiple types of parameters contained in the SRAM bit cell parameter set, and inputting each combination into the simulation software for simulation to generate the performance indicator set composed of performance indicators of multiple combinations.

[0058] In an embodiment of the present invention, the parameter types included in the SRAM bit cell parameter set include: one or more of process angle parameters, threshold voltage parameters, and transistor size parameters.

[0059] In one embodiment of the present invention, the performance indicators in the performance indicator set include: one or more of read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, and write power consumption.

[0060] It should be noted that: the SRAM bit cell optimization design device based on machine learning provided in the above embodiment only uses the division of the above program modules as an example when performing the optimization design of the SRAM bit cell based on machine learning. In actual applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program modules to complete all or part of the processing described above. In addition, the SRAM bit cell optimization design device based on machine learning provided in the above embodiment and the SRAM bit cell optimization design method embodiment based on machine learning belong to the same concept. The specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0061] The method for optimizing the design of the SRAM bit unit based on machine learning provided in the embodiment of the present invention can be implemented on the terminal side or the server side. As for the hardware structure of the terminal for optimizing the design of the SRAM bit unit based on machine learning, please refer to Figure 5 , is an optional hardware structure diagram of a terminal 500 for optimizing the design of an SRAM bit cell based on machine learning provided in an embodiment of the present invention. The terminal 500 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The terminal 500 for optimizing the design of an SRAM bit cell based on machine learning includes: at least one processor 501, a memory 502, at least one network interface 504 and a user interface 506. The various components in the device are coupled together through a bus system 505. It can be understood that the bus system 505 is used to realize connection and communication between these components. In addition to the data bus, the bus system 505 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 5 In the specification, various buses are labeled as bus systems.

[0062] The user interface 506 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0063] It is understood that the memory 502 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0064] The memory 502 in the embodiment of the present invention is used to store various categories of data to support the operation of the SRAM bit cell optimization design terminal 500 based on machine learning. Examples of these data include: any executable program used to operate on the SRAM bit cell optimization design terminal 500 based on machine learning, such as an operating system 5021 and an application 5022; the operating system 5021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 5022 may include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The optimization design method of the SRAM bit cell based on machine learning provided in the embodiment of the present invention may be included in the application 5022.

[0065] The method disclosed in the above embodiment of the present invention can be applied to the processor 501, or implemented by the processor 501. The processor 501 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 501 or the instruction in the form of software. The above processor 501 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 501 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 501 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0066] In an exemplary embodiment, the machine learning-based SRAM bit cell optimization design terminal 500 can be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), and complex programmable logic devices (CPLDs) to execute the aforementioned machine learning-based SRAM bit cell optimization design method.

[0067] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0068] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0069] In summary, the present application provides an optimization design method, device, terminal and medium for SRAM bit cells based on machine learning. The present invention provides a new size design method for SRAM bit cells, which reduces the possibility of errors in the manual parameter adjustment process through an automated process, and improves the reliability and consistency of the design, providing an efficient and accurate design tool for SRAM bit cell design, thereby greatly reducing the time cost, labor cost and economic cost of the design, accelerating the development process of SRAM bit cells, and improving the flexibility of SRAM bit cell design. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A method for optimizing the design of a SRAM bit cell based on machine learning, characterized in that: include: Collect the SRAM bit cell parameter set of the process node; The process of inputting the SRAM bit cell parameter set into the simulation software for simulation to generate the performance indicator set includes: arranging and combining the various types of parameters included in the SRAM bit cell parameter set, and inputting each combination into the simulation software for simulation to generate the performance indicator set consisting of the performance indicators of the multiple combinations; the SRAM bit cell parameter set includes at least one of the following parameters: process angle parameter, threshold voltage parameter, transistor size parameter; the threshold voltage parameter is obtained by collecting historical data of the SRAM bit cell of a specific process node; Based on the machine learning algorithm, a parameter prediction model is constructed by the performance indicator set and the SRAM bit cell parameter set, and the process includes: dividing the performance indicator set and the SRAM bit cell parameter set into a training set and a test set; inputting the training set into the parameter prediction model for model training, including: dividing the performance indicator set and the SRAM bit cell parameter set into a training set and a test set; inputting the performance indicator set in the training set into the parameter prediction model to generate a predicted SRAM bit cell parameter set; constructing a loss function based on the predicted SRAM bit cell parameter set and the SRAM bit cell parameter set corresponding to the performance indicator set in the training set; training and optimizing the parameter prediction model based on the loss function; inputting the test set into the trained prediction model to evaluate the performance of the prediction model; when using the K-means clustering algorithm, obtaining K sample data with the closest distance to the prediction sample from the performance indicator set in the training set, performing statistics based on the SRAM bit cell parameters corresponding to the K sample data obtained, and taking the SRAM bit cell parameter with the largest number of corresponding SRAM bit cell parameter types as the prediction result of the currently predicted performance indicator sample; The expected performance set of the SRAM bit cell to be designed is input into the parameter prediction model to output an optimized parameter set of the SRAM bit cell to be designed.

2. The method for optimizing the design of a SRAM bit cell based on machine learning according to claim 1, characterized in that: The machine learning algorithms include: K-nearest neighbor algorithm, decision tree algorithm, regression algorithm, support vector machine algorithm and neural network.

3. The method for optimizing the design of a SRAM bit cell based on machine learning according to claim 1, characterized in that: The performance indicators in the performance indicator set include: one or more of read static noise capacity, read speed, read power consumption, write static noise capacity, write speed, and write power consumption.

4. A device for optimizing the design of SRAM bit cells based on machine learning, characterized in that: include: Data acquisition module: used to collect SRAM bit cell parameter sets of process nodes; The process of inputting the SRAM bit cell parameter set into the simulation software for simulation to generate the performance indicator set includes: arranging and combining the various types of parameters included in the SRAM bit cell parameter set, and inputting each combination into the simulation software for simulation to generate the performance indicator set consisting of the performance indicators of the multiple combinations; the SRAM bit cell parameter set includes at least one of the following parameters: process angle parameter, threshold voltage parameter, transistor size parameter; the threshold voltage parameter is obtained by collecting historical data of the SRAM bit cell of a specific process node; Model building module: used for building a parameter prediction model based on the performance indicator set and the SRAM bit unit parameter set based on a machine learning algorithm, wherein the process includes: dividing the performance indicator set and the SRAM bit unit parameter set into a training set and a test set; inputting the training set into the parameter prediction model for model training, including: Input the performance indicator set in the training set into the parameter prediction model to generate a predicted SRAM bit cell parameter set; construct a loss function based on the predicted SRAM bit cell parameter set and the SRAM bit cell parameter set corresponding to the performance indicator set in the training set; train and optimize the parameter prediction model based on the loss function; input the test set into the trained prediction model to evaluate the performance of the prediction model; input the test set into the trained prediction model to evaluate the performance of the prediction model; when using the K-means clustering algorithm, obtain K sample data closest to the predicted sample from the performance indicator set in the training set, perform statistics based on the SRAM bit cell parameters corresponding to the K sample data obtained, and use the SRAM bit cell parameter with the largest number of corresponding SRAM bit cell parameter types as the prediction result of the currently predicted performance indicator sample; Automatic design module: used for inputting the expected performance set of the SRAM bit cell to be designed into the parameter prediction model to generate an optimized parameter set of the SRAM bit cell to be designed.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for optimizing the design of an SRAM bit cell based on machine learning as described in any one of claims 1 to 3 is implemented.

6. An electronic terminal, characterized in that: include: Processor and memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory so that the terminal executes the SRAM bit cell optimization design method based on machine learning as described in any one of claims 1 to 3.

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