High electron mobility gallium oxide field effect transistor preparation method and transistor

Abstract

The present application relates to a method for preparing a high electron mobility gallium oxide field effect transistor and a transistor, the method comprising the following steps: using Fe-dope Ga2O3 as a substrate, epitaxially growing a buffer layer, a channel layer and a barrier layer on the substrate from bottom to top, the barrier layer being an n-type doped AlGaO barrier layer and an unintentionally doped barrier layer, and the channel layer being an unintentionally doped high electron mobility semiconductor channel layer; depositing a regrowth mask layer on the barrier layer; etching the regrowth region; regrowing the source and drain regions in the regrowth region and removing the mask; making source and drain ohmic electrodes in the source and drain regions; isolating the active region and the passive region; depositing a gate metal electrode to obtain an AlGaO / high electron mobility semiconductor / Ga2O3 field effect transistor. The present application obtains a field effect transistor device with high mobility, high withstand voltage and low leakage by adding a high electron mobility semiconductor material to a Ga2O3 field effect transistor.

Description

Technical Field

[0001] The present application relates to the field of radio frequency technology, and in particular to a method for preparing a high electron mobility gallium oxide field effect transistor and a transistor. Background Art

[0002] Gallium oxide (Ga2O3) material is an emerging ultra-wide bandgap semiconductor material. The most common crystal structures include α, β, γ, δ, ε and transitional κ phases. The energy band gap reaches 4.8-5.2eV, and the breakdown electric field is as high as 8MV / cm, which is 2.5 times that of GaN and more than 3 times that of SiC. Due to the advantages of high voltage resistance and low power consumption, Ga2O3 material has broad application value in the preparation of high-temperature, high-frequency and high-power power electronic devices in the future.

[0003] However, the electron mobility of Ga2O3 materials is low, with a theoretical limit of only 300 cm 2 / V·s, and due to epitaxy and process reasons, the maximum electron mobility of Ga2O3 field-effect transistors reported so far at room temperature is only 180cm 2 / V·s, compared with field-effect transistors made of other materials, its low electron mobility limits its application in high-power and high-frequency applications.

[0004] Among other semiconductors, many materials have electron mobility significantly better than Ga2O3. For example, GaN has a higher electron mobility of -1200cm 2 / V·s, the 2DEG electron mobility of the high electron mobility field effect transistor composed of AlGaN / GaN heterojunction can reach up to 2200cm 2 / V·s, and the lattice mismatch between GaN and Ga2O3 is small, which can achieve quasi-homogeneous epitaxy. In addition, the variable component InAlGaN, AlGaN and other materials composed of it can also flexibly participate in the band adjustment project, bringing more possibilities to the design of Ga2O3 field effect transistors.

[0005] Prior art solution 1 is a Ga2O3 metal oxide field effect transistor, which forms a low-resistance source-drain contact by contacting heavily n-type doped Ga2O3 with metal, etches part of the Ga2O3 channel in the area under the gate to increase the gate control capability, and then uses Al2O3 dielectric to isolate the gate metal from the channel, reducing the reverse gate leakage of the device and improving the switching ratio of the device.

[0006] However, the electron mobility of the transistor device prepared by the prior art 1 is low. Due to the inherent characteristics of the Ga2O3 material, the mobility of such field effect transistors is currently low, and most of the devices reported are below 100 cm 2 / V·s or so.

[0007] The prior art solution 2 forms a two-dimensional electron gas through an AlGaO / Ga2O3 heterojunction and combines it with a delta doping method of an AlGaO barrier layer to increase the electron mobility of the field effect transistor.

[0008] However, the mobility of the transistor device prepared by the prior art solution 2 is greatly improved compared with the gallium oxide MOSFET, but the maximum is only 180cm 2 / V·s, still very low. Summary of the invention

[0009] Based on the above description, the present application provides a high electron mobility to solve the technical problem of low electron mobility of field effect transistors.

[0010] The technical solution of this application to solve the above technical problems is as follows:

[0011] A method for preparing a high electron mobility gallium oxide field effect transistor comprises the following steps:

[0012] Step S1, using a gallium oxide high-resistance homogeneous substrate, specifically a Fe-dope Ga2O3 substrate, epitaxially growing a buffer layer, a channel layer and a barrier layer on the substrate from bottom to top, wherein the barrier layer is an n-type doped AlGaO barrier layer and an unintentionally doped AlGaO barrier layer, and the channel layer is an unintentionally doped high electron mobility semiconductor channel layer, wherein the specific composition of the AlGaO is (Al x Ga 1-x )2O3, 0<x≤0.3;

[0013] Step S2, depositing a regrowth mask layer on the channel layer;

[0014] Step S3, etching the regrown area;

[0015] Step S4, regrow the source and drain regions in the regrowth region, and remove the mask;

[0016] Step S5, making source and drain ohmic electrodes in the source and drain regions;

[0017] Step S6, isolating the active area and the passive area;

[0018] Step S7, depositing a gate metal electrode to obtain an AlGaO / high electron mobility semiconductor / Ga2O3 field effect transistor.

[0019] Based on the above technical solution, the present application can also be improved as follows.

[0020] In some embodiments, the thickness of the substrate is 375 μm-675 μm.

[0021] In some embodiments, a buffer layer, a channel layer, and a barrier layer are epitaxially grown sequentially from bottom to top on the substrate by MOCVD (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), or HVPE (hydride vapor phase epitaxy).

[0022] In some embodiments, the buffer layer is an unintentionally doped Ga2O3 buffer layer, and the high electron mobility semiconductor is GaN, GaAs, AlN, InP, diamond, Si, graphene, etc. Preferably, the buffer layer has a thickness range of 300nm-600nm, the channel layer has a thickness range of 20nm-300nm, and the barrier layer has a thickness range of 12nm-40nm, including an n-type doped barrier layer of 2nm~10nm and an unintentionally doped barrier layer of 10nm~30nm. More preferably, the buffer layer has a thickness range of 400nm-500nm, the channel layer has a thickness range of 20nm-300nm, and the barrier layer has a thickness range of 12nm-25nm, including an n-type doped barrier layer of 2nm~5nm and an unintentionally doped barrier layer of 10nm~20nm.

[0023] In some embodiments , the thickness of the substrate ranges from 375 μm to 675 μm.

[0024] In some embodiments, in order to ensure that each channel is in good contact with the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. Specifically, a mask layer is first grown on a wafer, and then the source and drain regions are etched out by photolithography, and then the regrowth mask is etched, and the pattern of the photoresist is transferred to the regrowth mask, and the photoresist is removed after the etching is completed. Preferably, the mask layer includes but is not limited to various SiO2, SiNx, Al2O3 media or composite media formed by a combination of multiple thereof.

[0025] Preferably, in the step S3, etching the regrown region, a Cl-based gas is used to etch the barrier layer and the channel layer from top to bottom in an ICP, RIE or other equipment.

[0026] In some embodiments, in step S4, the source and drain regions are regrown in the regrown region, and the mask is removed, and the etched region is regrown by MOCVD or MBE to grow a heavily doped n-type Ga2O3 or GaN regrown layer, as shown in FIG6(a), and then the regrown mask layer is removed by a wet method, as shown in FIG6(b);

[0027] In some embodiments, after the secondary epitaxy is completed, source-drain ohmic electrodes are made in the source-drain region. Specifically, photolithography is performed to define the source-drain electrode pattern, followed by metal deposition, and finally metal stripping is performed to make the source-drain electrode; preferably, in this step, the metal system of the deposited metal is exemplified by the commonly used Ti / Pt / Au; preferably, in this step, if the regrowth doping concentration is not high enough to directly form a good ohmic contact, annealing can be used to improve it to form an ohmic contact, the annealing temperature ranges from 400°C to 600°C, the annealing atmosphere is nitrogen, and the annealing time is 30s-1min; the structural cross-sectional view of the electrode preparation is shown in FIG. Figure 7 In the embodiment of the present application, the ohmic contact of the source and drain regions is formed by n-type ion implantation, such as Si, Sn, Se plasma, followed by high temperature activation, and finally deposition of Ti / Pt / Au metal, followed by annealing at 400°C-600°C, 30s-60s, to form an ohmic contact.

[0028] In some embodiments, in the step S6, isolating the active region from the passive region, the active region from the passive region is isolated by ion implantation. Preferably, the ions are B, N, Fe or Ar.

[0029] In some embodiments, in the step S6, isolating the active area from the passive area, the active area and the passive area are isolated by an etching method.

[0030] Use photoresist, dielectric, metal, etc. as etching masks to protect the active area, and use Cl-based gas to etch the unprotected area in etching equipment such as ICP and RIE. After etching, wet remove the etching mask to isolate the active area and the passive area.

[0031] In some embodiments, in the step S7, in which the gate metal electrode is deposited, the metal is Ni / Au, and after the gate electrode is deposited, it is peeled off to finally complete the manufacture of the field effect transistor. Figure 7 As shown; preferably, the first metal layer Ni can also be replaced by other high work function metals; more preferably, the high work function metals include but are not limited to Pt, W, Ir, WN, TiW, Pd, etc.

[0032] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0033] The present application provides a method for preparing a high electron mobility gallium oxide field effect transistor, which effectively improves the electron mobility of the Ga2O3 transistor by adding a high electron mobility semiconductor material into the Ga2O3 field effect transistor, thereby obtaining a field effect transistor device with high mobility, high withstand voltage and low leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1A schematic cross-sectional view of a Ga2O3 metal oxide field effect transistor in the prior art;

[0035] Figure 2 It is a schematic cross-sectional view of an AlGaO / Ga2O3 heterojunction field effect transistor in the prior art;

[0036] Figure 3 A schematic diagram of the epitaxial structure of a gallium oxide field effect transistor provided in an embodiment of the present application;

[0037] Figure 4 A schematic diagram of the source and drain region regrowth mask and patterning provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the source and drain etching regrowth region provided in an embodiment of the present application;

[0039] FIG. 6 (a)-FIG. 6 (b) are schematic diagrams of source / drain region regrowth and hard mask removal according to an embodiment of the present application;

[0040] Figure 7 Schematic diagram of lithography, deposition and stripping of ohmic electrodes in the source and drain regions provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of ion implantation isolation provided in an embodiment of the present application;

[0042] Fig. 9 Schematic diagram of the gate metal electrode manufacturing provided in an embodiment of the present application.

[0043] In the figure: 1. AlGO barrier layer; 2. Si-doped AlGaO barrier layer; 3. Unintentionally doped GaN channel layer; 4. Unintentionally doped Ga2O3 buffer layer; 5. Ga2O3 substrate layer; 6. Regrowth mask layer; 7. Heavily doped n-type Ga2O3 or GaN regrowth layer; 8. Source; 9. Drain; 10. Gate electrode. DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] Embodiment 1: The high electron mobility semiconductor is GaN.

[0047] Step 1: Prepare epitaxial substrate, such as Figure 3 As shown:

[0048] An Fe-dope Ga2O3 substrate layer 5 is selected as an example, with a thickness of 375 μm; an unintentionally doped Ga2O3 buffer layer 4 is subsequently grown by MOCVD with a thickness of 300-600 nm; an unintentionally doped GaN channel layer 3 is 20 nm thick; a delta-doped AlGaO barrier layer, specifically a Si-doped AlGaO barrier layer 2, with a thickness of 2 nm, where Si-doping is used as an example, and an unintentionally doped AlGaO barrier layer 1, with a thickness of 10 nm, wherein the specific composition of AlGaO is (Al x Ga 1-x )2O3,0<x≤0.3.

[0049] Step 2: deposit a regrowth mask layer 6 on the barrier layer, such as Figure 4 As shown:

[0050] In order to ensure good contact between each channel and the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. First, a 300nm SiO2 mask layer is grown on the wafer, and then the source and drain areas are exposed by photolithography. The regrowth mask is then etched, and the pattern of the photoresist is transferred to the regrowth mask. After the etching is completed, the photoresist is removed.

[0051] Step 3: Etch the regrown area, such as Figure 5 As shown:

[0052] The regrowth mask is used as an etching mask for AlGaO and GaN, and the regrowth area is etched in an ICP device using Cl-based gas.

[0053] Step 4: regrow the source and drain regions, as shown in Figure 6:

[0054] Then, the etched area is regrown by MOCVD to grow a heavily doped n-type Ga2O3 or GaN regrown layer 7, and then the regrown mask is removed by a wet method.

[0055] Step 5: Make source and drain ohmic electrodes in the source and drain regions, such as Figure 7 As shown:

[0056] After completing the secondary epitaxy, the source and drain electrode patterns are defined by photolithography, followed by metal deposition. The metal system takes the commonly used Ti / Pt / Au as an example. Finally, the metal is stripped to complete the production of the source 8 and the drain 9.

[0057] Step 6: Ion implantation isolation, such as Figure 8 As shown:

[0058] After completing the ohmic contact, the active area and the passive area are isolated by ion implantation, and the implanted ions are B.

[0059] Step 7: gate electrode fabrication, such as Fig. 9 As shown:

[0060] After the ion implantation isolation is completed, a gate metal electrode is deposited, the metal is Ni / Au, and the first layer of metal is Ni. After the gate electrode 10 is deposited, it is peeled off, and finally the manufacture of the field effect transistor device is completed.

[0061] Embodiment 2: The high electron mobility semiconductor is GaAs.

[0062] Step 1: Prepare epitaxial substrate

[0063] An Fe-dope Ga2O3 substrate is selected as an example, with a thickness of 375 μm; an unintentionally doped Ga2O3 buffer layer is then grown by MOCVD, with a thickness of 300-600 nm; an unintentionally doped high electron mobility semiconductor channel layer, with a thickness of 20 nm, here GaAs; a delta-doped AlGaO barrier layer, with a thickness of 2 nm, here Si-doped is used as an example, and an unintentionally doped AlGaO barrier layer, with a thickness of 10 nm, wherein the specific composition of AlGaO is (Al x Ga 1-x )2O3,0<x≤0.3.

[0064] Step 2: Deposit a regrowth mask layer on the barrier layer

[0065] To ensure good contact between each channel and the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. First, a 300nm SiO2 mask layer is grown on the wafer, and then the source and drain areas are exposed by photolithography. The regrowth mask is then etched and the pattern of the photoresist is transferred to the regrowth mask. The photoresist is removed after the etching is completed.

[0066] Step 3: Etch the regrowth area

[0067] The regrowth mask is used as an etching mask for AlGaO and GaN, and the regrowth area is etched in an ICP device using Cl-based gas.

[0068] Step 4: Regrowth of source and drain regions

[0069] The etched area is then regrown using MOCVD to grow a heavily doped n-type Ga2O3 or GaN regrown layer, and the regrown mask is then removed using a wet method.

[0070] Step 5: Make source and drain ohmic electrodes in the source and drain areas

[0071] After completing the secondary epitaxy, the source and drain electrode patterns are defined by photolithography, followed by metal deposition. The metal system is commonly used Ti / Pt / Au as an example. Finally, the metal is stripped to complete the production of the source and drain electrodes. If the regrowth doping concentration is not high enough to directly form a good ohmic contact, it can also be improved by annealing. The annealing temperature can be 400℃-600℃, the annealing atmosphere is nitrogen, and the annealing time is 30s-1min. Structural cross-section diagram of electrode preparation.

[0072] Step 6: Ion implantation isolation

[0073] After completing the ohmic contact, the active area and the passive area are isolated by ion implantation, and the implanted ions are B.

[0074] Step 7: Gate electrode fabrication

[0075] After ion implantation isolation is completed, a gate metal electrode is deposited, the metal is Ni / Au, and the first layer of metal is Ni. After the gate electrode is deposited, it is stripped and the field effect transistor device is finally manufactured.

[0076] Embodiment three: The high electron mobility semiconductor is InP.

[0077] Step 1: Prepare epitaxial substrate

[0078] An Fe-dope Ga2O3 substrate is selected as an example, with a thickness of 375 μm; an unintentionally doped Ga2O3 buffer layer is subsequently grown by MOCVD with a thickness of 300-600 nm; an unintentionally doped high electron mobility semiconductor channel layer with a thickness of 20 nm, in which GaAs is used; a delta-doped AlGaO barrier layer with a thickness of 2 nm, in which Si is used as an example, and an unintentionally doped AlGaO barrier layer with a thickness of 10 nm, wherein the specific composition of AlGaO is (Al x Ga 1-x )2O3,0<x≤0.3.

[0079] Step 2: Deposit a regrowth mask layer on the barrier layer

[0080] In order to ensure good contact between each channel and the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. First, a 300nm SiO2 mask layer is grown on the wafer, and then the source and drain areas are exposed by photolithography. Then the regrowth mask is etched, and the pattern of the photoresist is transferred to the regrowth mask. After the etching is completed, the photoresist is removed.

[0081] Step 3: Etch the regrowth area

[0082] The regrowth mask is used as an etching mask for AlGaO and GaN, and the regrowth area is etched in an ICP device using Cl-based gas.

[0083] Step 4: Regrowth of source and drain regions

[0084] The etched area is then regrown using MOCVD to grow a heavily doped n-type Ga2O3 or GaN regrown layer, and the regrown mask is then removed using a wet method.

[0085] Step 5: Make source and drain ohmic electrodes in the source and drain areas

[0086] After completing the secondary epitaxy, the source and drain electrode patterns are defined by photolithography, followed by metal deposition. The metal system is commonly used Ti / Pt / Au as an example. Finally, the metal is stripped to complete the production of the source and drain electrodes. If the regrowth doping concentration is not high enough to directly form a good ohmic contact, it can also be improved by annealing. The annealing temperature can be 400℃-600℃, the annealing atmosphere is nitrogen, and the annealing time is 30s-1min. Structural cross-section diagram of electrode preparation.

[0087] Step 6: Ion implantation isolation

[0088] After completing the ohmic contact, the active area and the passive area are isolated by ion implantation, and the implanted ions are B.

[0089] Step 7: Gate electrode fabrication

[0090] After ion implantation isolation is completed, a gate metal electrode is deposited, the metal is Ni / Au, and the first layer of metal is Ni. After the gate electrode is deposited, it is stripped and the field effect transistor device is finally manufactured.

[0091] Embodiment 4 Compared with the first embodiment, the difference of this embodiment is that the active area and the passive area are isolated by an etching method.

[0092] Step 1: Prepare epitaxial substrate

[0093] An Fe-dope Ga2O3 substrate is selected as an example, with a thickness of 375 μm; an unintentionally doped Ga2O3 buffer layer is subsequently grown by MOCVD with a thickness of 300-600 nm; an unintentionally doped high electron mobility semiconductor channel layer with a thickness of 20 nm, in which GaN is used; a delta-doped AlGaO barrier layer with a thickness of 2 nm, in which Si is used as an example, and it can also be Sn, Ge, etc., and an unintentionally doped AlGaO barrier layer with a thickness of 10 nm, wherein the specific composition of AlGaO is (Al x Ga 1-x )2O3,0<x≤0.3.

[0094] Step 2: Deposit a regrowth mask layer on the barrier layer

[0095] In order to ensure good contact between each channel and the source and drain electrodes, the source and drain electrodes are made by selective etching and regrowth. First, a mask layer is grown on the wafer, and then the source and drain areas are exposed by photolithography. Then the regrowth mask is etched, and the pattern of the photoresist is transferred to the regrowth mask. After the etching is completed, the photoresist is removed.

[0096] Step 3: Etch the regrowth area

[0097] The regrowth mask is used as an etching mask for AlGaO and GaN, and the regrowth area is etched in an ICP device using Cl-based gas.

[0098] Step 4: Regrowth of source and drain regions

[0099] The etched area is then regrown using MOCVD to grow a heavily doped n-type Ga2O3 or GaN regrown layer, and the regrown mask is then removed using a wet method.

[0100] Step 5: Make source and drain ohmic electrodes in the source and drain areas

[0101] After completing the secondary epitaxy, the source and drain electrode patterns are defined by photolithography, and then metal is deposited. For example, the metal system is the commonly used Ti. Finally, metal stripping is performed to complete the production of the source and drain electrodes.

[0102] Step 6: Use an etching method to complete the isolation of the active area and the passive area;

[0103] Step 7: Making the gate electrode.

[0104] After ion implantation isolation is completed, a gate metal electrode is deposited, the metal is Ni / Au, and the first layer of metal is Ni. After the gate electrode is deposited, it is stripped and the field effect transistor device is finally manufactured.

[0105] Comparative Example 1

[0106] A low-resistance source-drain contact is formed by contacting heavily n-type doped Ga2O3 with a metal, and a portion of the Ga2O3 channel is etched in the area under the gate to obtain a Ga2O3 metal oxide field effect transistor.

[0107] Comparative Example 2

[0108] A two-dimensional electron gas is formed through an AlGaO / Ga2O3 heterojunction, and combined with a delta doping method of an AlGaO barrier layer, an AlGaO / Ga2O3 heterojunction field effect transistor is manufactured.

[0109] Table 1 Comparison of electron mobility of field effect transistor devices prepared in various embodiments and comparative examples

[0110]

[0111] The method for preparing a high electron mobility gallium oxide field effect transistor provided in the present application is based on the Ga2O3 material system, and proposes an AlGaO / high electron mobility semiconductor / Ga2O3 field effect transistor scheme. A semiconductor with high electron mobility is used as the channel layer of the Ga2O3 field effect transistor. The prepared Ga2O3 field effect transistor has the following technical effects:

[0112] (1) High mobility: Using semiconductors with high electron mobility as the channel layer of the Ga2O3 field-effect transistor solves the problem of low electron mobility of Ga2O3 materials and improves the output power and frequency characteristics of the device.

[0113] (2) High withstand voltage: Ga2O3 has a bandgap of up to 5eV and a critical breakdown field strength of up to 8MV / cm. Using it as a barrier layer can effectively improve the withstand voltage characteristics of the device;

[0114] (3) Low leakage: Taking the 3.4 eV bandgap width of GaN as an example, since its bandgap width is smaller than that of Ga2O3, it can further increase the band gap of the AlGaO / Ga2O3 heterojunction, increase the confinement of 2DEG, reduce the leakage of the field effect transistor, improve the switching ratio of the device, reduce the operating loss of the device, and improve the power efficiency of the device.

[0115] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for preparing a high electron mobility gallium oxide field effect transistor, characterized in that: The steps include: Taking Fe-doped Ga2O3 as a substrate, epitaxially growing a buffer layer, a channel layer and a barrier layer on the substrate from bottom to top, wherein the channel layer is an unintentionally doped high electron mobility semiconductor channel layer, the high electron mobility semiconductor is GaN, GaAs, AlN, InP, diamond, Si or graphene, and the barrier layer is AlGaO; depositing a regrowth mask layer on the barrier layer; etching the regrown area; regrow the source and drain regions in the regrowth region and remove the mask; Making source and drain ohmic electrodes in the source and drain regions; Isolate active and passive areas; A gate metal electrode is deposited to produce an AlGaO / high electron mobility semiconductor / Ga2O3 field effect transistor.

2. The method for preparing a high electron mobility gallium oxide field effect transistor according to claim 1, characterized in that: The thickness of the substrate ranges from 375 μm to 675 μm, the thickness of the buffer layer ranges from 300 nm to 600 nm, the thickness of the channel layer ranges from 20 nm to 300 nm, and the thickness of the barrier layer ranges from 12 nm to 40 nm, including 2 nm to 10 nm of n-type doped barrier layer and 10 nm to 30 nm of unintentionally doped barrier layer.

3. The method for preparing a high electron mobility gallium oxide field effect transistor according to claim 1, characterized in that: The mask layer includes SiO2, SiNx, Al2O3 medium or a composite medium formed by a combination of the above.

4. The method for preparing a high electron mobility gallium oxide field effect transistor according to claim 1, characterized in that: In the step of etching the regrown region, Cl-based gas is used to etch the barrier layer and the channel layer from top to bottom.

5. The method for preparing a high electron mobility gallium oxide field effect transistor according to claim 1, characterized in that: In the step of isolating the active area and the passive area, the active area and the passive area are isolated by ion implantation.

6. The method for preparing a high electron mobility gallium oxide field effect transistor according to claim 5, characterized in that: The ions are B, N, Fe or Ar.

7. The method for preparing a high electron mobility gallium oxide field effect transistor according to claim 1, characterized in that: In the step of depositing the gate metal electrode, the metal is Ni / Au.

8. A transistor, characterized in that: The high electron mobility gallium oxide field effect transistor is prepared by the preparation method according to any one of claims 1 to 7.

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