An integrated schottky structure sgt-mos device and a method of fabricating the same

Abstract

The application discloses an SGT-MOS device integrated with a Schottky structure and a preparation method thereof. The device comprises, from bottom to top, a back metal, a substrate, two epitaxial layers, a SiO2 oxide layer and a front metal. The two epitaxial layers are a first epitaxial layer and a second epitaxial layer. The device further comprises a shielding gate trench, which is divided into a shielding gate and a control gate by an HDP oxide layer. The control gate is located above the shielding gate. The second epitaxial layer is provided with a P well region of an SGT part and a P region of a PiN structure in an MPS part. A source region is arranged in the P well region. The front metal of the SGT part is arranged separately from the front metal of the MPS part. The SGT part is formed with a first contact hole, and the MPS part is formed with a second contact hole. The front metal fills the first contact hole and the second contact hole. The device has a good breakdown voltage when in a forward blocking state. The device significantly shortens a Miller platform during switching, improves switching speed and reduces switching loss.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to an SGT-MOS device with an integrated Schottky structure and its fabrication method. Background Technology

[0002] SGT MOSFETs are a new type of power semiconductor device that combines the low conduction losses of traditional deep trench MOSFETs with even lower switching losses. As a switching device, SGT MOSFETs are used in motor drive systems, inverter systems, and power management systems in fields such as new energy electric vehicles, new photovoltaic power generation, and energy-saving home appliances, serving as a core power control component.

[0003] Improving the breakdown voltage of a device in the forward cutoff state while reducing gate-drain capacitance and gate-drain charge, shortening the Miller plateau during switching, increasing switching speed, and reducing switching losses are directions that those skilled in the art are dedicated to researching. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating an SGT-MOS device with an integrated Schottky structure.

[0005] To achieve this objective, the present invention adopts the following technical solution: A method for fabricating an SGT-MOS device with an integrated Schottky structure includes the following steps: Step 1) Prepare a substrate and grow two epitaxial layers sequentially on its upper surface, namely the first epitaxial layer and the second epitaxial layer; Step 2) A SiO2 pad oxide layer is formed on the upper surface of the second epitaxial layer by thermal oxidation. Then, SiN is deposited on the upper surface of the SiO2 pad oxide layer to form a hard mask. After photolithography, development and etching of the hard mask, an etching window is made for the shielding gate trench. Then, the etching is carried out along the window down to the first epitaxial layer to form the shielding gate trench. Step 3) Fabricate oxide layer: Based on step 2), form shielding gate oxide layer on the surface of hard mask and the inner wall of shielding gate trench by thermal oxidation and deposition. Then deposit shielding gate polysilicon on the surface of hard mask and in shielding gate trench. Step 4) Etch the shielding gate polysilicon to a predetermined depth, then deposit an HDP oxide layer as an isolation between the shielding gate and the control gate, and then etch the HDP oxide layer to a predetermined depth. Step 5) Thermally oxidize the inner wall of the shielding gate trench to form a control gate CG oxide layer, then deposit the control gate on top of the HDP oxide layer, and use chemical mechanical polishing to grind the device to the surface of the second epitaxial layer. Step 6) After photolithography and development on the surface of the second epitaxial layer, P ions are implanted to simultaneously form the P well region of the SGT part and the P region of the PiN structure in the MPS part. The P well region is also doped with phosphorus element. Phosphorus element is implanted in the P well region to form the source region. Step 7) Deposit a SiO2 oxide layer on the second epitaxial layer, and etch along the SiO2 oxide layer to the P-well region through a via plate to form the first contact hole of the SGT portion. Boron is implanted into the first contact hole, and then it is rapidly annealed. The SiO2 oxide layer of the MPS portion is etched to the surface of the second epitaxial layer to form the second contact hole of the MPS portion. Step 8) Deposit the front metal on the upper surface of the device obtained in step 7), etch the front metal at the connection between the SGT device part and the MPS device part, and then deposit and thin the back metal on the back of the device.

[0006] In one specific embodiment, the substrate is doped with phosphorus at a concentration of 1×10⁻⁶. 19 cm -3 Both the first and second epitaxial layers are doped with phosphorus, and their resistivities are 0.25 Ωcm / 4 μm and 0.4 Ωcm / 3 μm, respectively.

[0007] In one specific implementation, the thickness of the shielding gate oxide layer deposited in step 3) is 0.1 μm, and the polysilicon of the shielding gate is doped with P element at a concentration of 4.5 × 10⁻⁶. 18 cm -3 .

[0008] In one specific implementation, in step 5), the thermal oxidation temperature is 1000℃, the thickness of the control gate CG oxide layer is 60-70 nm, and the control gate is doped with P element at a concentration of 1.7 × 10⁻⁶. 18 cm -3 .

[0009] In one specific implementation, in step 6), the implantation dose of boron ions is 1 × 10⁻⁶. 14 cm -3 The energy is 15 keV or the injection dose is 5 × 10⁻⁶. 13 cm -3 The energy is 40keV.

[0010] In one specific implementation, in step 6), the dose of phosphorus injected into the source region is 1×10⁻⁶. 15 cm -3 The energy is 50keV.

[0011] In one specific implementation, in step 7), the depth of the first contact hole in the P-well region is 0.32 μm, and the dose of boron ions injected into the hole is 1 × 10⁻⁶. 14 cm -3 Energy of 15 keV or dose of 5 × 10 13 cm -3 The energy is 40keV.

[0012] Another objective of this invention is to provide an integrated Schottky structure SGT-MOS device, fabricated using the aforementioned method. The SGT-MOS device comprises, from bottom to top, a back metal, a substrate, two epitaxial layers, a SiO2 oxide layer, and a front metal. The two epitaxial layers are a first epitaxial layer and a second epitaxial layer, respectively. The SGT-MOS device further includes a shielding gate trench disposed in the two epitaxial layers. The shielding gate trench is divided into a shielding gate and a control gate by an HDP oxide layer. The control gate is located above the shielding gate. The second epitaxial layer contains a P-well region of the SGT portion and a P-region of the PiN structure in the MPS portion. A source region is disposed in the P-well region. The front metal of the SGT portion and the front metal of the MPS portion are spaced apart. The SGT portion has a first contact hole, and the MPS portion has a second contact hole. The front metal fills both the first and second contact holes.

[0013] Compared with the prior art, the technical solution of the present invention has the following advantages: The present invention prepares an SGT-MOS device with an integrated Schottky structure. By adding a shielding gate with a potential and source shorted below the control gate, on the one hand, when the device is in the forward cutoff state, the shielding gate acts as a body field plate, assisting in the depletion of the drift region, optimizing the electric field distribution, and effectively improving the breakdown voltage of the device; on the other hand, the shielding gate isolates the control gate and the drift region, greatly reducing the overlap area of ​​the gate and drain, reducing the gate-drain capacitance and gate-drain charge, significantly shortening the Miller plateau during switching, improving the switching speed, and reducing switching losses. Attached Figure Description

[0014] Figure 1 This is a process flow diagram for fabricating the SGT-MOS device with integrated Schottky structure described in this invention; Wherein: 1. Substrate; 2. First epitaxial layer; 3. Second epitaxial layer; 4. SiO2 pad oxide layer; 5. Hard mask; 6. Shielding gate trench; 7. Shielding gate oxide layer; 8. Shielding gate polysilicon; 9. CG oxide layer; 10. HDP oxide layer; 11. Shielding gate; 12. Control gate; 13. P-well region; 14. P-region; 15. Source region; 16. SiO2 oxide layer; 17. First contact hole; 18. Second contact hole; 19. Front metal; 20. Back metal. Detailed Implementation

[0015] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0016] This invention provides an integrated Schottky-structured SGT-MOS device, comprising, from bottom to top, a back metal 20, a substrate 1, two epitaxial layers, a SiO2 oxide layer 16, and a front metal 19. The two epitaxial layers are a first epitaxial layer 2 and a second epitaxial layer 3. The SGT-MOS device also includes a shielding gate trench 6 disposed in the two epitaxial layers. The shielding gate trench is divided into a shielding gate 11 and a control gate 12 by an HDP oxide layer 10. The control gate 12 is located above the shielding gate 11. The second epitaxial layer 3 is provided with a P-well region 13 of the SGT portion and a P-region 14 of the PiN structure in the MPS portion. A source region 15 is disposed in the P-well region. The front metal of the SGT portion and the front metal of the MPS portion are disposed alternately. The SGT portion forms a first contact hole 17, and the MPS portion forms a second contact hole 18. The front metal 19 fills the first contact hole 17 and the second contact hole 18.

[0017] For the specific fabrication method of this SGT-MOS device, please refer to [link / reference]. Figure 1 As shown, it includes the following steps: Step 1) Prepare substrate 1, which is doped with phosphorus at a concentration of 1×10⁻⁶. 19 cm -3 Two epitaxial layers are grown sequentially on its upper surface, namely the first epitaxial layer 2 and the second epitaxial layer 3. Both the first epitaxial layer 2 and the second epitaxial layer 3 are doped with phosphorus, and their resistivities are 0.25Ωcm / 4μm and 0.4Ωcm / 3μm, respectively. The structure formed by the substrate and the two epitaxial layers is used as the common material for the SGT part and part of the MPS part. Step 2) A SiO2 pad oxide layer 4 is formed on the upper surface of the second epitaxial layer 3 by thermal oxidation. Then, SiN is deposited on the upper surface of the SiO2 pad oxide layer 4 to form a hard mask 5. After photolithography, development and etching of the hard mask, an etching window is made for the shielding gate trench. Then, the etching is carried out along the window down to the first epitaxial layer to form the shielding gate trench 6, while protecting the MPS part from being etched. Step 3) Fabrication of the oxide layer: Based on step 2), a shielding gate oxide layer 7 is formed on the surface of the hard mask and the inner wall of the shielding gate trench by thermal oxidation and deposition. Here, the thickness of the shielding gate oxide layer is 0.1 μm. Then, shielding gate polysilicon 8 is deposited on the surface of the hard mask and in the shielding gate trench. This shielding gate polysilicon is doped with P element, and the doping concentration is 4.5 × 10⁻⁶. 18 cm -3 ; Step 4) Etch the shielding gate polysilicon to a predetermined depth, and then deposit an HDP oxide layer 10 as an isolation between the shielding gate 11 and the control gate 12. Then etch the HDP oxide layer to a predetermined depth, keeping the HDP oxide layer thickness at 0.3 μm. Step 5) The inner wall of the shielding gate trench is thermally oxidized at 1000℃ to form a 65nm control gate CG oxide layer 9. Then, a control gate 12 is deposited on top of the HDP oxide layer. This control gate is doped with P element at a doping concentration of 1.7×10⁻⁶. 18 cm -3 The device was then ground to the surface of the second epitaxial layer using chemical mechanical polishing (CMP). Step 6) After trap lithography and development, P ions are implanted onto the surface of the second epitaxial layer. The implantation dose of boron ions is 1×10⁻⁶. 14 cm -3 The energy is 15 keV or the injection dose is 5 × 10⁻⁶. 13 cm -3 The energy is 40 keV to simultaneously form the P-well region 13 of the SGT portion and the P-region 14 of the PiN structure in the MPS portion. The P-well region is also doped with phosphorus. Phosphorus is implanted into the P-well region to form the source region 15. Here, the phosphorus ion implantation dose is 1 × 10⁻⁶. 15 cm -3 The energy is 50keV; Step 7) A SiO2 oxide layer 16 is deposited on the second epitaxial layer. The first contact hole 17 of the SGT portion is formed by etching along the SiO2 oxide layer through a via plate to the P-well region. The depth of the first contact hole in the P-well region is 0.32 μm. Boron is implanted into the first contact hole at a dose of 1 × 10⁻⁶. 14 cm -3 Energy of 15 keV or dose of 5 × 10 13 cm -3 The energy is 40keV, and then it is rapidly annealed; the SiO2 oxide layer of the MPS part is etched to the surface of the second epitaxial layer to form the second contact hole 18 of the MPS part; Step 8) Deposit the front metal 19 on the upper surface of the device obtained in step 7), etch the front metal at the connection between the SGT device part and the MPS device part, and then deposit and thin the back metal 20 on the back side of the device.

[0018] The SGT-MOS device of the present invention, by adding a shielding gate with a potential and source shorted below the control gate, has the following advantages: First, when the device is in the forward cutoff state, the shielding gate acts as an internal field plate, assisting in the depletion of the drift region, optimizing the electric field distribution, and effectively improving the breakdown voltage of the device. Second, the shielding gate isolates the control gate and the drift region, greatly reducing the overlap area between the gate and the drain, reducing the gate-drain capacitance and gate-drain charge, significantly shortening the Miller plateau during switching, improving the switching speed, and reducing switching losses.

[0019] The above description is only a preferred embodiment of the present invention. For those skilled in the art, there will be changes in the specific implementation and application scope based on the ideas of the present invention. The content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for fabricating an SGT-MOS device with an integrated Schottky structure, characterized in that, Includes the following steps: Step 1) Prepare a substrate and grow two epitaxial layers sequentially on its upper surface, namely the first epitaxial layer and the second epitaxial layer; Step 2) A SiO2 pad oxide layer is formed on the upper surface of the second epitaxial layer by thermal oxidation. Then, SiN is deposited on the upper surface of the SiO2 pad oxide layer to form a hard mask. After photolithography, development and etching of the hard mask, an etching window is made for the shielding gate trench. Then, the etching is carried out along the window down to the first epitaxial layer to form the shielding gate trench. Step 3) Fabricate oxide layer: Based on step 2), form shielding gate oxide layer on the surface of hard mask and the inner wall of shielding gate trench by thermal oxidation and deposition. Then deposit shielding gate polysilicon on the surface of hard mask and in shielding gate trench. Step 4) Etch the shielding gate polysilicon to a predetermined depth, then deposit an HDP oxide layer as an isolation between the shielding gate and the control gate, and then etch the HDP oxide layer to a predetermined depth. Step 5) Thermally oxidize the inner wall of the shielding gate trench to form a control gate CG oxide layer, then deposit the control gate on top of the HDP oxide layer, and use chemical mechanical polishing to grind the device to the surface of the second epitaxial layer. Step 6) After photolithography and development on the surface of the second epitaxial layer, P ions are implanted to simultaneously form the P well region of the SGT part and the P region of the PiN structure in the MPS part. The P well region is also doped with phosphorus element. Phosphorus element is implanted in the P well region to form the source region. Step 7) Deposit a SiO2 oxide layer on the second epitaxial layer, and etch along the SiO2 oxide layer to the P-well region through a via plate to form the first contact hole of the SGT portion. Boron is implanted into the first contact hole, and then it is rapidly annealed. The SiO2 oxide layer of the MPS portion is etched to the surface of the second epitaxial layer to form the second contact hole of the MPS portion. Step 8) Deposit the front metal on the upper surface of the device obtained in step 7), etch the front metal at the connection between the SGT device part and the MPS device part, and then deposit and thin the back metal on the back of the device.

2. The method for fabricating an SGT-MOS device with an integrated Schottky structure according to claim 1, characterized in that, The substrate is doped with phosphorus at a concentration of 1×10⁻⁶. 19 cm -3 Both the first and second epitaxial layers are doped with phosphorus, and their resistivities are 0.25 Ωcm / 4 μm and 0.4 Ωcm / 3 μm, respectively.

3. The method for fabricating an SGT-MOS device with an integrated Schottky structure according to claim 1, characterized in that, The thickness of the shielding gate oxide layer deposited in step 3) is 0.1 μm, and the polysilicon of the shielding gate is doped with P element at a concentration of 4.5 × 10⁻⁶. 18 cm -3 .

4. The method for fabricating an SGT-MOS device with an integrated Schottky structure according to claim 1, characterized in that, In step 5), the thermal oxidation temperature is 1000℃, and the thickness of the control gate CG oxide layer is 60-70 nm; the control gate is doped with P element at a concentration of 1.7 × 10⁻⁶. 18 cm -3 .

5. The method for fabricating an SGT-MOS device with an integrated Schottky structure according to claim 1, characterized in that, In step 6), the boron ion implantation dose is 1×10⁻⁶. 14 cm -3 The energy is 15 keV or the injection dose is 5 × 10⁻⁶. 13 cm -3 The energy is 40keV.

6. The method for fabricating an SGT-MOS device with an integrated Schottky structure according to claim 1, characterized in that, In step 6), the dose of phosphorus injected into the source region is 1×10⁻⁶. 15 cm -3 The energy is 50keV.

7. The method for fabricating an SGT-MOS device with an integrated Schottky structure according to claim 1, characterized in that, In step 7), the depth of the first contact hole in the P-well region is 0.32 μm, and the dose of boron ions injected into the hole is 1 × 10⁻⁶. 14 cm -3 Energy of 15 keV or dose of 5 × 10 13 cm -3 The energy is 40keV.

8. An SGT-MOS device with an integrated Schottky structure, characterized in that, The SGT-MOS device, fabricated using the method described in claim 1, comprises, from bottom to top, a back metal, a substrate, two epitaxial layers, a SiO2 oxide layer, and a front metal. The two epitaxial layers are a first epitaxial layer and a second epitaxial layer, respectively. The SGT-MOS device further comprises a shielding gate trench disposed in the two epitaxial layers. The shielding gate trench is divided into a shielding gate and a control gate by an HDP oxide layer. The control gate is located above the shielding gate. The second epitaxial layer contains a P-well region of the SGT portion and a P-region of the PiN structure in the MPS portion. A source region is disposed in the P-well region. The front metal of the SGT portion and the front metal of the MPS portion are spaced apart. The SGT portion forms a first contact hole, and the MPS portion forms a second contact hole. The front metal fills the first contact hole and the second contact hole.

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