A power-on reset circuit and integrated circuit system

Abstract

The present invention discloses a power-on reset circuit and an integrated circuit system, and relates to the technical field of reset circuits. The reset circuit comprises: a first NMOS tube, the drain of the first NMOS tube is connected to a system power supply, the gate of the first NMOS tube is grounded, and the source of the first NMOS tube is used to output a reference voltage; a current mirror circuit and an inverter, the current mirror circuit is used to copy the current value of the reference voltage and output it to the input end of the inverter; a second NMOS tube and a voltage divider circuit, the voltage divider circuit is used to divide the system power supply voltage and output it to the gate of the second NMOS tube; the source of the second NMOS tube is grounded, and the drain of the second NMOS tube is connected to the input end of the inverter; when the system power supply voltage is lower than a preset threshold, the output end of the inverter outputs a low-level reset signal, and when the system power supply voltage is higher than the preset threshold, the output end of the inverter outputs a high-level stop reset signal. The present application can work stably at low voltage, and the area can also be greatly optimized compared to the traditional power-on reset circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of reset circuits, and in particular to a power-on reset circuit and an integrated circuit system. Background Art

[0002] With the development of integrated circuits, power consumption has gradually become a key issue that limits the application of integrated circuits. Especially for battery-powered or self-powered systems, the requirements for integrated circuit power consumption are more stringent. Since the power consumption of integrated circuits is directly related to the power supply voltage, reducing the power supply voltage can effectively reduce the power consumption of integrated circuits. Therefore, low-voltage technology has received widespread attention in recent years. In integrated circuit systems, a power-on reset circuit is always required to reset the storage units in the system to an initial state during the initial power-on process of the system. In order to adapt to the development of low-voltage technology, the power-on reset circuit also needs to work stably at low voltage, but the traditional power-on reset circuit is difficult to work stably at low voltage due to the existence of the bandgap reference circuit, and the area of ​​the bandgap reference circuit is large. Summary of the invention

[0003] The object of the present invention is to provide a power-on reset circuit and an integrated circuit system, which can work stably at a low voltage and whose area can be greatly optimized compared with a traditional power-on reset circuit.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0005] An aspect of an embodiment of the present invention provides a power-on reset circuit and an integrated circuit system, wherein the reset circuit comprises: a first NMOS tube, wherein the drain of the first NMOS tube is connected to a system power supply, the gate of the first NMOS tube is grounded, and the source of the first NMOS tube is used to output a reference voltage; a current mirror circuit, wherein one end of the current mirror circuit is used to receive the reference voltage, and the other end of the current mirror circuit is used to copy the current value of the reference voltage for output; a second NMOS tube and a voltage divider circuit, wherein the input end of the voltage divider circuit receives the system power supply, the output end of the voltage divider circuit is connected to the gate of the second NMOS tube, and the voltage divider circuit is used to control the operation of the second NMOS tube; an inverter, wherein the source of the second NMOS tube is grounded, and the drain of the second NMOS tube is connected to the input end of the inverter and the other end of the current mirror circuit; when the system power supply voltage is lower than a preset threshold, the output end of the inverter outputs a low-level reset signal, and when the system power supply voltage is higher than the preset threshold, the output end of the inverter outputs a high-level stop reset signal.

[0006] In some embodiments, the current mirror circuit includes a first sub-current mirror circuit and a second sub-current mirror circuit, one end of the first sub-current mirror circuit is connected to the source of the first NMOS tube, the other end of the first sub-current mirror circuit is connected to one end of the second sub-current mirror circuit, the other end of the second sub-current mirror circuit is connected to the drain of the second NMOS tube and the input end of the inverter, the first sub-current mirror circuit is used to receive the reference voltage, and output the current value of the reference voltage to the second sub-current mirror circuit after a first copy, and the second sub-current mirror circuit outputs the current value of the reference voltage after a second copy.

[0007] In some embodiments, the first sub-current mirror circuit includes a third NMOS tube and a fourth NMOS tube, the gate of the third NMOS tube is connected to the drain of the third NMOS tube, the source of the first NMOS tube and the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to one end of the second sub-current mirror circuit, the source of the third NMOS tube and the source of the fourth NMOS tube are grounded, and the other end of the second sub-current mirror circuit is connected to the input end of the inverter and the drain of the second NMOS tube.

[0008] In some embodiments, the second sub-current mirror circuit includes a first PMOS tube and a second PMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are both connected to the system power supply, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the second PMOS tube and the drain of the fourth NMOS tube, and the drain of the first PMOS tube is connected to the input end of the inverter and the drain of the second NMOS tube.

[0009] In some embodiments, the voltage divider circuit includes a first unidirectional conducting element and a second unidirectional conducting element, the input end of the first unidirectional conducting element is connected to a system power supply, the output end of the first unidirectional conducting element is connected to the input end of the second unidirectional conducting element and the gate of the second NMOS tube, and the output end of the second unidirectional conducting element is grounded.

[0010] In some embodiments, the first unidirectional conducting element includes a third PMOS tube and a fourth PMOS tube, the source of the third PMOS tube is connected to the system power supply, the gate of the third PMOS tube is connected to the drain of the third PMOS tube and the source of the fourth PMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube, the input end of the second unidirectional conducting element and the gate of the second NMOS tube.

[0011] In some embodiments, the second unidirectional conducting element includes a fifth PMOS tube, a source of the fifth PMOS tube is connected to a gate of the fourth PMOS tube, a drain of the fourth PMOS tube and a gate of the second NMOS tube, and a gate of the fifth PMOS tube is connected to a drain and a ground of the fifth PMOS tube.

[0012] In some embodiments, the turn-on voltage of the first NMOS tube is a first voltage threshold, the turn-on voltages of the third NMOS tube, the fourth NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are a second voltage threshold, and the turn-on voltage of the second NMOS tube is a third voltage threshold.

[0013] In some embodiments, the third threshold > the second threshold > the first threshold.

[0014] An aspect of an embodiment of the present invention provides an integrated circuit system, wherein the integrated circuit system includes the reset circuit as described above.

[0015] A power-on reset circuit and an integrated circuit system according to an embodiment of the present invention have at least the following beneficial effects: the conventional power-on reset circuit is implemented by a bandgap reference and a comparator circuit, but the bandgap reference circuit is difficult to work stably at a low voltage, and the area of ​​the bandgap reference circuit is large. The power-on reset circuit of the present application is only composed of MOS transistors, relying on transistors of the first threshold, the second threshold and the third threshold, that is, the subthreshold current of the low threshold transistor and the source-drain current of the high threshold transistor to generate a stable reset signal. The structure can work stably at a low voltage, and because no bipolar devices and resistor devices are required, the area can be greatly optimized compared to the conventional power-on reset circuit.

[0016] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 FIG. 4 is a schematic diagram of a power-on reset circuit according to an embodiment. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0021] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected", "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present disclosure will be more comprehensive and complete and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0023] The technical solution of the embodiment of the present application is briefly described below:

[0024] According to some embodiments, Figure 1 As shown, the present application provides a power-on reset circuit, the reset circuit comprising:

[0025] A first NMOS transistor NM1, wherein a drain of the first NMOS transistor NM1 is connected to a system power supply VDD, a gate of the first NMOS transistor NM1 is grounded VSS, and a source of the first NMOS transistor NM1 is used to output a reference voltage;

[0026] A current mirror circuit, one end of which is used to receive the reference voltage, and the other end of which is used to copy the current value of the reference voltage for output;

[0027] A second NMOS transistor NM2 and a voltage divider circuit, wherein the input end of the voltage divider circuit receives the system power supply VDD, the output end of the voltage divider circuit is connected to the gate of the second NMOS transistor NM2, and the voltage divider circuit is used to control the operation of the second NMOS transistor NM2;

[0028] An inverter NOT, a source of the second NMOS tube NM2 is grounded to VSS, and a drain of the second NMOS tube NM2 is connected to an input end of the inverter NOT and the other end of the current mirror circuit;

[0029] When the voltage of the system power supply VDD is lower than the preset threshold, the output end of the inverter NOT outputs a low-level reset signal RSTN. When the voltage of the system power supply VDD is higher than the preset threshold, the output end of the inverter NOT outputs a high-level stop reset signal RSTN.

[0030] Based on the working principle of the above embodiment, after the system is powered on, the voltage of the system power supply VDD gradually rises until the source of the first NMOS tube NM1 outputs a stable reference voltage, and the reference voltage is positive. The current mirror circuit copies the current value of the reference voltage and outputs it to the input end of the inverter NOT, so as to pull up the input voltage of the inverter NOT. The drain of the gate of the second NMOS tube NM2 is used to pull down the input voltage of the inverter NOT. At this time, the voltage of the system power supply VDD continues to rise. When the voltage of the system power supply VDD is lower than the preset threshold, the reference voltage is greater than the voltage output by the voltage divider circuit to the gate of the second NMOS tube NM2. The input voltage of the inverter NOT is pulled up to a high level, and the inverter NOT outputs a low-level reset signal RSTN. When the voltage of the system power supply VDD is higher than the preset threshold, the reference voltage is less than the voltage output by the voltage divider circuit to the gate of the second NMOS tube NM2. The input voltage of the inverter NOT is pulled down to a low level, and the inverter NOT outputs a high-level stop reset signal RSTN.

[0031] The following is combined with the appendix of this manual Figure 1 , the preferred implementation modes of the present disclosure are further elaborated in detail.

[0032] According to some embodiments, Figure 1As shown, the current mirror circuit includes a first sub-current mirror circuit and a second sub-current mirror circuit, one end of the first sub-current mirror circuit is connected to the source of the first NMOS tube NM1, the other end of the first sub-current mirror circuit is connected to one end of the second sub-current mirror circuit, the other end of the second sub-current mirror circuit is connected to the drain of the second NMOS tube NM2 and the input end of the inverter NOT, the first sub-current mirror circuit is used to receive the reference voltage, and output the current value of the reference voltage to the second sub-current mirror circuit after a first copy, and the second sub-current mirror circuit outputs the current value of the reference voltage after a second copy.

[0033] Further, such as Figure 1 As shown, the first sub-current mirror circuit includes a third NMOS tube NM3 and a fourth NMOS tube NM4, the gate of the third NMOS tube NM3 is connected to the drain of the third NMOS tube NM3, the source of the first NMOS tube NM1 and the gate of the fourth NMOS tube NM4, the drain of the fourth NMOS tube NM4 is connected to one end of the second sub-current mirror circuit, the source of the third NMOS tube NM3 and the source of the fourth NMOS tube NM4 are grounded VSS, and the other end of the second sub-current mirror circuit is connected to the input end of the inverter NOT and the drain of the second NMOS tube NM2.

[0034] Further, such as Figure 1 As shown, the second sub-current mirror circuit includes a first PMOS tube PM1 and a second PMOS tube PM2, the source of the first PMOS tube PM1 and the source of the second PMOS tube PM2 are both connected to the system power supply VDD, the gate of the first PMOS tube PM1 is connected to the gate of the second PMOS tube PM2, the drain of the second PMOS tube PM2 and the drain of the fourth NMOS tube NM4, and the drain of the first PMOS tube PM1 is connected to the input end of the inverter NOT and the drain of the second NMOS tube NM2.

[0035] According to some embodiments, Figure 1 As shown, the voltage divider circuit includes a first unidirectional conducting element and a second unidirectional conducting element, the input end of the first unidirectional conducting element is connected to the system power supply VDD, the output end of the first unidirectional conducting element is connected to the input end of the second unidirectional conducting element and the gate of the second NMOS tube NM2, and the output end of the second unidirectional conducting element is grounded VSS.

[0036] According to some embodiments, Figure 1As shown, the first unidirectional conducting element includes a third PMOS tube PM3 and a fourth PMOS tube PM4, the source of the third PMOS tube PM3 is connected to the system power supply VDD, the gate of the third PMOS tube PM3 is connected to the drain of the third PMOS tube PM3 and the source of the fourth PMOS tube PM4, and the gate of the fourth PMOS tube PM4 is connected to the drain of the fourth PMOS tube PM4, the input end of the second unidirectional conducting element and the gate of the second NMOS tube NM2.

[0037] According to some embodiments, Figure 1 As shown, the second unidirectional conducting element includes a fifth PMOS tube PM4, a source of the fifth PMOS tube PM5 is connected to the gate of the fourth PMOS tube PM4, a drain of the fourth PMOS tube PM4 and a gate of the second NMOS tube NM2, and a gate of the fifth PMOS tube PM5 is connected to the drain of the fifth PMOS tube PM5 and a ground VSS.

[0038] Among them, the unidirectional conducting element can be a diode or a base and collector connection of an NPN transistor, etc., which is not limited in this application.

[0039] According to some embodiments, Figure 1 As shown, the turn-on voltage of the first NMOS tube NM1 is the first voltage threshold, the turn-on voltages of the third NMOS tube NM3, the fourth NMOS tube NM4, the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3, the fourth PMOS tube PM4 and the fifth PMOS tube PM5 are the second voltage threshold, and the turn-on voltage of the second NMOS tube NM2 is the third voltage threshold.

[0040] Among them, the third threshold>the second threshold>the first threshold.

[0041] The working principle of the present application is that the gate of the first NMOS tube NM1 is grounded to VSS, and its subthreshold voltage is used as a reference voltage. As the voltage of the system power supply VDD rises, the reference voltage remains unchanged. The gate of the third PMOS tube PM3 is connected to the drain, the gate of the fourth PMOS tube PM4 is connected to the drain, and the gate of the fifth PMOS tube PM5 is connected to the drain, so that the third PMOS tube PM3, the fourth PMOS tube PM4 and the fifth PMOS tube PM5 form a diode structure, which can divide the voltage of the system power supply VDD equally. The voltage of the system power supply VDD after voltage division is connected to the gate of the second NMOS tube NM2. As the voltage of the system power supply VDD increases, the gate current voltage of the second NMOS tube NM2 gradually increases. The third NMOS tube NM3 and the fourth NMOS tube NM4 are connected to form a current mirror structure to copy the current value of the reference voltage of the first NMOS tube NM1. Similarly, the first PMOS tube PM1 and the second PMOS tube PM2 are also current mirror structures, so the current of the first PMOS tube PM1 is equal to the current value of the reference voltage of the first NMOS tube NM1. Initially, the gate current voltage of the second NMOS transistor NM2 is less than the reference voltage, so the node V2 is charged to a high level, and the inverter NOT outputs a low-level reset signal RSTN. As the system power supply VDD voltage rises, the gate current voltage of the second NMOS transistor NM2 gradually increases until it exceeds the reference voltage, causing the node V2 to discharge to a low level, and the inverter NOT outputs a high-level stop reset signal RSTN.

[0042] The traditional power-on reset circuit is implemented by a bandgap reference and a comparator circuit, but the bandgap reference circuit is difficult to work stably at low voltage, and the area of ​​the bandgap reference circuit is large. The power-on reset circuit of the present application is composed of only MOS transistors, relying on transistors of the first threshold, the second threshold and the third threshold, that is, the subthreshold current of the low threshold transistor and the source-drain current of the high threshold transistor to generate a stable reset signal. This structure can work stably at low voltage, and because no bipolar devices and resistor devices are required, the area can be greatly optimized compared to the traditional power-on reset circuit.

[0043] According to some embodiments, the present application provides an integrated circuit system, which includes the reset circuit as described above.

[0044] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0045] Although the present disclosure has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present disclosure can be implemented in a variety of forms without departing from the spirit or essence of the present application, it should be understood that the above-mentioned embodiments are not limited to any of the foregoing details, but should be widely interpreted within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A power-on reset circuit, characterized in that: The reset circuit comprises: A first NMOS tube, wherein a drain of the first NMOS tube is connected to a system power supply, a gate of the first NMOS tube is grounded, and a source of the first NMOS tube is used to output a reference voltage; A current mirror circuit, one end of which is used to receive the reference voltage, and the other end of which is used to copy the current value of the reference voltage for output; A second NMOS tube and a voltage divider circuit, wherein the input end of the voltage divider circuit receives the system power supply, the output end of the voltage divider circuit is connected to the gate of the second NMOS tube, and the voltage divider circuit is used to control the operation of the second NMOS tube; An inverter, a source of the second NMOS tube is grounded, and a drain of the second NMOS tube is connected to an input end of the inverter and the other end of the current mirror circuit; When the system power supply voltage is lower than the preset threshold, the output end of the inverter outputs a low-level reset signal, and when the system power supply voltage is higher than the preset threshold, the output end of the inverter outputs a high-level stop reset signal; The gate and drain of the third PMOS tube are connected, the gate and drain of the fourth PMOS tube are connected, and the gate and drain of the fifth PMOS tube are connected, so that the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube form a diode structure to equally divide the voltage of the system power supply VDD; The third NMOS tube and the fourth NMOS tube are connected to form a current mirror structure, and the first PMOS tube and the second PMOS tube are connected to form a current mirror structure; The turn-on voltage of the first NMOS tube is a first voltage threshold, the turn-on voltages of the third NMOS tube, the fourth NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are a second voltage threshold, the turn-on voltage of the second NMOS tube is a third voltage threshold, the third voltage threshold>the second voltage threshold>the first voltage threshold, and the power-on reset circuit is composed only of MOS transistors.

2. The reset circuit according to claim 1, characterized in that: The current mirror circuit includes a first sub-current mirror circuit and a second sub-current mirror circuit, one end of the first sub-current mirror circuit is connected to the source of the first NMOS tube, the other end of the first sub-current mirror circuit is connected to one end of the second sub-current mirror circuit, the other end of the second sub-current mirror circuit is connected to the drain of the second NMOS tube and the input end of the inverter, the first sub-current mirror circuit is used to receive the reference voltage, and output the current value of the reference voltage to the second sub-current mirror circuit after a first copy, and the second sub-current mirror circuit outputs the current value of the reference voltage after a second copy.

3. The reset circuit according to claim 2, characterized in that: The first sub-current mirror circuit includes a third NMOS tube and a fourth NMOS tube, the gate of the third NMOS tube is connected to the drain of the third NMOS tube, the source of the first NMOS tube and the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to one end of the second sub-current mirror circuit, the source of the third NMOS tube and the source of the fourth NMOS tube are grounded, and the other end of the second sub-current mirror circuit is connected to the input end of the inverter and the drain of the second NMOS tube.

4. The reset circuit according to claim 3, characterized in that: The second sub-current mirror circuit includes a first PMOS tube and a second PMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are both connected to the system power supply, the gate of the first PMOS tube is connected to the gate of the second PMOS tube, the drain of the second PMOS tube and the drain of the fourth NMOS tube, and the drain of the first PMOS tube is connected to the input end of the inverter and the drain of the second NMOS tube.

5. The reset circuit according to claim 4, characterized in that: The voltage divider circuit includes a first unidirectional conducting element and a second unidirectional conducting element, wherein the input end of the first unidirectional conducting element is connected to a system power supply, the output end of the first unidirectional conducting element is connected to the input end of the second unidirectional conducting element and a gate of the second NMOS tube, and the output end of the second unidirectional conducting element is grounded.

6. The reset circuit according to claim 5, characterized in that: The first unidirectional conducting element includes a third PMOS tube and a fourth PMOS tube, the source of the third PMOS tube is connected to the system power supply, the gate of the third PMOS tube is connected to the drain of the third PMOS tube and the source of the fourth PMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube, the input end of the second unidirectional conducting element and the gate of the second NMOS tube.

7. The reset circuit according to claim 6, characterized in that: The second unidirectional conducting element comprises a fifth PMOS tube, a source of the fifth PMOS tube is connected to a gate of the fourth PMOS tube, a drain of the fourth PMOS tube and a gate of the second NMOS tube, and a gate of the fifth PMOS tube is connected to a drain and a ground of the fifth PMOS tube.

8. An integrated circuit system, characterized in that: The integrated circuit system comprises the reset circuit according to any one of claims 1 to 7.

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