Solar cell and method for manufacturing the same

Abstract

The present application relates to a solar cell and a method for preparing the same. A solar cell comprises: a substrate layer, the substrate layer comprises a first surface and a second surface arranged opposite to each other, the first surface of the substrate layer being provided with a first groove; a first transparent conductive layer, the first transparent conductive layer being provided on the first surface and covering the first groove and the area of ​​the first surface other than the first groove; a first gate line electrode, the first gate line electrode being provided on the surface of the first transparent conductive layer away from the substrate layer. The groove design on the substrate layer of the solar cell can increase the coating thickness of the transparent conductive layer, so that the square resistance inside the groove is smaller than the square resistance outside the groove, thereby realizing the design of selective high square resistance area and low square resistance area, which can reduce the series resistance, increase the carrier transmission efficiency, and improve the conversion efficiency of the battery.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] In order to achieve the goal of reducing dependence on traditional fossil energy and increasing the use of new green energy, vigorously developing photovoltaic power generation technology is one of the main means.

[0003] Passivated Emitter and Rear Cell (PERC) is the mainstream technology in the current photovoltaic cell market and has achieved a long life cycle. However, the efficiency of PERC cells is close to the theoretical efficiency limit of 24%. Subsequently, new solar cell categories with higher theoretical efficiency limits have been developed in the market, such as heterojunction solar cells (Hereto-junction with Intrinsic Thin-layer, HJT), tunnel oxide passivating contacts (TOPCon), etc.

[0004] Among them, heterojunction solar cells have the advantages of simple structure, low process temperature, good passivation effect, high open circuit voltage, good temperature characteristics, and double-sided power generation, and are one of the hot research directions for developing high conversion efficiency silicon-based solar cells. However, the conversion efficiency of heterojunction solar cells on the market is still a certain distance away from the theoretical limit, and how to achieve higher energy conversion efficiency is the current research focus. Summary of the invention

[0005] Based on this, it is necessary to provide a solar cell and a preparation method thereof that can improve energy conversion efficiency.

[0006] In a first aspect, the present application provides a solar cell, comprising:

[0007] A base layer, the base layer comprising a first surface and a second surface arranged opposite to each other, and the first surface of the base layer is provided with a first groove;

[0008] a first transparent conductive layer, wherein the first transparent conductive layer is disposed on the first surface and covers the first groove and an area of ​​the first surface except the first groove;

[0009] A first gate line electrode is disposed on a surface of the first transparent conductive layer away from the base layer.

[0010] In some embodiments, a second groove is disposed on at least a portion of the surface of the first transparent conductive layer corresponding to the first groove, and at least a portion of the first gate line electrode is disposed in the second groove.

[0011] In some embodiments, at least a portion of the first gate line electrode fills up the second groove.

[0012] In some embodiments, there are a plurality of first grooves, and a second groove is disposed on at least a portion of the surface of the first transparent conductive layer corresponding to at least one of the first grooves.

[0013] In some embodiments, the first transparent conductive layer includes: a first transparent conductive oxide layer;

[0014] The first transparent conductive oxide layer is provided with a depression on the surface of at least a portion of the area corresponding to the first groove, so as to form the second groove in at least a portion of the area of ​​the first transparent conductive layer corresponding to the first groove.

[0015] In some embodiments, the first transparent conductive layer comprises: at least one first transparent conductive oxide layer and at least one first metal nanowire layer alternately stacked;

[0016] At least one of the first metal nanowire layers and at least one of the first transparent conductive oxide layers are provided with depressions in at least a portion of the surface corresponding to the first groove, so as to form the second groove in at least a portion of the first transparent conductive layer corresponding to the first groove.

[0017] In some of the embodiments, the solar cell further comprises: a second transparent conductive layer and a second grid line electrode;

[0018] The second transparent conductive layer is disposed on the second surface of the base layer, and the second gate line electrode is disposed on a surface of the second transparent conductive layer away from the base layer.

[0019] In some embodiments, a third groove is disposed on the second surface of the base layer, and the second transparent conductive layer covers the third groove and an area of ​​the second surface except the third groove.

[0020] In some embodiments, a fourth groove is disposed on at least a portion of the surface of the second transparent conductive layer corresponding to the third groove, and at least a portion of the second gate line electrode is disposed in the fourth groove.

[0021] In some embodiments, at least a portion of the second gate line electrode fills up the fourth groove.

[0022] In some embodiments, there are a plurality of the third grooves, and the fourth groove is disposed on at least a partial area of ​​the surface of the second transparent conductive layer corresponding to at least one of the third grooves.

[0023] In some embodiments, the second transparent conductive layer includes: a second transparent conductive oxide layer;

[0024] The second transparent conductive oxide layer is provided with a depression on the surface of at least a portion of the area corresponding to the third groove, so as to form the fourth groove in at least a portion of the area of ​​the second transparent conductive layer corresponding to the third groove.

[0025] In some embodiments, the second transparent conductive layer comprises: at least one second transparent conductive oxide layer and at least one second metal nanowire layer alternately stacked;

[0026] At least one layer of the second metal nanowire layer and at least one layer of the second transparent conductive oxide layer are both provided with depressions in at least a portion of the surface corresponding to the third groove, so as to form the fourth groove in at least a portion of the second transparent conductive layer corresponding to the third groove.

[0027] In a second aspect, the present application further provides a method for preparing a solar cell as described in any embodiment of the first aspect above, comprising the following steps:

[0028] Providing a base layer, the base layer comprising a first surface and a second surface disposed opposite to each other;

[0029] forming a first groove on the first surface of the base layer;

[0030] forming a first transparent conductive layer on the first surface, wherein the first transparent conductive layer covers the first groove and an area of ​​the first surface except the first groove;

[0031] A first gate line electrode is formed on a surface of the first transparent conductive layer away from the base layer.

[0032] The solar cell provided in the present application has a first groove arranged on the first surface of the substrate, and the first transparent conductive layer is arranged on the first surface and covers the first groove and the area other than the first groove. The design of the first groove can increase the coating thickness of the first transparent conductive layer, so that the square resistance inside the first groove is smaller than the square resistance outside the first groove, thereby realizing the design scheme of selective high square resistance area and low square resistance area, and further, the first grid line electrode is arranged on the surface of the first transparent conductive layer away from the substrate layer, which can increase the transmission efficiency of carriers and is conducive to improving the conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1Schematic diagram of the structure of a solar cell in traditional technology.

[0034] Figure 2 Schematic diagram of the structure of a solar cell in some embodiments of the present application.

[0035] Description of reference numerals:

[0036] 1: solar cell; 11: substrate layer; 12: passivation layer; 13: doping layer; 14: transparent conductive layer; 15: gate electrode; 2: solar cell; 21: substrate layer; 22: first groove; 23: first transparent conductive layer; 24: first gate electrode; 25: second groove; 26: first passivation layer; 27: first doping layer. DETAILED DESCRIPTION

[0037] For ease of understanding of the present application, the present application will be described more fully below in conjunction with embodiments. However, the present application can be implemented in many different forms and is not limited to the embodiments described in the present application. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0040] like Figure 1 As shown, a conventional solar cell 1 is composed of a substrate layer 11, a passivation layer 12, a doping layer 13, a transparent conductive layer 14 and a gate electrode 15. Each layer structure is a flat structure with a high series resistance and low carrier transfer efficiency.

[0041] like Figure 2 As shown, in order to overcome the above-mentioned problems of high series resistance and low carrier transfer efficiency, the present application provides a solar cell 2, comprising:

[0042] A base layer 21, the base layer 21 comprises a first surface and a second surface which are arranged opposite to each other, and a first groove 22 is arranged on the first surface of the base layer 21;

[0043] A first transparent conductive layer 23, which is disposed on the first surface and covers the first groove 22 and the area of ​​the first surface except the first groove 22;

[0044] The first gate line electrode 24 is disposed on a surface of the first transparent conductive layer 23 away from the base layer 21 .

[0045] The solar cell 2 provided in the present application has a first groove 22 disposed on the first surface of the substrate, and a first transparent conductive layer 23 is disposed on the first surface and covers the first groove 22 and the area other than the first groove 22. The design of the first groove 22 can increase the coating thickness of the first transparent conductive layer 23, so that the square resistance inside the first groove 22 is smaller than the square resistance outside the first groove 22, thereby realizing the design of selective high square resistance area and low square resistance area, which is beneficial to the control of electrical performance. Furthermore, the first grid line electrode 24 is disposed on the surface of the first transparent conductive layer 23 away from the substrate layer 21, and the low resistance channel formed in the first groove 22 can be used as a grid line, which can increase the transmission efficiency of carriers and is beneficial to improving the conversion efficiency of the battery.

[0046] In some embodiments, a second groove 25 is provided on the surface of at least a portion of the first transparent conductive layer 23 corresponding to the first groove 22, and at least a portion of the first gate electrode 24 is disposed in the second groove 25. At least a portion of the first gate electrode 24 is disposed in the second groove 25, which is beneficial to improving the contact effect between the first gate electrode 24 and the first transparent conductive layer 23, thereby reducing the series resistance, improving the fill factor and conversion efficiency, and the above structure also has a buried gate effect, which can further improve the series resistance.

[0047] In some of the embodiments, at least a portion of the first gate line electrode 24 fills the second groove 25, so that the first gate line electrode 24 can be in contact with the first transparent conductive layer 23 more firmly and tightly, which is beneficial to improving the series resistance and having a better buried gate effect, thereby improving the battery energy conversion efficiency.

[0048] In some embodiments, there are multiple first grooves 22, and the first transparent conductive layer 23 is provided with a second groove 25 on at least a partial surface area corresponding to at least one of the first grooves 22. It can be understood that there are multiple first grooves 22, and the second groove 25 can be provided on at least a partial surface area corresponding to each first groove 22, or the second groove 25 can be provided on at least a partial surface area corresponding to several of the first grooves 22. It can be understood that if the second groove 25 is not provided on the surface area of ​​the first transparent conductive layer 23 corresponding to the first groove 22, the first groove 22 is filled with the first transparent conductive layer 23, so that the thickness of the first transparent conductive layer 23 at the first groove 22 is increased, which is more conducive to reducing the square resistance. Further, the low-resistance channel formed can also be used as a gate line, which can increase the carrier transmission performance; if the second groove 25 is provided on the surface area of ​​the first transparent conductive layer 23 corresponding to the first groove 22, the contact effect between the first gate line electrode 24 and the first transparent conductive layer 23 can be improved, thereby reducing the series resistance and having a buried gate effect.

[0049] In some embodiments, the first transparent conductive layer 23 includes: a first transparent conductive oxide layer.

[0050] The first transparent conductive oxide layer is provided with a depression on the surface of at least a portion of the area corresponding to the first groove 22 , so as to form a second groove 25 in at least a portion of the area of ​​the first transparent conductive layer 23 corresponding to the first groove 22 .

[0051] The first transparent conductive oxide layer has good conductivity and transmittance, and is beneficial to electrical conduction and light transmission.

[0052] Furthermore, the material of the first transparent conductive oxide layer may be, for example but not limited to, selected from ITO, VTTO, and the like.

[0053] In some embodiments, the first transparent conductive layer 23 includes: at least one first transparent conductive oxide layer and at least one first metal nanowire layer alternately stacked.

[0054] At least one first metal nanowire layer and at least one first transparent conductive oxide layer are both provided with depressions in at least a portion of the surface corresponding to the first groove 22 , so as to form a second groove 25 in at least a portion of the first transparent conductive layer 23 corresponding to the first groove 22 .

[0055] The first transparent conductive layer 23 is composed of a first transparent conductive oxide layer and a first metal nanowire layer. The first metal nanowire layer is beneficial to reducing the contact resistance between the first gate electrode 24 and the first transparent conductive oxide layer, and is also beneficial to reducing the body resistance of the first transparent conductive oxide layer in other areas not corresponding to the first gate electrode 24. At the same time, the metal nanowire layer in the first transparent conductive layer 23 corresponding to the second groove 25 can balance the optical and electrical properties, reduce the series resistance while ensuring the optical performance, and is beneficial to improving the fill factor and conversion efficiency of the solar cell 2.

[0056] It can be understood that when the first transparent conductive oxide layer and the first metal nanowire layer have multiple layers respectively, the stacking order from the first surface of the base layer 21 along the direction of the first gate electrode 24 can be alternating in the order of first the first transparent conductive oxide layer and then the first metal nanowire layer, and can be alternating in the order of first the first metal nanowire layer and then the first transparent conductive oxide layer.

[0057] It can be understood that when there are multiple first transparent conductive oxide layers, they can be referred to as the first first transparent conductive oxide layer, the second first transparent conductive oxide layer, and so on.

[0058] It can be understood that when the first metal nanowire layer has multiple layers, it can be called the first first metal nanowire layer, the second first metal nanowire layer... and so on.

[0059] Preferably, the layer closest to the base layer 21 is the first transparent conductive oxide layer.

[0060] Preferably, the layer closest to the first gate line electrode 24 is the first transparent conductive oxide layer.

[0061] Furthermore, the material of the first metal nanowire layer may be, for example but not limited to, silver.

[0062] In some embodiments, the material of the base layer 21 may be, for example, crystalline silicon, or other materials such as transparent glass.

[0063] In some embodiments, the material of the first gate line electrode 24 may be, for example but not limited to, silver.

[0064] It can be understood that the interior of the first groove 22 and other areas outside the first groove 22 on the first surface of the base layer 21 can be a flat structure or a non-flat structure independently.

[0065] It can be understood that the inside of the second groove 25 and other areas outside the second groove 25 on the surface of the first transparent conductive layer 23 can be a flat structure or a non-flat structure independently.

[0066] In some embodiments, the solar cell 2 further includes a first passivation layer 26 and a first doping layer 27, which are sequentially stacked between the first surface of the substrate layer 21 and the first transparent conductive layer 23. Further, the material of the first passivation layer 26 may be, for example, but not limited to, intrinsic amorphous silicon. Further, the material of the first doping layer 27 may be, for example, but not limited to, doped microcrystalline silicon.

[0067] It can be understood that if a first groove 22 is provided on the first surface of the base layer 21, and a second groove 25 is provided on the surface of at least a portion of the area corresponding to the first groove 22 of the first transparent conductive layer 23, then depressions are provided on the surfaces of at least a portion of the area corresponding to the first groove 22 of the first passivation layer 26 and the first doping layer 27, so as to facilitate the formation of the second groove 25 in at least a portion of the area of ​​the first transparent conductive layer 23 corresponding to the first groove 22.

[0068] It is understandable that the solar cell 2 may be a double-sided structure, and the second surface of the base layer 21 may adopt a conventional structure of a heterojunction solar cell, or may adopt the same structure as the first surface. That is, the second surface may have a corresponding groove structure, or may not have a groove structure.

[0069] In some of the embodiments, the solar cell 2 further includes: a second transparent conductive layer and a second grid line electrode;

[0070] The second transparent conductive layer is disposed on the second surface of the base layer 21 , and the second gate line electrode is disposed on the surface of the second transparent conductive layer away from the base layer 21 .

[0071] In some of the embodiments, the second surface of the base layer 21 is provided with a third groove, and the second transparent conductive layer covers the third groove and the area of ​​the second surface except the third groove.

[0072] In some embodiments, a fourth groove is disposed on at least a portion of the surface of the second transparent conductive layer corresponding to the third groove, and at least a portion of the second gate line electrode is disposed in the fourth groove.

[0073] In some embodiments, at least a portion of the second gate line electrode fills up the fourth groove.

[0074] In some of the embodiments, there are a plurality of third grooves, and a fourth groove is disposed on at least a portion of the surface of the second transparent conductive layer corresponding to at least one of the third grooves.

[0075] In some embodiments, the second transparent conductive layer includes: a second transparent conductive oxide layer.

[0076] The second transparent conductive oxide layer is provided with a depression on the surface of at least a portion of the area corresponding to the third groove, so as to form a fourth groove in at least a portion of the area of ​​the second transparent conductive layer corresponding to the third groove.

[0077] In some embodiments, the second transparent conductive layer includes: at least one second transparent conductive oxide layer and at least one second metal nanowire layer alternately stacked.

[0078] At least one second metal nanowire layer and at least one second transparent conductive oxide layer are both provided with depressions in at least a portion of the surface corresponding to the third groove, so as to form a fourth groove in at least a portion of the second transparent conductive layer corresponding to the third groove.

[0079] In some embodiments, the solar cell 2 further includes a second passivation layer and a second doping layer, and the second passivation layer and the second doping layer are sequentially stacked and disposed between the second surface of the substrate layer 21 and the second transparent conductive layer.

[0080] It can be understood that in the structure located on the second surface of the base layer 21 , the structure and function of the second transparent conductive layer and the second gate line electrode are similar to those located on the second surface of the base layer 21 , and are not described in detail here.

[0081] In a second aspect, the present application further provides a method for preparing the solar cell 2 in any embodiment of the first aspect, comprising the following steps:

[0082] Providing a base layer 21, the base layer 21 includes a first surface and a second surface disposed opposite to each other;

[0083] A first groove 22 is formed on a first surface of the base layer 21;

[0084] Forming a first transparent conductive layer 23 on the first surface, the first transparent conductive layer 23 covers the first groove 22 and the area of ​​the first surface except the first groove 22;

[0085] A first gate line electrode 24 is formed on a surface of the first transparent conductive layer 23 away from the base layer 21 .

[0086] Furthermore, the first groove 22 can be prepared by combining regional protection and etching technology. It can be understood that the etching technology can be, for example, laser etching, wet etching, etc.

[0087] Furthermore, the first transparent conductive layer 23 includes at least one first transparent conductive oxide layer and at least one first metal nanowire layer.

[0088] Furthermore, the first metal nanowire layer is prepared by a solution method. By using a solution method to prepare the first metal nanowire layer, a thicker liquid film can be formed inside the first groove 22, so that there are more metal nanowires in the first groove 22, which is beneficial to reducing the square resistance in the first groove 22. It can be understood that the solution method can be, for example, but not limited to, spin coating, coating, roll coating, spray coating, etc.

[0089] The following are specific embodiments.

[0090] Example 1

[0091] A preparation method of a solar cell 2 comprises the following steps:

[0092] (1) A crystalline silicon base layer 21 is provided, and a first surface of the base layer 21 is locally etched by laser using silicon oxide protection to form a plurality of first grooves 22, which is then polished and textured to achieve a structure in which the outer surface of the base layer 21 of the first groove 22 is textured and the inner surface of the base layer 21 of the first groove 22 is polished, wherein the first surface is the back side of the base layer 21.

[0093] (2) A layer of intrinsic amorphous silicon is deposited on the first surface and the second surface of the base layer 21 respectively to form a first passivation layer 26 and a second passivation layer, wherein the second surface is the front side of the base layer 21 .

[0094] (3) A layer of doped microcrystalline silicon is deposited on the first passivation layer 26 and the second passivation layer respectively to form a first doped layer 27 and a second doped layer.

[0095] (4) depositing ITO with a thickness of 80 nm on the first doping layer 27 and the second doping layer, respectively, to form a first transparent conductive oxide layer and a second transparent conductive oxide layer;

[0096] The first transparent conductive oxide layer is provided with depressions on at least a portion of the surface corresponding to each first groove 22 to form a second groove 25 , and the depth of the groove is 2 μm.

[0097] (5) screen-printing a first gate line electrode 24 and a second gate line electrode on the first transparent conductive oxide layer and the second transparent conductive oxide layer, respectively;

[0098] On the first surface of the base layer 21 , the first gate line electrodes 24 are disposed in correspondence with each of the second grooves 25 , and the first gate line electrodes 24 fill up each of the second grooves 25 .

[0099] Example 2

[0100] (1) to (3) of Example 2 are the same as steps (1) to (3) of Example 1.

[0101] (4) in the first doping layer 27, a first transparent conductive oxide layer, a first metal nanowire layer, and a second transparent conductive oxide layer are sequentially stacked from the first surface of the base layer 21 along the direction of the first gate electrode 24;

[0102] The first transparent conductive oxide layer and the second transparent conductive oxide layer are both ITO with a thickness of 40 nm;

[0103] The first metal nanowire layer is silver nanowires;

[0104] Depositing ITO with a thickness of 80 nm on the second doped layer to form a second transparent conductive oxide layer;

[0105] The first transparent conductive oxide layer, the first metal nanowire layer, and the second transparent conductive oxide layer are all provided with depressions on the surface of at least a portion of the area corresponding to the first groove 22, so as to form a second groove 25 in at least a portion of the area of ​​the first transparent conductive layer 23 corresponding to the first groove 22, and the groove depth is 2μm.

[0106] (5) screen printing a first gate line electrode 24 and a second gate line electrode on the second first transparent conductive oxide layer and the second transparent conductive oxide layer respectively;

[0107] On the first surface of the base layer 21 , the first gate line electrodes 24 are disposed in correspondence with each of the second grooves 25 , and the first gate line electrodes 24 fill up each of the second grooves 25 .

[0108] Example 3

[0109] (1) to (3) of Example 3 are the same as steps (1) to (3) of Example 1.

[0110] (4) forming a first transparent conductive oxide layer and a first metal nanowire layer in sequence from the first surface of the base layer 21 along the direction of the first gate electrode 24 in the first doping layer 27;

[0111] The first transparent conductive oxide layer is ITO with a thickness of 80 nm;

[0112] The first metal nanowire layer is silver nanowires;

[0113] Depositing ITO with a thickness of 80 nm on the second doped layer to form a second transparent conductive oxide layer;

[0114] The first transparent conductive oxide layer and the first metal nanowire layer are both provided with depressions in at least a portion of the surface corresponding to the first groove 22 , so as to form a second groove 25 in at least a portion of the first transparent conductive layer 23 corresponding to the first groove 22 , and the groove depth is 2 μm.

[0115] (6) screen-printing a first gate line electrode 24 and a second gate line electrode on the first metal nanowire layer and the second transparent conductive oxide layer, respectively;

[0116] On the first surface of the base layer 21 , the first gate line electrodes 24 are disposed in correspondence with each of the second grooves 25 , and the first gate line electrodes 24 fill up each of the second grooves 25 .

[0117] Example 4

[0118] (1) to (3) of Example 4 are the same as steps (1) to (3) of Example 1.

[0119] (4) in the first doping layer 27, a first first transparent conductive oxide layer, a first metal nanowire layer, and a first first transparent conductive oxide layer are sequentially stacked from the first surface of the base layer 21 along the direction of the first gate electrode 24;

[0120] The first transparent conductive oxide layer and the second transparent conductive oxide layer are both ITO with a thickness of 40 nm;

[0121] The first metal nanowire layer is silver nanowires;

[0122] Depositing ITO with a thickness of 80 nm on the second doped layer to form a second transparent conductive oxide layer;

[0123] After the first transparent conductive oxide layer, the first metal nanowire layer, and the second transparent conductive oxide layer cover the first groove 22 , no depression is provided to form a second groove 25 .

[0124] (7) screen printing a first gate line electrode 24 and a second gate line electrode on the second first transparent conductive oxide layer and the second transparent conductive oxide layer, respectively;

[0125] On the first surface of the base layer 21 , the first gate line electrode 24 is disposed on a surface of the second first transparent conductive oxide layer away from the base layer 21 .

[0126] Example 5

[0127] (1) A crystalline silicon substrate is provided, and the first surface and the second surface of the substrate are locally etched by laser using silicon oxide protection to form a plurality of first grooves 22 and a third groove, and then polished and textured to achieve a structure in which the surface of the outer substrate layer 21 of the groove is textured and the surface of the inner substrate layer 21 of the groove is polished, wherein the first surface is the back side of the substrate layer 21, and the second surface is the front side of the substrate layer 21.

[0128] (2) A layer of intrinsic amorphous silicon is deposited on the first surface and the second surface of the base layer 21 respectively to form a first passivation layer 26 and a second passivation layer.

[0129] (3) A layer of doped microcrystalline silicon is deposited on the first passivation layer 26 and the second passivation layer respectively to form a first doped layer 27 and a second doped layer.

[0130] (4) The first doping layer 27 is stacked in sequence from the first surface of the base layer 21 along the direction of the first gate electrode 24 to form a first first transparent conductive oxide layer, a first metal nanowire layer, and a second first transparent conductive oxide layer;

[0131] In the second doping layer, a first second transparent conductive oxide layer, a second metal nanowire layer, and a second second transparent conductive oxide layer are sequentially stacked from the second surface of the base layer 21 along the direction of the second gate line electrode;

[0132] The first first transparent conductive oxide layer, the second first transparent conductive oxide layer, the first second transparent conductive oxide layer, and the second second transparent conductive oxide layer are all VTTO with a thickness of 40 nm;

[0133] The first metal nanowire layer and the second metal nanowire layer are both silver nanowires;

[0134] The first transparent conductive oxide layer, the first metal nanowire layer, and the second transparent conductive oxide layer are all provided with depressions on the surface of at least a portion of the area corresponding to the first groove 22, so as to form a second groove 25 in at least a portion of the area of ​​the first transparent conductive layer 23 corresponding to the first groove 22;

[0135] The first second transparent conductive oxide layer, the second metal nanowire layer, and the second second transparent conductive oxide layer are all provided with depressions on their surfaces in at least a portion of the area corresponding to the third groove, so as to form a fourth groove in at least a portion of the area of ​​the second transparent conductive layer corresponding to the third groove.

[0136] (5) screen-printing a first gate line electrode 24 and a second gate line electrode on the second first transparent conductive oxide layer and the second second transparent conductive oxide layer, respectively;

[0137] On the first surface of the base layer 21 , the first gate line electrodes 24 are disposed in correspondence with each of the second grooves 25 , and the first gate line electrodes 24 fill up each of the second grooves 25 .

[0138] On the second surface of the base layer 21 , the second gate line electrodes are disposed in the fourth grooves corresponding to each other, and the second gate line electrodes fill up the fourth grooves.

[0139] Comparative Example 1

[0140] (1) Providing a crystalline silicon base layer and performing texturing to realize a velvet structure on the surface of the base layer.

[0141] (2) Depositing a layer of intrinsic amorphous silicon on the first surface and the second surface of the substrate respectively to form a first passivation layer and a second passivation layer, wherein the first surface is the back side of the substrate layer and the second surface is the front side of the substrate layer.

[0142] (3) Depositing a layer of doped microcrystalline silicon on the first passivation layer and the second passivation layer respectively to form a first doped layer and a second doped layer.

[0143] (4) Depositing a layer of ITO with a thickness of 80 nm on the first doped layer and the second doped layer respectively to form a first transparent conductive oxide layer and a second transparent conductive oxide layer.

[0144] (5) Screen-printing a first gate line electrode and a second gate line electrode on the first transparent conductive oxide layer and the second transparent conductive oxide layer, respectively.

[0145] The solar cells of Examples 1 to 5 and the comparative example were subjected to a battery performance test, and the test results are shown in Table 1 below.

[0146] Table 1 Performance test results of solar cells

[0147]

[0148] It can be seen from Table 1 that the solar cells of Examples 1 to 5 have higher energy conversion efficiency than that of Comparative Example 1.

[0149] Compared with comparative example 1, the conversion efficiency Eff of the battery in embodiment 1 is improved by 0.07%, mainly because the setting of the first groove and the second groove on the back side realizes a certain degree of buried gate effect, which reduces the contact resistance of the first gate line electrode and increases the fill factor FF by 0.21%.

[0150] Compared with comparative example 1, the cell conversion efficiency Eff of Example 2 is increased by 0.14%, mainly because in addition to the buried gate effect of the first groove and the second groove, the presence of the nano silver wires arranged on the back can also reduce the contact resistance between the first gate electrode and the first transparent conductive oxide layer, as well as the body resistance of the first transparent conductive oxide layer in other regions, and finally achieve a fill factor FF increase of 0.56%. Moreover, the nano silver wires arranged on the back have little effect on the short-circuit current Isc, which is only reduced by 0.01A.

[0151] Compared with comparative example 1, the battery conversion efficiency Eff of Example 3 is increased by 0.08%, and compared with Example 2, the battery conversion efficiency Eff is reduced by 0.06%. This is mainly because there is no ITO layer covering the nano silver wires, and the bonding between the lower layer ITO and the nano silver wires is poor.

[0152] The first gate line electrode of Example 4 is not buried in the area corresponding to the first groove, and the first groove is completely covered by the first transparent conductive layer. When the gate line remains unchanged, the transparent conductive layer covering the first groove is equivalent to an additional gate line structure, thereby increasing the current transmission channel. Therefore, compared with Comparative Example 1, the battery conversion efficiency Eff of Example 4 is also improved by 0.04%.

[0153] Example 5 is a double-sided groove setting. Compared with Comparative Example 1, the battery conversion efficiency Eff is increased by 0.19%, and compared with Example 2, the battery conversion efficiency Eff is increased by 0.05%. This is mainly due to the gain on the front side. The double-sided groove setting further increases the gain of the filling factor FF, but the front side of the substrate layer has a greater impact on optics, so the gain is slightly lower than the back side.

[0154] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A solar cell, characterized in that: include: A base layer, the base layer comprising a first surface and a second surface arranged opposite to each other, and the first surface of the base layer is provided with a first groove; a first transparent conductive layer, wherein the first transparent conductive layer is disposed on the first surface and covers the first groove and a region of the first surface except the first groove, wherein a thickness of the first transparent conductive layer in the first groove is greater than a thickness of the first transparent conductive layer in a region except the first groove, and a sheet resistance of the first transparent conductive layer in the first groove is less than a sheet resistance of the first transparent conductive layer in a region except the first groove; A first gate line electrode, wherein the first gate line electrode is disposed on a surface of the first transparent conductive layer away from the base layer; A second groove is arranged on the surface of at least a portion of the first transparent conductive layer corresponding to the first groove, and at least a portion of the first gate line electrode fills up the second groove.

2. The solar cell according to claim 1, characterized in that There are a plurality of the first grooves, and the second groove is arranged on at least a partial area of ​​the surface of the first transparent conductive layer corresponding to at least one of the first grooves.

3. The solar cell according to claim 1, characterized in that The first transparent conductive layer includes: a first transparent conductive oxide layer; The first transparent conductive oxide layer is provided with a depression on the surface of at least a portion of the area corresponding to the first groove, so as to form the second groove in at least a portion of the area of ​​the first transparent conductive layer corresponding to the first groove.

4. The solar cell according to claim 3, characterized in that: The first transparent conductive layer comprises: at least one first transparent conductive oxide layer and at least one first metal nanowire layer alternately stacked; At least one of the first metal nanowire layers and at least one of the first transparent conductive oxide layers are provided with depressions in at least a portion of the surface corresponding to the first groove, so as to form the second groove in at least a portion of the first transparent conductive layer corresponding to the first groove.

5. The solar cell according to claim 4, characterized in that: The layer closest to the first gate line electrode is the first transparent conductive oxide layer.

6. The solar cell according to claim 4, characterized in that: The layer closest to the base layer is a first transparent conductive oxide layer.

7. The solar cell according to any one of claims 1 to 6, characterized in that: The solar cell further comprises: a second transparent conductive layer and a second grid line electrode; The second transparent conductive layer is disposed on the second surface of the base layer, and the second gate line electrode is disposed on a surface of the second transparent conductive layer away from the base layer.

8. The solar cell according to claim 7, characterized in that: A third groove is disposed on the second surface of the base layer, and the second transparent conductive layer covers the third groove and a region of the second surface except the third groove.

9. The solar cell according to claim 8, characterized in that A fourth groove is arranged on the surface of at least a portion of the second transparent conductive layer corresponding to the third groove, and at least a portion of the second gate line electrode is arranged in the fourth groove.

10. The solar cell according to claim 9, characterized in that: At least a portion of the second gate line electrode fills up the fourth groove.

11. The solar cell according to claim 9, characterized in that: There are a plurality of the third grooves, and the fourth groove is arranged on at least a partial area of ​​the surface of the second transparent conductive layer corresponding to at least one of the third grooves.

12. The solar cell according to any one of claims 9 to 11, characterized in that: The second transparent conductive layer includes: a second transparent conductive oxide layer; The second transparent conductive oxide layer is provided with a depression on the surface of at least a portion of the area corresponding to the third groove, so as to form the fourth groove in at least a portion of the area of ​​the second transparent conductive layer corresponding to the third groove.

13. The solar cell according to claim 12, characterized in that: The second transparent conductive layer comprises: at least one second transparent conductive oxide layer and at least one second metal nanowire layer alternately stacked; At least one layer of the second metal nanowire layer and at least one layer of the second transparent conductive oxide layer are both provided with depressions in at least a portion of the surface corresponding to the third groove, so as to form the fourth groove in at least a portion of the second transparent conductive layer corresponding to the third groove.

14. A method for preparing a solar cell according to any one of claims 1 to 13, characterized in that: The steps include: Providing a base layer, the base layer comprising a first surface and a second surface disposed opposite to each other; forming a first groove on the first surface of the base layer; forming a first transparent conductive layer on the first surface, wherein the first transparent conductive layer covers the first groove and an area of ​​the first surface except the first groove; A first gate line electrode is formed on a surface of the first transparent conductive layer away from the base layer.

Images