A method and system for improving photoresist packaging process

Abstract

The present invention relates to the field of photolithography manufacturing technology, and in particular to a method and system for improving photoresist packaging technology. The method comprises the following steps: performing surface pretreatment and hydrophobic drying treatment on the surface of a photolithography chip to obtain a hydrophobic surface for photolithography chip adhesion; performing multi-layer photoresist coating and packaging treatment on the hydrophobic surface for photolithography chip adhesion to obtain a chip photoresist coating and packaging layer; performing mask imaging auxiliary alignment and standing wave elimination exposure treatment on the chip photoresist coating and packaging layer to obtain a photoresist packaging standing wave elimination exposure image; performing development curing treatment and defect monitoring on the photoresist packaging standing wave elimination exposure image to obtain photoresist packaging development defect data; performing packaging defect improvement matching on the photoresist packaging development defect data to generate a photoresist packaging defect improvement strategy and perform corresponding photoresist packaging defect improvement operations. The present invention can realize an efficient photoresist packaging improvement process.

Description

Technical Field

[0001] The present invention relates to the technical field of photolithography manufacturing, and in particular to a method and system for improving photoresist packaging technology. Background Art

[0002] In the semiconductor packaging process, photoresist packaging is one of the key steps, which directly affects the accuracy and performance of the photolithography chip. The traditional photoresist packaging process has some problems, such as poor adhesion of the photoresist and uneven film formation, which affects the preparation quality of the photolithography chip. Summary of the invention

[0003] Based on this, it is necessary for the present invention to provide a method for improving the photoresist packaging process to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for improving a photoresist packaging process comprises the following steps:

[0005] Step S1: performing surface pretreatment on the surface of the photolithography chip to obtain a photolithography chip adhesion strengthening surface; performing hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface; performing multi-layer photoresist coating and packaging treatment on the photolithography chip adhesion hydrophobic surface to obtain a chip photoresist coating and packaging layer;

[0006] Step S2: performing mask imaging auxiliary alignment on the chip photoresist coating packaging layer to obtain a photoresist packaging mask alignment image; performing standing wave elimination exposure processing on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave elimination exposure image;

[0007] Step S3: performing development and curing processing on the photoresist package standing wave elimination exposure image to obtain a photoresist package development and curing image; performing defect monitoring on the photoresist package development and curing image to obtain photoresist package development defect data;

[0008] Step S4: performing packaging defect improvement matching on the photoresist packaging development defect data to generate a photoresist packaging defect improvement strategy; and executing corresponding photoresist packaging defect improvement operations according to the photoresist packaging defect improvement strategy.

[0009] The present invention firstly performs surface pretreatment on the surface of the photolithography chip, which can effectively remove the particles on the chip surface and ensure the cleanliness and quality of the surface. Through this step, it is ensured that the subsequent treatment is carried out on a clean basis, and the preparation quality of the photolithography chip is improved, thereby laying the foundation for the subsequent processing process. At the same time, by performing hydrophobic drying treatment on the adhesion strengthening surface of the photolithography chip, this treatment means can form hydrophobic properties on the surface, improve the moisture-proof and waterproof properties of the chip, and reduce the adhesion of dust and impurities at the same time, which helps to improve the service life and stability of the chip. By performing multi-layer photoresist coating and packaging treatment on the hydrophobic surface of the photolithography chip adhesion, necessary protection and support can be provided for the chip surface, and a stable and solid foundation is provided for subsequent processing. These steps are integrated, which not only improves the efficiency of surface treatment, but also ensures uniform film coating of photoresist and overall protection of the chip. Secondly, by using optical imaging technology to perform mask imaging auxiliary alignment on the chip photoresist coating and packaging layer, the application of this technology makes the alignment operation more accurate, provides accurate position information for subsequent process steps, and helps to ensure the accuracy and consistency of the entire packaging process. Subsequently, by performing standing wave elimination exposure processing on the photoresist package mask alignment image, the standing wave effect problem that occurs during the exposure process can be successfully eliminated, ensuring the clarity and consistency of the exposure image. The combined effect of these steps provides reliable support for imaging and alignment in the process, ensuring the precise execution of subsequent processing steps. Then, by developing and dissolving the photoresist package standing wave elimination exposure image, the redundant and unnecessary photoresist in the photoresist package standing wave elimination exposure image can be successfully removed, thereby forming a clear development image. This operation process can effectively eliminate unnecessary photoresist materials in the image area, thereby simplifying the image structure and improving the overall reliability and stability of the photolithography chip. In addition, by curing the image after development and dissolution, this step not only ensures the firm adhesion of the photoresist material, but also enhances the stability and durability of the image, providing a guarantee for the long-term use of the chip. Moreover, by performing defect monitoring on the photoresist package development and curing image, any defects or abnormalities in the photoresist package development and curing image can be comprehensively and accurately identified. This step provides important data for quality control of the production process, helping to timely discover and correct potential problems and ensure the quality and reliability of the final product. Finally, by matching the photoresist package development defect data with the package defect improvement, a photoresist package defect improvement strategy is generated. The key to this step is to generate targeted defect improvement strategies by analyzing and matching the data. In addition, based on these strategies, the corresponding photoresist package defect improvement operations can be performed, ultimately achieving rapid and effective defect repair and continuous process optimization, thereby improving the preparation quality of photolithography chips.

[0010] Preferably, the present invention further provides a system for improving a photoresist packaging process, which is used to perform the method for improving a photoresist packaging process as described above, and the system for improving a photoresist packaging process comprises:

[0011] The photolithography chip coating and packaging processing module is used to perform surface pretreatment on the surface of the photolithography chip to obtain a photolithography chip adhesion strengthening surface; perform hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface; perform multi-layer photoresist coating and packaging treatment on the photolithography chip adhesion hydrophobic surface to obtain a chip photoresist coating and packaging layer;

[0012] The photoresist mask exposure processing module is used to perform mask imaging auxiliary alignment on the chip photoresist coating packaging layer to obtain a photoresist packaging mask alignment image; perform standing wave elimination exposure processing on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave elimination exposure image;

[0013] The photoresist development defect monitoring module is used to perform development and curing processing on the photoresist package standing wave elimination exposure image to obtain a photoresist package development and curing image; and to perform defect monitoring on the photoresist package development and curing image to obtain photoresist package development defect data;

[0014] The photoresist package defect improvement module is used to perform package defect improvement processing on the photoresist package development and curing image based on the photoresist package development defect data to generate a photoresist package defect improvement strategy; and execute corresponding photoresist package defect improvement operations according to the photoresist package defect improvement strategy.

[0015] In summary, the present invention provides a system for improving a photoresist packaging process, the system for improving a photoresist packaging process comprises a photoresist chip coating and packaging processing module, a photoresist mask exposure processing module, a photoresist development defect monitoring module and a photoresist packaging defect improvement module, and can implement any one of the methods for improving a photoresist packaging process described in the present invention, and is used to combine the operations between computer programs running on each module to implement a method for improving a photoresist packaging process. The internal structures of the system cooperate with each other, and multi-layer packaging and mask design are introduced to improve the sensitivity of the photoresist to light, thereby achieving higher resolution and shorter exposure time. At the same time, the photoresist is accurately solidified through development and curing treatment to form a stable packaging layer. Defect monitoring is also used to ensure that any abnormal defects occurring during the development process can be discovered in a timely manner, providing key data support for subsequent improvements. By generating defect improvement strategies based on monitored defect data, the developer and curing image can be automatically adjusted to overcome existing defects. This proactive improvement strategy ensures process stability and product quality, and provides a guarantee for the quality of the final product of photoresist packaging. This can greatly reduce repetitive work and manpower investment, and can quickly and effectively provide a more accurate and efficient photoresist packaging process improvement process, thereby simplifying the operating procedures of the system for improving the photoresist packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments thereof made with reference to the following drawings:

[0017] Figure 1 A schematic flow chart of the steps of the method for improving the photoresist packaging process of the present invention;

[0018] Figure 2 for Figure 1 Detailed step flow diagram of step S1;

[0019] Figure 3 for Figure 2 Detailed step flow chart of step S15 in FIG. DETAILED DESCRIPTION

[0020] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0021] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0022] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0023] To achieve this, please refer to Figures 1 to 3 The present invention provides a method for improving a photoresist packaging process, the method comprising the following steps:

[0024] Step S1: performing surface pretreatment on the surface of the photolithography chip to obtain a photolithography chip adhesion strengthening surface; performing hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface; performing multi-layer photoresist coating and packaging treatment on the photolithography chip adhesion hydrophobic surface to obtain a chip photoresist coating and packaging layer;

[0025] Step S2: performing mask imaging auxiliary alignment on the chip photoresist coating packaging layer to obtain a photoresist packaging mask alignment image; performing standing wave elimination exposure processing on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave elimination exposure image;

[0026] Step S3: performing development and curing processing on the photoresist package standing wave elimination exposure image to obtain a photoresist package development and curing image; performing defect monitoring on the photoresist package development and curing image to obtain photoresist package development defect data;

[0027] Step S4: performing packaging defect improvement matching on the photoresist packaging development defect data to generate a photoresist packaging defect improvement strategy; and executing corresponding photoresist packaging defect improvement operations according to the photoresist packaging defect improvement strategy.

[0028] In the embodiment of the present invention, please refer to Figure 1FIG. 1 is a schematic flow chart of the steps of the method for improving the photoresist packaging process of the present invention. In this example, the steps of the method for improving the photoresist packaging process include:

[0029] Step S1: performing surface pretreatment on the surface of the photolithography chip to obtain a photolithography chip adhesion strengthening surface; performing hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface; performing multi-layer photoresist coating and packaging treatment on the photolithography chip adhesion hydrophobic surface to obtain a chip photoresist coating and packaging layer;

[0030] The embodiment of the present invention detects the surface of the photolithography chip by using professional impurity particle detection equipment (such as an optical microscope or a surface particle size analyzer) to detect and obtain the distribution information of the impurity particles, including the position, size, shape and other information of the impurity particles. At the same time, the impurity particles on the surface of the photolithography chip at the corresponding position are removed by selecting a suitable particle removal method (such as mechanical removal, solvent cleaning, etc.) to ensure that the impurity particles on the surface of the photolithography chip can be cleaned up, and activated by using surfactants and plasma treatment technology to enable it to have more active surface chemical properties, so as to improve the adhesion of the active surface of the photolithography chip at the microscopic level, making it more uniform and stable, thereby obtaining a photolithography chip adhesion strengthening surface. Then, the photolithography chip adhesion strengthening surface is treated by using a hydrophobic temperature controlled drying method to improve the hydrophobic performance of the photolithography chip adhesion strengthening surface, thereby obtaining a photolithography chip adhesion hydrophobic surface. Finally, by introducing a photoresist coater and configuring the corresponding photoresist coating film thickness control value, the photolithography chip adheres to the hydrophobic surface and performs multi-layer coating and packaging to protect and strengthen the chip surface and ensure that it is not easily affected by the external environment during use, and finally obtain the chip photoresist coating packaging layer.

[0031] Step S2: performing mask imaging auxiliary alignment on the chip photoresist coating packaging layer to obtain a photoresist packaging mask alignment image; performing standing wave elimination exposure processing on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave elimination exposure image;

[0032] The embodiment of the present invention performs connection processing on the chip photoresist-coated packaging layer by using a packaging cross-connection method to achieve cross-connection of the chip photoresist-coated packaging layer, so that different layers of photoresist can form a more solid and stable structure at the intersection, and performs imaging processing by using optical imaging technology (including a microscope or other optical imaging equipment), and uses an optically assisted alignment method during the imaging process to perform high-precision alignment of the chip photoresist packaging cross-connection structure and the mask to ensure accurate alignment and replication of the image, thereby obtaining a photoresist packaging mask alignment image. Secondly, the photoresist packaging mask alignment image is exposed by using exposure technology to improve the accuracy and resolution of the photoresist packaging mask alignment image. Then, during the exposure process, the exposure image is divided into non-exposure areas and exposure areas in the shape of a waveform through the standing wave effect, and the edge of the exposure area is adjusted for exposure to effectively solve the problem of uneven exposure of the photoresist caused by the standing wave effect. Finally, the non-exposure area and the exposure area after edge exposure adjustment are processed by using soft baking technology to effectively eliminate the standing wave effect in the image and improve the clarity and accuracy of the image, ultimately obtaining a photoresist packaging standing wave eliminated exposure image.

[0033] Step S3: performing development and curing processing on the photoresist package standing wave elimination exposure image to obtain a photoresist package development and curing image; performing defect monitoring on the photoresist package development and curing image to obtain photoresist package development defect data;

[0034] The embodiment of the present invention processes the photoresist package standing wave elimination exposure image by using threshold-based, edge detection or other computer vision technologies to identify and separate the position of unnecessary photoresist in the photoresist package standing wave elimination exposure image, and uses a photolithography developer to develop and dissolve the photoresist in the detected position area to dissolve and remove unnecessary photoresist materials in the area, and at the same time, the remaining photoresist is cured by a hard baking method to ensure that the remaining photoresist material can be firmly attached, thereby obtaining a photoresist package development and curing image. Finally, the photoresist package development and curing image is processed by using a defect monitoring method to extract defect data in the photoresist package development and curing image, including information data such as the location, size, and shape of the defect, and finally obtain photoresist package development defect data.

[0035] Step S4: performing packaging defect improvement matching on the photoresist packaging development defect data to generate a photoresist packaging defect improvement strategy; and executing corresponding photoresist packaging defect improvement operations according to the photoresist packaging defect improvement strategy.

[0036] The embodiment of the present invention performs pattern learning on the photoresist packaging development defect data by using a defect pattern learning method to obtain the defect pattern in the photoresist packaging development defect data, and classifies it by using an intelligent classification algorithm in machine learning, such as a support vector machine, a decision tree, or a deep learning neural network, so as to obtain defect type data. Secondly, a suitable photoresist packaging development defect improvement knowledge base is pre-set, which contains known defect types and their corresponding improvement strategies. Then, by matching the defect type data with the information in the photoresist packaging development defect improvement knowledge base, an applicable defect improvement strategy is found, thereby generating a photoresist packaging defect improvement strategy, including specific operating steps, parameter adjustment, etc. Finally, the corresponding photoresist packaging defect improvement operation is performed by using the generated photoresist packaging defect improvement strategy, including operations such as adjusting the photoresist packaging equipment and optimizing process parameters.

[0037] The present invention firstly performs surface pretreatment on the surface of the photolithography chip, which can effectively remove the particles on the chip surface and ensure the cleanliness and quality of the surface. Through this step, it is ensured that the subsequent treatment is carried out on a clean basis, and the preparation quality of the photolithography chip is improved, thereby laying the foundation for the subsequent processing process. At the same time, by performing hydrophobic drying treatment on the adhesion strengthening surface of the photolithography chip, this treatment means can form hydrophobic properties on the surface, improve the moisture-proof and waterproof properties of the chip, and reduce the adhesion of dust and impurities at the same time, which helps to improve the service life and stability of the chip. By performing multi-layer photoresist coating and packaging treatment on the hydrophobic surface of the photolithography chip adhesion, necessary protection and support can be provided for the chip surface, and a stable and solid foundation is provided for subsequent processing. These steps are integrated, which not only improves the efficiency of surface treatment, but also ensures uniform film coating of photoresist and overall protection of the chip. Secondly, by using optical imaging technology to perform mask imaging auxiliary alignment on the chip photoresist coating and packaging layer, the application of this technology makes the alignment operation more accurate, provides accurate position information for subsequent process steps, and helps to ensure the accuracy and consistency of the entire packaging process. Subsequently, by performing standing wave elimination exposure processing on the photoresist package mask alignment image, the standing wave effect problem that occurs during the exposure process can be successfully eliminated, ensuring the clarity and consistency of the exposure image. The combined effect of these steps provides reliable support for imaging and alignment in the process, ensuring the precise execution of subsequent processing steps. Then, by developing and dissolving the photoresist package standing wave elimination exposure image, the redundant and unnecessary photoresist in the photoresist package standing wave elimination exposure image can be successfully removed, thereby forming a clear development image. This operation process can effectively eliminate unnecessary photoresist materials in the image area, thereby simplifying the image structure and improving the overall reliability and stability of the photolithography chip. In addition, by curing the image after development and dissolution, this step not only ensures the firm adhesion of the photoresist material, but also enhances the stability and durability of the image, providing a guarantee for the long-term use of the chip. Moreover, by performing defect monitoring on the photoresist package development and curing image, any defects or abnormalities in the photoresist package development and curing image can be comprehensively and accurately identified. This step provides important data for quality control of the production process, helping to timely discover and correct potential problems and ensure the quality and reliability of the final product. Finally, by matching the photoresist package development defect data with the package defect improvement, a photoresist package defect improvement strategy is generated. The key to this step is to generate targeted defect improvement strategies by analyzing and matching the data. In addition, based on these strategies, the corresponding photoresist package defect improvement operations can be performed, ultimately achieving rapid and effective defect repair and continuous process optimization, thereby improving the preparation quality of photolithography chips.

[0038] Preferably, step S1 comprises the following steps:

[0039] Step S11: Detect impurity particles on the surface of the photolithography chip to obtain the distribution information of impurity particles on the chip surface;

[0040] Step S12: performing particle removal processing on the surface of the photolithography chip according to the distribution information of impurity particles on the chip surface to obtain a particle-removed surface of the photolithography chip;

[0041] Step S13: using a surfactant to perform an activation treatment on the particle-removed surface of the photolithography chip to obtain an active surface of the photolithography chip;

[0042] Step S14: using plasma treatment technology to perform uniform adhesion strengthening treatment on the active surface of the photolithography chip to obtain an adhesion strengthening surface of the photolithography chip;

[0043] Step S15: performing a hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface;

[0044] Step S16: performing a multi-layer photoresist coating and packaging process on the hydrophobic surface of the photolithography chip to obtain a chip photoresist coating and packaging layer.

[0045] As an embodiment of the present invention, refer to Figure 2 As shown, Figure 1 Detailed step flow diagram of step S1 in FIG. 1 , in this embodiment, step S1 includes the following steps:

[0046] Step S11: Detect impurity particles on the surface of the photolithography chip to obtain the distribution information of impurity particles on the chip surface;

[0047] The embodiment of the present invention uses professional impurity particle detection equipment (such as an optical microscope or a surface particle size analyzer) to detect the surface of the photolithography chip to detect and obtain the distribution information of the impurity particles, including the position, size, shape and other information of the impurity particles, and finally obtains the impurity particle distribution information on the chip surface.

[0048] Step S12: performing particle removal processing on the surface of the photolithography chip according to the distribution information of impurity particles on the chip surface to obtain a particle-removed surface of the photolithography chip;

[0049] The embodiment of the present invention removes impurity particles on the surface of the photolithography chip at the corresponding position by selecting a suitable particle removal method (such as mechanical removal, solvent cleaning, etc.) according to the distribution information of the impurity particles on the chip surface, so as to ensure that the impurity particles on the surface of the photolithography chip can be completely removed, and finally obtain a photolithography chip particle-free surface.

[0050] Step S13: using a surfactant to perform an activation treatment on the particle-removed surface of the photolithography chip to obtain an active surface of the photolithography chip;

[0051] The embodiment of the present invention activates the surface of the photolithography chip particles by using a surfactant, so that the surface has more active surface chemical properties, and improves the affinity and responsiveness of the photolithography chip surface, and finally obtains the active surface of the photolithography chip.

[0052] Step S14: using plasma treatment technology to perform uniform adhesion strengthening treatment on the active surface of the photolithography chip to obtain an adhesion strengthening surface of the photolithography chip;

[0053] The embodiment of the present invention uses plasma processing technology to process the active surface of the lithography chip to improve the adhesion of the active surface of the lithography chip at a microscopic level, making it more uniform and stable, and finally obtaining an adhesion-enhanced surface of the lithography chip.

[0054] Step S15: performing a hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface;

[0055] The embodiment of the present invention processes the adhesion strengthening surface of the lithography chip by using a hydrophobic temperature controlled drying method to enhance the hydrophobicity of the adhesion strengthening surface of the lithography chip, and improve the moisture-proof and waterproof properties of the adhesion strengthening surface of the lithography chip, while reducing the adhesion of dust and impurities, and finally obtaining a hydrophobic adhesion surface for the lithography chip.

[0056] Step S16: performing a multi-layer photoresist coating and packaging process on the hydrophobic surface of the photolithography chip to obtain a chip photoresist coating and packaging layer.

[0057] The embodiment of the present invention introduces a photoresist coater and configures corresponding photoresist coating film thickness control values ​​to perform multi-layer coating and packaging on the hydrophobic surface of the photolithography chip to protect and reinforce the chip surface and ensure that it is not easily affected by the external environment during use, and finally obtains a chip photoresist coating and packaging layer.

[0058] The present invention firstly detects impurity particles on the surface of the photolithography chip, and can obtain detailed information about the distribution of impurity particles on the chip surface. This process helps to discover and record the distribution of particles on the chip surface, and provides accurate basic data for subsequent processing steps. Through this step, the goal and direction of subsequent processing are ensured. At the same time, by performing particle removal treatment on the surface of the photolithography chip according to the distribution information of impurity particles on the chip surface, this treatment method can effectively remove particles on the chip surface and ensure the cleanliness and quality of the surface. Through this step, it is ensured that the subsequent processing is carried out on a clean basis, and the preparation quality of the photolithography chip is improved. Secondly, by using a surfactant to perform active activation treatment on the particle removal surface of the photolithography chip, this treatment method can enhance the activity of the surface of the photolithography chip, improve the affinity and responsiveness of the surface of the photolithography chip, and lay the foundation for subsequent processing. The formation of the active surface makes the subsequent processing more accurate and efficient. Then, by using plasma treatment technology to perform adhesion uniform strengthening treatment on the active surface of the photolithography chip, this technology can improve the surface adhesion at the microscopic level, making it more uniform and stable, thereby improving the adhesion strength and stability of the photolithography chip. This step ensures the reliability and durability of the photolithography chip in subsequent use. Next, the photolithography chip adhesion strengthening surface is subjected to a hydrophobic drying treatment. This treatment method can make the surface hydrophobic, improve the moisture and water resistance of the chip, and reduce the adhesion of dust and impurities, which helps to improve the service life and stability of the chip. Finally, the photolithography chip is subjected to a multi-layer photoresist coating and packaging treatment on the hydrophobic surface. This step is to protect and strengthen the chip surface and ensure that it is not easily affected by the external environment during use. The multi-layer coating and packaging treatment can improve the stability and reliability of the chip, thereby meeting the various needs of the photolithography chip in practical applications.

[0059] Preferably, step S15 comprises the following steps:

[0060] Step S151: using a surface hydrophilicity calculation formula to calculate the hydrophilicity of the photolithography chip adhesion strengthening surface to obtain a hydrophilicity value of the photolithography chip surface;

[0061] Step S152: comparing and judging the surface hydrophilicity value of the photolithography chip according to a preset surface hydrophilicity threshold value, when the surface hydrophilicity value of the photolithography chip is greater than or equal to the preset surface hydrophilicity threshold value, the photolithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the photolithography chip is determined as the photolithography chip hydrophilic surface; when the surface hydrophilicity value of the photolithography chip is less than the preset surface hydrophilicity threshold value, the photolithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the photolithography chip is determined as the photolithography chip hydrophobic surface;

[0062] Step S153: when it is determined that the adhesion strengthening surface of the lithography chip is the hydrophilic surface of the lithography chip, the hydrophilic surface of the lithography chip is divided into a heating range to obtain a low temperature range, a medium temperature range and a high temperature range; when the heating range is in the low temperature range, the hydrophilic surface of the lithography chip is subjected to a low temperature evaporation treatment to obtain a hydrophilic low temperature evaporation area of ​​the chip; when the heating range is in the medium temperature range, the hydrophilic low temperature evaporation area of ​​the chip is subjected to a medium temperature molecule removal treatment to obtain a hydrophilic medium temperature molecule removal area of ​​the chip; when the heating range is in the high temperature range, the hydrophilic medium temperature molecule removal area of ​​the chip is subjected to a high temperature drying treatment to obtain a hydrophilic high temperature hydrophobic recovery area of ​​the chip;

[0063] Step S154: when it is determined that the adhesion strengthening surface of the photolithography chip is the hydrophobic surface of the photolithography chip, the hydrophobic surface of the photolithography chip is subjected to an adhesion-increasing and drying treatment to obtain a hydrophobic adhesion-increasing and hydrophobic recovery area of ​​the chip;

[0064] Step S155: Merge the chip hydrophilic high temperature hydrophobic recovery area and the chip hydrophobic viscosity increased hydrophobic recovery area to obtain a photolithography chip adhesion hydrophobic surface.

[0065] As an embodiment of the present invention, refer to Figure 3 As shown, Figure 2 Detailed step flow diagram of step S15 in FIG. 1 , in this embodiment, step S15 includes the following steps:

[0066] Step S151: using a surface hydrophilicity calculation formula to calculate the hydrophilicity of the photolithography chip adhesion strengthening surface to obtain a hydrophilicity value of the photolithography chip surface;

[0067] The embodiment of the present invention combines surface area parameters, surface area range parameters, spatial coordinate parameters, surface tension parameters, gradient operators, hydrophilic influence measurement parameters, temperature parameters, temperature attenuation coefficients, surface medium distribution range parameters, surface medium distribution position parameters, surface medium distribution functions, surface medium distribution normalization coefficients, surface medium distribution mean values, surface medium distribution standard deviations, and related parameters to form a suitable surface hydrophilicity calculation formula to calculate the hydrophilicity of the photolithography chip adhesion strengthening surface, so as to quantify the physicochemical properties of the photolithography chip adhesion strengthening surface, and finally obtain the photolithography chip surface hydrophilicity value. In addition, the surface hydrophilicity calculation formula can also use any hydrophilicity detection algorithm in the art to replace the hydrophilicity calculation process, and is not limited to the surface hydrophilicity calculation formula.

[0068] Step S152: comparing and judging the surface hydrophilicity value of the photolithography chip according to a preset surface hydrophilicity threshold value, when the surface hydrophilicity value of the photolithography chip is greater than or equal to the preset surface hydrophilicity threshold value, the photolithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the photolithography chip is determined as the photolithography chip hydrophilic surface; when the surface hydrophilicity value of the photolithography chip is less than the preset surface hydrophilicity threshold value, the photolithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the photolithography chip is determined as the photolithography chip hydrophobic surface;

[0069] The embodiment of the present invention compares and judges the calculated surface hydrophilicity value of the lithography chip by using a preset surface hydrophilicity threshold value. If the surface hydrophilicity value of the lithography chip is greater than or equal to the preset surface hydrophilicity threshold value, it means that the hydrophilicity of the lithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the lithography chip is stronger, and the lithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the lithography chip is judged as the hydrophilic surface of the lithography chip; if the surface hydrophilicity value of the lithography chip is less than the preset surface hydrophilicity threshold value, it means that the hydrophilicity of the lithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the lithography chip is weak or non-existent, and the lithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the lithography chip is judged as the hydrophobic surface of the lithography chip.

[0070] Step S153: when it is determined that the adhesion strengthening surface of the lithography chip is the hydrophilic surface of the lithography chip, the hydrophilic surface of the lithography chip is divided into a heating range to obtain a low temperature range, a medium temperature range and a high temperature range; when the heating range is in the low temperature range, the hydrophilic surface of the lithography chip is subjected to a low temperature evaporation treatment to obtain a hydrophilic low temperature evaporation area of ​​the chip; when the heating range is in the medium temperature range, the hydrophilic low temperature evaporation area of ​​the chip is subjected to a medium temperature molecule removal treatment to obtain a hydrophilic medium temperature molecule removal area of ​​the chip; when the heating range is in the high temperature range, the hydrophilic medium temperature molecule removal area of ​​the chip is subjected to a high temperature drying treatment to obtain a hydrophilic high temperature hydrophobic recovery area of ​​the chip;

[0071] The embodiment of the present invention determines that the corresponding photolithography chip adhesion strengthening surface is the hydrophilic surface of the photolithography chip, then heats the hydrophilic surface of the photolithography chip, and divides the heating range according to the heating effect, thereby obtaining a low temperature range (150°C-200°C), a medium temperature range (201°C-400°C) and a high temperature range (over 750°C). Then, when the heating range is within the low temperature range, the water in the hydrophilic surface of the photolithography chip is evaporated at low temperature, thereby obtaining a chip hydrophilic low temperature evaporation area; when the heating range is within the medium temperature range, the water molecules in the hydrophilic low temperature evaporation area of ​​the chip that are loosely bound to the surface are removed at medium temperature, thereby obtaining a chip hydrophilic medium temperature molecule removal area; when the heating range is within the high temperature range, the chip hydrophilic medium temperature molecule removal area is dried at high temperature, so that the chip surface in the area can be restored to a hydrophobic condition in terms of chemical properties, thereby obtaining a chip hydrophilic high temperature hydrophobic recovery area.

[0072] Step S154: when it is determined that the adhesion strengthening surface of the photolithography chip is the hydrophobic surface of the photolithography chip, the hydrophobic surface of the photolithography chip is subjected to an adhesion-increasing and drying treatment to obtain a hydrophobic adhesion-increasing and hydrophobic recovery area of ​​the chip;

[0073] In the embodiment of the present invention, when it is determined that the corresponding adhesion strengthening surface of the lithography chip is the hydrophobic surface of the lithography chip, the hydrophobic surface of the lithography chip is thickened by using a thickener, so that the hydrophobic surface of the lithography chip can be more easily bonded with the photoresist, and the chip surface after thickening is dried to finally obtain a chip hydrophobic thickening and hydrophobic recovery area.

[0074] Step S155: Merge the chip hydrophilic high temperature hydrophobic recovery area and the chip hydrophobic viscosity increased hydrophobic recovery area to obtain a photolithography chip adhesion hydrophobic surface.

[0075] The embodiment of the present invention uses the region merging technology to merge the chip hydrophilic high temperature hydrophobic recovery area and the chip hydrophobic viscosity hydrophobic recovery area obtained by different hydrophobic treatment methods, so as to merge the treatment effects of different areas and finally obtain the photolithography chip adhesion hydrophobic surface.

[0076] The present invention first calculates the hydrophilicity of the adhesion strengthening surface of the lithography chip by using a surface hydrophilicity calculation formula. This calculation process utilizes an advanced hydrophilicity evaluation method and comprehensively considers the physical and chemical properties of the surface to obtain an accurate surface hydrophilicity value, providing a reliable data basis for subsequent decision-making. Secondly, by using a pre-set surface hydrophilicity threshold to compare and judge the surface hydrophilicity value of the lithography chip, an intelligent judgment of the surface hydrophilicity value of the lithography chip can be achieved. When the surface hydrophilicity value of the lithography chip is greater than or equal to the surface hydrophilicity threshold, the surface is judged as a hydrophilic surface of the lithography chip, otherwise it is judged as a hydrophobic surface of the lithography chip. This judgment mechanism can provide a clear classification basis for subsequent processing decisions through comparison. Then, the strategy for dividing the heating range for the hydrophilic surface of the lithography chip divides the heating process into three ranges: low temperature, medium temperature and high temperature. By performing evaporation at low temperature, molecular removal at medium temperature, and drying at high temperature, this multi-stage treatment method effectively utilizes the change in temperature, realizes the fine treatment of the hydrophilic surface, and obtains the property adjustment of different regions, thereby improving the stability and performance of the surface. Next, when the surface of the photolithography chip is judged to be a hydrophobic surface, the hydrophobic surface of the photolithography chip is subjected to a viscosity-enhancing and drying treatment. This step aims to change the surface properties and make it hydrophobic. By adding a thickener and drying treatment, the properties of the hydrophobic surface are adjusted, laying the foundation for the subsequent formation of a hydrophobic surface. Finally, by merging the hydrophilic high-temperature hydrophobic recovery area of ​​the chip and the hydrophobic viscosity-enhancing and hydrophobic recovery area of ​​the chip, this step aims to comprehensively consider the results of different treatment methods and obtain the final photolithography chip adhesion hydrophobic surface. By merging the treatment effects of different regions, the comprehensive regulation of the surface properties of the photolithography chip can be effectively achieved to meet the needs of different application scenarios. Overall, this process provides a comprehensive and flexible solution for the performance improvement and customized processing of photolithography chips.

[0077] Preferably, the surface hydrophilicity calculation formula in step S151 is specifically:

[0078] ;

[0079] ;

[0080] In the formula, is the hydrophilicity value of the photolithography chip surface, is the surface area parameter of the photolithography chip adhesion strengthening surface, is the surface area range parameter of the photolithography chip adhesion strengthening surface, is the spatial coordinate parameter of the photolithography chip adhesion strengthening surface, Strengthening surfaces for photolithographic chip adhesion in spatial coordinates The surface tension parameter at is the gradient operator, is the hydrophilicity influence measurement parameter of the surface tension gradient term, is the hydrophilicity effect measurement parameter of surface tension curvature, is the temperature parameter of the photolithography chip adhesion strengthening surface, is the temperature attenuation coefficient, is the hydrophilicity influence measurement parameter of the temperature attenuation term, is the surface medium distribution range parameter of the photolithography chip adhesion strengthening surface, is the surface medium distribution position parameter of the photolithography chip adhesion strengthening surface, is the surface medium distribution function, is the surface medium distribution normalization coefficient, is the mean value of the surface medium distribution, is the standard deviation of the surface medium distribution, It is the correction value of the hydrophilicity value of the photolithography chip surface.

[0081] The present invention constructs a surface hydrophilicity calculation formula for calculating the hydrophilicity of a photolithography chip adhesion strengthening surface. The surface hydrophilicity calculation formula represents the total area of ​​the photolithography chip adhesion strengthening surface through a surface area parameter, describes the geometric shape and range of the photolithography chip adhesion strengthening surface through a surface area range parameter, represents the position on the surface through a spatial coordinate parameter, describes the distribution of the surface tension through a surface tension parameter, calculates the gradient of the surface tension by using a gradient operator, represents the influence of the gradient on the hydrophilicity through a hydrophilicity influence measurement parameter of a surface tension gradient term, represents the influence of the curvature on the hydrophilicity through a hydrophilicity influence measurement parameter of a surface tension curvature, and represents the influence of the photolithography chip adhesion strengthening surface through a surface area parameter. The temperature parameters of the enhanced surface are used to affect the effect of temperature on hydrophilicity. The temperature attenuation coefficient is used to represent the temperature attenuation rate. The hydrophilic influence measurement parameter of the temperature attenuation term is used to represent the degree of influence of temperature on hydrophilicity. The surface medium distribution range parameter is used to describe the distribution range of the surface medium. The surface medium distribution position parameter is used to represent the distribution position of the medium on the surface. The surface medium distribution function is used to describe the distribution of the medium on the surface. At the same time, the surface medium distribution normalization coefficient is used to normalize the medium distribution function. In addition, the surface medium distribution mean is used to represent the center position of the medium distribution, and the surface medium distribution standard deviation is used to represent the discrete degree of the medium distribution. Subsequently, the overall hydrophilicity calculation result is adjusted by introducing a correction value, so that the formula calculates the hydrophilicity of the surface by comprehensively considering multiple factors such as surface tension, temperature, and medium distribution. In summary, this formula fully takes into account the hydrophilicity value of the photolithography chip surface. , Surface area parameters of photolithography chip adhesion strengthening surface , Surface area range parameters for photolithography chip adhesion strengthening surfaces , spatial coordinate parameters of the photolithography chip adhesion strengthening surface , the photolithography chip adhesion strengthening surface in the spatial coordinates Surface tension parameters at , the gradient operator , the hydrophilicity effect measurement parameter of the surface tension gradient term , a measure of the hydrophilicity effect of surface tension curvature , Temperature parameters for photolithography chip adhesion strengthening surface , Temperature attenuation coefficient , the hydrophilicity influence measurement parameter of the temperature attenuation term , Surface dielectric distribution range parameters of photolithography chip adhesion strengthening surface , Surface dielectric distribution position parameters of photolithography chip adhesion strengthening surface , surface medium distribution function , surface medium distribution normalization coefficient , surface medium distribution mean , surface medium distribution standard deviation , Correction value of hydrophilicity of photolithography chip surface , where the surface medium distribution position parameter of the photolithographic chip adhesion strengthening surface is , surface medium distribution normalization coefficient , surface medium distribution mean and the standard deviation of the surface medium distribution A surface medium distribution function Functional Relationship , according to the hydrophilicity value of the photolithography chip surface The correlation between the above parameters forms a functional relationship:

[0082] ;

[0083] This formula can realize the hydrophilic calculation process of the photolithography chip adhesion strengthening surface. At the same time, the correction value of the hydrophilicity value of the photolithography chip surface is The introduction of can be adjusted according to the errors occurring in the calculation process, thereby improving the accuracy and applicability of the surface hydrophilicity calculation formula.

[0084] Preferably, step S16 comprises the following steps:

[0085] Step S161: using chemical modification technology to control the wettability of the hydrophobic surface to which the photolithography chip is adhered, so as to obtain a wettability-modified surface of the photolithography chip;

[0086] The embodiment of the present invention uses chemical modification technology (such as chemical modifier) ​​to treat the hydrophobic surface of the photolithography chip to change the adhesion and hydrophobic properties of the surface of the photolithography chip, and controls the time, temperature and other parameters of the chemical modification to achieve wetting modification control of the hydrophobic surface of the photolithography chip, effectively adjust the properties of the hydrophobic surface of the photolithography chip to finally obtain a wetting modified surface of the photolithography chip.

[0087] Step S162: introducing a photoresist coating machine and performing film thickness control calculation on the photoresist coating machine using a coating film thickness control calculation formula to obtain a photoresist coating film thickness control value;

[0088] The embodiment of the present invention introduces a photoresist coating machine, and then, by combining the time variable parameter of the film thickness control calculation, the initial coating film thickness parameter of the photoresist coating machine, the coating speed control parameter, the coating time attenuation coefficient, the coating frequency oscillation parameter, the coating time Gaussian distribution amplitude parameter, the coating time Gaussian distribution mean, the coating time Gaussian distribution standard deviation and related parameters, a suitable coating film thickness control calculation formula is formed to perform film thickness control calculation on the photoresist coating machine to control the coating film thickness of the photoresist coating machine, and finally obtain the photoresist coating film thickness control value. In addition, the coating film thickness control calculation formula can also use any coating control algorithm in the art to replace the process of film thickness control calculation, and is not limited to the coating film thickness control calculation formula.

[0089] Among them, the calculation formula for controlling the coating film thickness is as follows:

[0090] ;

[0091] In the formula, For in time The photoresist coating film thickness control value at Time variable parameters calculated for film thickness control, The time-integrated variable parameter calculated for film thickness control, is the initial coating film thickness parameter of the photoresist coater, is the coating speed control parameter of the photoresist coater, is the coating time attenuation coefficient of the photoresist coater, is the coating frequency oscillation parameter of the photoresist coater, is the Gaussian distribution amplitude parameter of the photoresist coater coating time, is the mean value of the Gaussian distribution of the coating time of the photoresist coater, is the standard deviation of the Gaussian distribution of the photoresist coating time, is the correction value of the photoresist coating film thickness control value;

[0092] The present invention constructs a coating film thickness control calculation formula for performing film thickness control calculation on a photoresist coating machine. The coating film thickness control calculation formula uses a time variable parameter to represent a specific moment in the coating process, uses a time integral variable parameter to represent the integral time in the coating process, and is used to calculate the cumulative effect in the coating process. The initial coating film thickness parameter is used to represent the film thickness at the beginning of coating, and the coating speed of the coating machine is represented by a coating speed control parameter, thereby affecting the coating speed. The coating time attenuation coefficient is used to represent the attenuation degree of the coating speed over time. , the frequency oscillation of the coating machine is represented by the coating frequency oscillation parameter, the amplitude of the coating time distribution is represented by the coating time Gaussian distribution amplitude parameter, the mean position of the time distribution is represented by the coating time Gaussian distribution mean, and the discrete degree of the time distribution is represented by the coating time Gaussian distribution standard deviation. The overall effect of the calculation formula is to control the coating parameters of the photoresist coater to form a photoresist layer with a specific film thickness distribution on the surface of the photolithography chip. This control is to meet specific process requirements and ensure that the required photolithography pattern is obtained when manufacturing the chip. Among them, the dynamic behavior of the coating process is affected by using parameters such as coating speed control parameters, coating time attenuation coefficient, coating frequency oscillation parameters, and time Gaussian distribution amplitude parameters, including speed changes, frequency oscillations, and the shape of the time distribution. The shape of the time distribution during the coating process is affected by using the time Gaussian distribution mean and standard deviation, so as to adjust the uniformity and consistency of the film. The purpose of the entire formula is to accurately control the film thickness during the photoresist coating process to ensure that the photoresist forms the required pattern on the chip surface, thereby achieving accurate processing of the chip. In summary, the formula fully takes into account the time Photoresist coating thickness control value at , time variable parameter for film thickness control calculation , time-integrated variable parameter for film thickness control calculation , the initial coating film thickness parameters of the photoresist coater , coating speed control parameters of photoresist coater , the coating time attenuation coefficient of the photoresist coater , the coating frequency oscillation parameters of the photoresist coater , the amplitude parameter of the Gaussian distribution of the coating time of the photoresist coater , the mean of the Gaussian distribution of the coating time of the photoresist coater , the standard deviation of the Gaussian distribution of the coating time of the photoresist coater , correction value of photoresist coating film thickness control value , according to the time Photoresist coating thickness control value at The correlation between the above parameters constitutes a functional relationship This formula can realize the film thickness control calculation process of the photoresist coater. At the same time, the correction value of the photoresist coating film thickness control value The introduction of can be adjusted according to the error conditions that occur during the calculation process, thereby improving the accuracy and applicability of the calculation formula for coating film thickness control.

[0093] Step S163: Based on the photoresist coating film thickness control value, a photoresist coater is used to perform a multi-layer photoresist coating and packaging process on the wet modified surface of the photolithography chip to obtain a chip photoresist coating and packaging layer.

[0094] The embodiment of the present invention applies the calculated photoresist coating film thickness control value to the photoresist coater, and ensures that the photoresist can be evenly coated on the wet modified surface of the photolithography chip according to the film thickness. Then, multiple coating and packaging operations are performed to achieve layer-by-layer coating and superposition of the wet modified surface of the photolithography chip, gradually forming a packaging layer, and finally obtaining a chip photoresist coating and packaging layer.

[0095] The present invention firstly controls the wet modification of the hydrophobic surface of the photolithography chip adhesion by using chemical modification technology, and can realize the wet modification control of the hydrophobic surface of the photolithography chip adhesion. The application of this technology can effectively adjust the surface properties so that it has better wettability, and provides a good basis for subsequent process treatment. Through this modification, the surface of the photolithography chip can better adapt to different processing environments, thereby improving coating performance and processability. Secondly, by introducing a photoresist coater and combining a film thickness control calculation formula, it is possible to realize a highly accurate control of the photoresist film thickness. The introduction of this technology can effectively eliminate the uncertainty in the production process, and the photoresist coating film thickness control value is accurately calculated by a calculation formula, ensuring the consistency and stability of each coating. Such accurate control provides a reliable parameter basis for subsequent processes, thereby enhancing the repeatability and production efficiency of the product. Finally, the photoresist coating machine uses the calculated photoresist coating film thickness control value to perform multi-layer photoresist coating and packaging on the wet modified surface of the photolithography chip. This step can realize the layer-by-layer superposition of the chip surface according to the photoresist coating film thickness control value, thereby forming a multi-layer photoresist coating and packaging layer. This multi-level coating and packaging not only effectively protects the chip surface, but also provides more process options to meet the flexible requirements of different application scenarios for photolithography chip performance and protective layer requirements.

[0096] Preferably, step S2 comprises the following steps:

[0097] Step S21: performing encapsulation cross-connection on the chip photoresist coating encapsulation layer to obtain a chip photoresist encapsulation cross-connection structure;

[0098] The embodiment of the present invention performs connection processing on the chip photoresist coated packaging layer by using a packaging cross-connection method to achieve cross-connection of the chip photoresist coated packaging layer, so that different layers of photoresist can form a more firm and stable structure at the intersection, thereby improving the adhesion strength between different packaging layers, and finally obtaining a chip photoresist packaging cross-connection structure.

[0099] Step S22: using optical imaging technology to perform mask imaging auxiliary alignment on the chip photoresist package cross-connection structure to obtain a photoresist package mask alignment image;

[0100] The embodiment of the present invention uses optical imaging technology (including a microscope or other optical imaging equipment) to image the chip photoresist package cross-connection structure, and uses an optically assisted alignment method to perform high-precision alignment of the chip photoresist package cross-connection structure and the mask during the imaging process to ensure accurate alignment and replication of the image, and finally obtain a photoresist package mask alignment image.

[0101] Step S23: performing standing wave effect exposure division on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave non-exposure image area and a photoresist packaging standing wave exposure image area;

[0102] The embodiment of the present invention uses exposure technology to expose the photoresist packaging mask alignment image to improve the accuracy and resolution of the photoresist packaging mask alignment image. Then, during the exposure process, the exposure image is divided into non-exposure areas and exposure areas by the standing wave effect in the shape of a waveform, and finally a photoresist packaging standing wave non-exposure image area and a photoresist packaging standing wave exposure image area are obtained.

[0103] Step S24: performing edge exposure adjustment on the photoresist package standing wave exposure image area to obtain a photoresist package standing wave exposure edge adjustment area;

[0104] The embodiment of the present invention uses edge exposure technology to adjust the exposure of the divided photoresist package standing wave exposure image area, so as to effectively solve the problem of uneven photoresist exposure caused by the standing wave effect, ensure that the exposure of the entire photoresist edge area can be clearer, and finally obtain the photoresist package standing wave exposure edge adjustment area.

[0105] Step S25: performing standing wave elimination soft baking treatment on the photoresist package standing wave non-exposure image area and the photoresist package standing wave exposure edge adjustment area to obtain a photoresist package standing wave elimination exposure image.

[0106] The embodiment of the present invention processes the photoresist package standing wave non-exposure image area and the photoresist package standing wave exposure edge adjustment area by using soft baking technology to effectively eliminate the standing wave effect in the image and improve the clarity and accuracy of the image, and finally obtain a photoresist package standing wave eliminated exposure image.

[0107] The present invention firstly forms a chip photoresist encapsulation cross-connection structure by encapsulating the chip photoresist coating encapsulation layer. The main effect of this step is to realize the cross-connection of the chip encapsulation, which provides a basis for the integration of subsequent electronic components. Through precise process control, the reliability and stability of the cross-connection are ensured, thereby improving the overall performance and reliability of the chip. Secondly, by using optical imaging technology to perform mask imaging auxiliary alignment on the chip photoresist encapsulation cross-connection structure, the application of this technology makes the alignment operation more accurate, provides accurate position information for subsequent process steps, and helps to ensure the accuracy and consistency of the entire encapsulation process. Then, by performing standing wave effect exposure division on the photoresist encapsulation mask alignment image, the photoresist encapsulation standing wave non-exposure image area and the photoresist encapsulation standing wave exposure image area can be successfully obtained. In this way, different exposure processing methods can be adopted for different regions, thereby achieving more refined pattern formation and processing effects. Such a division strategy effectively copes with the influence of the standing wave effect on image quality and improves the controllability and stability of processing. Next, by adjusting the edge exposure of the photoresist package standing wave exposure image area, a photoresist package standing wave exposure edge adjustment area is formed. This adjustment measure can effectively solve the problem of uneven exposure of the photoresist caused by the standing wave effect, and ensure the consistency of the entire photoresist edge area. Through the edge exposure adjustment, the photoresist edge area can be clearer, thereby improving the photoresist package processing quality. Finally, by performing standing wave elimination soft baking treatment on the standing wave non-exposure image area and the standing wave exposure edge adjustment area, this processing step can effectively eliminate the standing wave effect through soft baking, and improve the clarity and accuracy of the image. By combining these steps, high-precision processing of chip photoresist packaging can be successfully achieved, providing a reliable pattern formation basis for chip manufacturing.

[0108] Preferably, step S3 comprises the following steps:

[0109] Step S31: performing non-essential area detection on the photoresist package standing wave elimination exposure image to obtain the photoresist non-essential image area;

[0110] The embodiment of the present invention processes the photoresist package standing wave elimination exposure image by using threshold-based, edge detection or other computer vision technologies to identify and separate the position of non-essential photoresist in the photoresist package standing wave elimination exposure image, and finally obtains the photoresist non-essential image area.

[0111] Step S32: developing and dissolving the photoresist in the non-essential image area of ​​the photoresist by using a photolithography developer to obtain a non-essential developed and dissolved image of the photoresist;

[0112] The embodiment of the present invention develops and dissolves the photoresist in the detected non-essential image area of ​​the photoresist using a photolithography developer to dissolve and remove unnecessary photoresist materials in the non-essential image area of ​​the photoresist, thereby forming a clear development image and finally obtaining a photoresist non-essential development and dissolution image.

[0113] Step S33: performing hard baking and curing treatment on the photoresist non-essential development and dissolution image to obtain a photoresist package development and curing image;

[0114] The embodiment of the present invention uses a hard baking method to cure the photoresist remaining in the photoresist non-essential development and dissolution image to ensure that the photoresist material in the photoresist non-essential development and dissolution image can be firmly adhered, and finally a photoresist encapsulation development and curing image is obtained.

[0115] Step S34: performing image denoising processing on the photoresist package development and curing image to obtain a photoresist package development denoised image;

[0116] The embodiment of the present invention processes the cured photoresist package development and curing image by using an image denoising algorithm (for example, based on a filter or other image processing technology) to effectively reduce the noise level in the photoresist package development and curing image, and finally obtains a photoresist package development denoised image.

[0117] Step S35: performing contrast enhancement processing on the photoresist package development denoised image to obtain a photoresist package development contrast standard image;

[0118] The embodiment of the present invention processes the photoresist package development denoised image by using a contrast enhancement algorithm (such as histogram equalization or other enhancement techniques) to further improve the contrast of the photoresist package development denoised image, and enhance the details in the photoresist package development denoised image, and finally obtain a photoresist package development contrast standard image.

[0119] Step S36: performing defect monitoring on the photoresist package development contrast standard image to obtain photoresist package development defect data.

[0120] The embodiment of the present invention processes the photoresist package development contrast standard image by using a defect monitoring method to extract defect data in the photoresist package development contrast standard image, including information data such as the location, size, shape, etc. of the defect, and finally obtains the photoresist package development defect data.

[0121] The present invention firstly detects the non-essential area of ​​the photoresist package standing wave elimination exposure image, and can accurately identify and separate the non-essential area of ​​the photoresist in the photoresist package standing wave elimination exposure image. The key of this step is to effectively distinguish the main structure and the non-essential elements of the photoresist in the image, and provide a clear target for subsequent processing. In this way, it is possible to focus on processing key areas and improve processing efficiency. At the same time, by using a photolithography developer to carry out a development and dissolution process on the photoresist in the non-essential image area of ​​the photoresist, the redundant photoresist in the non-essential image area of ​​the photoresist can be successfully removed, thereby forming a clear non-essential development and dissolution image of the photoresist. This operation effectively eliminates unnecessary photoresist materials in the region, thereby simplifying the image structure and improving the overall reliability and stability of the photolithography chip. Secondly, by carrying out a hard baking and curing process on the non-essential development and dissolution image of the photoresist, this step not only ensures the firm adhesion of the photoresist material, but also enhances the stability and durability of the image, and provides a guarantee for the long-term use of the chip. Then, by performing image denoising on the photoresist package development and curing image, the noise level in the photoresist package development and curing image can be effectively reduced, and the clarity and accuracy of the image can be improved. This step provides a clearer and more reliable image basis for subsequent processing, which helps to accurately identify and analyze the features in the image. Next, by performing contrast enhancement processing on the photoresist package development and denoising image, the contrast of the photoresist package development and denoising image can be further improved. Such a processing process can highlight the details in the image and help to more accurately detect and analyze the features in the image. Finally, by performing defect monitoring on the photoresist package development contrast standard image, any defects or abnormalities in the photoresist package development contrast standard image can be comprehensively and accurately identified. This step provides important data for quality control of the production process, helping to promptly discover and correct potential problems and ensure the quality and reliability of the final product.

[0122] Preferably, step S36 includes the following steps:

[0123] Step S361: performing abnormality detection processing on the photoresist package development contrast standard image to obtain abnormal data of the photoresist package development image;

[0124] The embodiment of the present invention processes the photoresist package development contrast standard image by using an anomaly detection algorithm (for example, a statistically based method, an outlier detection algorithm in machine learning) to extract abnormal conditions in the photoresist package development contrast standard image, including abnormal changes in the image due to foreign matter or other irregular properties, and finally obtains abnormal data of the photoresist package development image.

[0125] Step S362: performing abnormal defect evaluation analysis on the abnormal data of the photoresist package development image to obtain an abnormal defect factor of the photoresist package development;

[0126] The embodiment of the present invention further evaluates and analyzes the extracted abnormal data of the photoresist package development image to identify the specific factors causing the abnormal defects, and extracts the corresponding abnormal defect factors therefrom, and finally obtains the photoresist package development abnormal defect factors.

[0127] Step S363: Defect monitoring is performed on the photoresist package development contrast standard image according to the photoresist package development abnormal defect factor to obtain photoresist package development defect data.

[0128] The embodiment of the present invention processes the photoresist package development contrast standard image by using the photoresist package development abnormal defect factor to extract the potential defect conditions in the photoresist package development contrast standard image, including information data such as the position, shape, and size of the defect area, and finally obtains the photoresist package development defect data.

[0129] The present invention firstly performs abnormal detection processing on the photoresist package development contrast standard image, and can accurately detect abnormal conditions in the photoresist package development contrast standard image. This may include image changes of foreign matter or other irregular properties. The detailed advantage of this step is that it improves the accuracy and sensitivity of defect detection, ensures that even tiny abnormalities can be effectively captured, and provides a reliable data basis for further analysis. Then, by performing abnormal defect evaluation analysis on the abnormal data of the photoresist package development image, the specific factors causing the abnormal defects can be identified, and the photoresist package development abnormal defect factor can be generated. This analysis not only quantifies the nature of the abnormality, but also provides a deep understanding of the defect formation mechanism. The detailed advantage of this step is that it provides powerful guidance for quality improvement in the manufacturing process, helps to eliminate potential abnormal defect factors, and improves product quality and consistency. Finally, by using the photoresist package development abnormal defect factor to monitor the photoresist package development contrast standard image, this targeted monitoring can effectively improve the efficiency and accuracy of defect detection, and ensure that only potential problem areas are focused on. By performing defect monitoring according to the abnormal defect factor, not only defects can be found in time, but also real-time and accurate data support can be provided for quality control and manufacturing process improvement. The detailed advantage of this step is that it improves production efficiency and the controllability of the overall manufacturing process while ensuring product quality.

[0130] Preferably, step S4 comprises the following steps:

[0131] Step S41: performing defect mode learning processing on the photoresist package development defect data to obtain photoresist package defect mode data;

[0132] The embodiment of the present invention collects photoresist package development defect data, including various defect types and related data features in the development process. At the same time, the collected data is cleaned and outliers or incomplete data are removed to ensure the quality of the data. Then, key features such as the shape, size, and position of the defects are extracted from the cleaned photoresist package development defect data for subsequent learning and classification. Finally, by using a machine learning algorithm, such as a deep learning model or a traditional pattern recognition method, the extracted key features are subjected to pattern learning, and finally the photoresist package defect pattern data is obtained.

[0133] Step S42: using an intelligent classification algorithm to perform defect classification processing on the photoresist package defect mode data to obtain photoresist package defect type data;

[0134] The embodiment of the present invention trains the photoresist package defect mode data by using intelligent classification algorithms in machine learning, such as support vector machines, decision trees, or deep learning neural networks, to establish a defect classification model. Then, the new photoresist package defect mode data is classified by using the trained defect classification model to finally obtain the photoresist package defect type data.

[0135] Step S43: performing packaging defect improvement matching on the photoresist packaging defect type data through a preset photoresist packaging development defect improvement knowledge base to generate a photoresist packaging defect improvement strategy;

[0136] The embodiment of the present invention pre-sets a suitable photoresist package development defect improvement knowledge base, which contains known defect types and their corresponding improvement strategies. Then, by matching the photoresist package defect type data with the information in the photoresist package development defect improvement knowledge base, an applicable defect improvement strategy is found, and at the same time, based on the matching results, a photoresist package defect improvement strategy is finally generated, including specific operation steps, parameter adjustment, etc.

[0137] Step S44: performing corresponding photoresist package defect improvement operations according to the photoresist package defect improvement strategy.

[0138] The embodiment of the present invention uses the generated photoresist packaging defect improvement strategy to perform corresponding photoresist packaging defect improvement operations, including operations such as adjusting photoresist packaging equipment and optimizing process parameters.

[0139] The present invention firstly performs defect mode learning processing on the photoresist encapsulation development defect data, and can deeply analyze the photoresist encapsulation development defect data, identify and extract different defect modes. This learning process can help better understand different types of defects and their potential causes, and provide a strong basis for subsequent classification and improvement strategies. Detailed and comprehensive defect mode learning helps to more accurately identify and understand complex manufacturing defects, thereby improving the overall defect analysis capability. Secondly, the photoresist encapsulation defect mode data is subjected to defect classification processing by using an intelligent classification algorithm to achieve accurate classification of defects. This classification processing can divide complex defect data into different types, so that the nature and characteristics of defects can be understood more effectively. Through intelligent classification, not only the accuracy of defect identification can be improved, but also a more targeted data basis can be provided for subsequent improvement strategies, thereby accelerating the process of problem solving and quality improvement. Then, by using a preset photoresist encapsulation development defect improvement knowledge base, the photoresist encapsulation defect type data is matched with previously successful improvement experience, thereby generating a targeted defect improvement strategy. The detailed beneficial effect of this step is that by making full use of the lessons learned in the knowledge base, different types of defects can be responded to more quickly and accurately, thereby improving the efficiency and success rate of defect improvement. Finally, specific improvement work is performed according to the generated photoresist packaging defect improvement strategy. This includes adjusting manufacturing parameters, changing the production process, or taking other corresponding actions to correct the detected defects. Through targeted improvement strategies, defects can be effectively eliminated, production efficiency and product quality can be improved, thereby achieving continuous improvement and optimization of the photoresist packaging process.

[0140] Preferably, the present invention further provides a system for improving a photoresist packaging process, which is used to perform the method for improving a photoresist packaging process as described above, and the system for improving a photoresist packaging process comprises:

[0141] The photolithography chip coating and packaging processing module is used to perform surface pretreatment on the surface of the photolithography chip to obtain a photolithography chip adhesion strengthening surface; perform hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface; perform multi-layer photoresist coating and packaging treatment on the photolithography chip adhesion hydrophobic surface to obtain a chip photoresist coating and packaging layer;

[0142] The photoresist mask exposure processing module is used to perform mask imaging auxiliary alignment on the chip photoresist coating packaging layer to obtain a photoresist packaging mask alignment image; perform standing wave elimination exposure processing on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave elimination exposure image;

[0143] The photoresist development defect monitoring module is used to perform development and curing processing on the photoresist package standing wave elimination exposure image to obtain a photoresist package development and curing image; and to perform defect monitoring on the photoresist package development and curing image to obtain photoresist package development defect data;

[0144] The photoresist package defect improvement module is used to perform package defect improvement processing on the photoresist package development and curing image based on the photoresist package development defect data to generate a photoresist package defect improvement strategy; and execute corresponding photoresist package defect improvement operations according to the photoresist package defect improvement strategy.

[0145] In summary, the present invention provides a system for improving a photoresist packaging process, the system for improving a photoresist packaging process comprises a photoresist chip coating and packaging processing module, a photoresist mask exposure processing module, a photoresist development defect monitoring module and a photoresist packaging defect improvement module, and can implement any one of the methods for improving a photoresist packaging process described in the present invention, and is used to combine the operations between computer programs running on each module to implement a method for improving a photoresist packaging process. The internal structures of the system cooperate with each other, and multi-layer packaging and mask design are introduced to improve the sensitivity of the photoresist to light, thereby achieving higher resolution and shorter exposure time. At the same time, the photoresist is accurately solidified through development and curing treatment to form a stable packaging layer. Defect monitoring is also used to ensure that any abnormal defects occurring during the development process can be discovered in a timely manner, providing key data support for subsequent improvements. By generating defect improvement strategies based on monitored defect data, the developer and curing image can be automatically adjusted to overcome existing defects. This proactive improvement strategy ensures process stability and product quality, and provides a guarantee for the quality of the final product of photoresist packaging. This can greatly reduce repetitive work and manpower investment, and can quickly and effectively provide a more accurate and efficient photoresist packaging process improvement process, thereby simplifying the operating procedures of the system for improving the photoresist packaging process.

[0146] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0147] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for improving a photoresist packaging process, characterized in that: The following steps are involved: Step S1: performing surface pretreatment on the surface of the photolithography chip to obtain a photolithography chip adhesion strengthening surface; performing hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface; performing multi-layer photoresist coating and packaging treatment on the photolithography chip adhesion hydrophobic surface to obtain a chip photoresist coating and packaging layer; wherein step S1 includes the following steps: Step S11: Detect impurity particles on the surface of the photolithography chip to obtain the distribution information of impurity particles on the chip surface; Step S12: performing particle removal processing on the surface of the photolithography chip according to the distribution information of impurity particles on the chip surface to obtain a particle-removed surface of the photolithography chip; Step S13: using a surfactant to perform an activation treatment on the particle-removed surface of the photolithography chip to obtain an active surface of the photolithography chip; Step S14: using plasma treatment technology to perform uniform adhesion strengthening treatment on the active surface of the photolithography chip to obtain an adhesion strengthening surface of the photolithography chip; Step S15: performing a hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface; Step S16: performing a multi-layer photoresist coating and packaging process on the hydrophobic surface of the photolithography chip to obtain a chip photoresist coating and packaging layer; wherein step S16 includes the following steps: Step S161: using chemical modification technology to control the wettability of the hydrophobic surface to which the photolithography chip is adhered, so as to obtain a wettability-modified surface of the photolithography chip; Step S162: introducing a photoresist coating machine and performing film thickness control calculation on the photoresist coating machine using a coating film thickness control calculation formula to obtain a photoresist coating film thickness control value; Among them, the calculation formula for controlling the coating film thickness is as follows: ； In the formula, For in time The photoresist coating film thickness control value at Time variable parameters calculated for film thickness control, The time-integrated variable parameter calculated for film thickness control, is the initial coating film thickness parameter of the photoresist coater, is the coating speed control parameter of the photoresist coater, is the coating time attenuation coefficient of the photoresist coater, is the coating frequency oscillation parameter of the photoresist coater, is the Gaussian distribution amplitude parameter of the photoresist coater coating time, is the mean value of the Gaussian distribution of the coating time of the photoresist coater, is the standard deviation of the Gaussian distribution of the photoresist coating time, is the correction value of the photoresist coating film thickness control value; Step S163: performing a multi-layer photoresist coating and packaging process on the wet modified surface of the photolithography chip using a photoresist coater based on the photoresist coating film thickness control value to obtain a chip photoresist coating and packaging layer; Step S2: performing mask imaging auxiliary alignment on the chip photoresist coating packaging layer to obtain a photoresist packaging mask alignment image; performing standing wave elimination exposure processing on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave elimination exposure image; Step S3: performing development and curing processing on the photoresist package standing wave elimination exposure image to obtain a photoresist package development and curing image; performing defect monitoring on the photoresist package development and curing image to obtain photoresist package development defect data; Step S4: performing packaging defect improvement matching on the photoresist packaging development defect data to generate a photoresist packaging defect improvement strategy; and executing corresponding photoresist packaging defect improvement operations according to the photoresist packaging defect improvement strategy.

2. The method for improving the photoresist packaging process according to claim 1, characterized in that: Step S15 includes the following steps: Step S151: using a surface hydrophilicity calculation formula to calculate the hydrophilicity of the photolithography chip adhesion strengthening surface to obtain a hydrophilicity value of the photolithography chip surface; Step S152: comparing and judging the surface hydrophilicity value of the photolithography chip according to a preset surface hydrophilicity threshold value, when the surface hydrophilicity value of the photolithography chip is greater than or equal to the preset surface hydrophilicity threshold value, the photolithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the photolithography chip is determined as the photolithography chip hydrophilic surface; when the surface hydrophilicity value of the photolithography chip is less than the preset surface hydrophilicity threshold value, the photolithography chip adhesion strengthening surface corresponding to the surface hydrophilicity value of the photolithography chip is determined as the photolithography chip hydrophobic surface; Step S153: when it is determined that the adhesion strengthening surface of the lithography chip is the hydrophilic surface of the lithography chip, the hydrophilic surface of the lithography chip is divided into a heating range to obtain a low temperature range, a medium temperature range and a high temperature range; when the heating range is in the low temperature range, the hydrophilic surface of the lithography chip is subjected to a low temperature evaporation treatment to obtain a hydrophilic low temperature evaporation area of ​​the chip; when the heating range is in the medium temperature range, the hydrophilic low temperature evaporation area of ​​the chip is subjected to a medium temperature molecule removal treatment to obtain a hydrophilic medium temperature molecule removal area of ​​the chip; when the heating range is in the high temperature range, the hydrophilic medium temperature molecule removal area of ​​the chip is subjected to a high temperature drying treatment to obtain a hydrophilic high temperature hydrophobic recovery area of ​​the chip; Step S154: when it is determined that the adhesion strengthening surface of the photolithography chip is the hydrophobic surface of the photolithography chip, the hydrophobic surface of the photolithography chip is subjected to an adhesion-increasing and drying treatment to obtain a hydrophobic adhesion-increasing and hydrophobic recovery area of ​​the chip; Step S155: Merge the chip hydrophilic high temperature hydrophobic recovery area and the chip hydrophobic viscosity increased hydrophobic recovery area to obtain a photolithography chip adhesion hydrophobic surface.

3. The method for improving the photoresist packaging process according to claim 2, characterized in that: The surface hydrophilicity calculation formula in step S151 is specifically: ； ； In the formula, is the hydrophilicity value of the photolithography chip surface, is the surface area parameter of the photolithography chip adhesion strengthening surface, is the surface area range parameter of the photolithography chip adhesion strengthening surface, is the spatial coordinate parameter of the photolithography chip adhesion strengthening surface, Strengthening surfaces for photolithographic chip adhesion in spatial coordinates The surface tension parameter at is the gradient operator, is the hydrophilicity influence measurement parameter of the surface tension gradient term, is the hydrophilicity effect measurement parameter of surface tension curvature, is the temperature parameter of the photolithography chip adhesion strengthening surface, is the temperature attenuation coefficient, is the hydrophilicity influence measurement parameter of the temperature attenuation term, is the surface medium distribution range parameter of the photolithography chip adhesion strengthening surface, is the surface medium distribution position parameter of the photolithography chip adhesion strengthening surface, is the surface medium distribution function, is the surface medium distribution normalization coefficient, is the mean value of the surface medium distribution, is the standard deviation of the surface medium distribution, It is the correction value of the hydrophilicity value of the photolithography chip surface.

4. The method for improving photoresist packaging process according to claim 1, characterized in that: Step S2 includes the following steps: Step S21: performing encapsulation cross-connection on the chip photoresist coating encapsulation layer to obtain a chip photoresist encapsulation cross-connection structure; Step S22: using optical imaging technology to perform mask imaging auxiliary alignment on the chip photoresist package cross-connection structure to obtain a photoresist package mask alignment image; Step S23: performing standing wave effect exposure division on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave non-exposure image area and a photoresist packaging standing wave exposure image area; Step S24: performing edge exposure adjustment on the photoresist package standing wave exposure image area to obtain a photoresist package standing wave exposure edge adjustment area; Step S25: performing standing wave elimination soft baking treatment on the photoresist package standing wave non-exposure image area and the photoresist package standing wave exposure edge adjustment area to obtain a photoresist package standing wave elimination exposure image.

5. The method for improving photoresist packaging process according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: performing non-essential area detection on the photoresist package standing wave elimination exposure image to obtain the photoresist non-essential image area; Step S32: developing and dissolving the photoresist in the non-essential image area of ​​the photoresist by using a photolithography developer to obtain a non-essential developed and dissolved image of the photoresist; Step S33: performing hard baking and curing treatment on the photoresist non-essential development and dissolution image to obtain a photoresist package development and curing image; Step S34: performing image denoising processing on the photoresist package development and curing image to obtain a photoresist package development denoised image; Step S35: performing contrast enhancement processing on the photoresist package development denoised image to obtain a photoresist package development contrast standard image; Step S36: performing defect monitoring on the photoresist package development contrast standard image to obtain photoresist package development defect data.

6. The method for improving photoresist packaging process according to claim 5, characterized in that: Step S36 includes the following steps: Step S361: performing abnormality detection processing on the photoresist package development contrast standard image to obtain abnormal data of the photoresist package development image; Step S362: performing abnormal defect evaluation analysis on the abnormal data of the photoresist package development image to obtain an abnormal defect factor of the photoresist package development; Step S363: Defect monitoring is performed on the photoresist package development contrast standard image according to the photoresist package development abnormal defect factor to obtain photoresist package development defect data.

7. The method for improving photoresist packaging process according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: performing defect mode learning processing on the photoresist package development defect data to obtain photoresist package defect mode data; Step S42: using an intelligent classification algorithm to perform defect classification processing on the photoresist package defect mode data to obtain photoresist package defect type data; Step S43: performing packaging defect improvement matching on the photoresist packaging defect type data through a preset photoresist packaging development defect improvement knowledge base to generate a photoresist packaging defect improvement strategy; Step S44: performing corresponding photoresist package defect improvement operations according to the photoresist package defect improvement strategy.

8. A system for improving a photoresist packaging process, characterized in that: A method for improving a photoresist packaging process as claimed in claim 1, wherein the system for improving a photoresist packaging process comprises: The photolithography chip coating and packaging processing module is used to perform surface pretreatment on the surface of the photolithography chip to obtain a photolithography chip adhesion strengthening surface; perform hydrophobic drying treatment on the photolithography chip adhesion strengthening surface to obtain a photolithography chip adhesion hydrophobic surface; perform multi-layer photoresist coating and packaging treatment on the photolithography chip adhesion hydrophobic surface to obtain a chip photoresist coating and packaging layer; The photoresist mask exposure processing module is used to perform mask imaging auxiliary alignment on the chip photoresist coating packaging layer to obtain a photoresist packaging mask alignment image; perform standing wave elimination exposure processing on the photoresist packaging mask alignment image to obtain a photoresist packaging standing wave elimination exposure image; The photoresist development defect monitoring module is used to perform development and curing processing on the photoresist package standing wave elimination exposure image to obtain a photoresist package development and curing image; and to perform defect monitoring on the photoresist package development and curing image to obtain photoresist package development defect data; The photoresist package defect improvement module is used to perform package defect improvement processing on the photoresist package development and curing image based on the photoresist package development defect data to generate a photoresist package defect improvement strategy; and execute corresponding photoresist package defect improvement operations according to the photoresist package defect improvement strategy.

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