Thin film transistor and method for manufacturing the same, and display panel

Abstract

The present application provides a thin film transistor and a method for preparing the same, and a display panel. The thin film transistor includes: a substrate; a semiconductor layer, the semiconductor layer is arranged on the substrate, the semiconductor layer includes a metal oxide, and the semiconductor layer has a top surface, a peripheral side surface and a bottom surface connected in sequence, and the bottom surface of the semiconductor layer faces the substrate; a first gate, the first gate is arranged on a side of the semiconductor layer adjacent to the substrate, and the first gate is at least partially facing the bottom surface of the semiconductor layer; and a second gate, the second gate is arranged on a side of the semiconductor layer away from the first gate, the second gate includes a first sub-gate portion and a second sub-gate portion, the first sub-gate portion is at least partially facing the top surface of the semiconductor layer, the second sub-gate portion is at least partially facing the peripheral side surface of the semiconductor layer, and the second sub-gate portion abuts and is electrically connected to the first gate, so that the thin film transistor has both high mobility and device stability, thereby meeting the product requirements of high performance of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a thin film transistor and a method for preparing the same, and a display panel. Background Art

[0002] Thin-film transistors (TFT) are a type of field effect transistors (FET) widely used in the display field. Whether it is an active liquid crystal display product (AMLCD) or an active matrix organic light-emitting diode display product (AMOLED), thin-film transistors must participate in the switching and driving process. As the core device of display products, the performance of thin-film transistors will directly affect the performance and life of display products.

[0003] However, existing thin film transistors have the problem of unstable device performance, which limits the performance improvement of display panels and cannot meet the driving requirements of high-performance display products. Summary of the invention

[0004] In view of this, the present application provides a thin film transistor and a method for manufacturing the same, and a display panel, so that the thin film transistor has high mobility and high stability.

[0005] In a first aspect, the present application provides a thin film transistor, the thin film transistor comprising:

[0006] substrate;

[0007] A semiconductor layer, wherein the semiconductor layer is disposed on the substrate, the semiconductor layer comprises a metal oxide, and the semiconductor layer has a top surface, a peripheral side surface and a bottom surface which are sequentially connected, and the bottom surface of the semiconductor layer faces the substrate;

[0008] a first gate, the first gate being disposed on a side of the semiconductor layer adjacent to the substrate, and at least a portion of the first gate being directly opposite to a bottom surface of the semiconductor layer; and

[0009] A second gate, the second gate is arranged on a side of the semiconductor layer away from the first gate, the second gate includes a first sub-gate portion and a second sub-gate portion, the first sub-gate portion at least partially faces the top surface of the semiconductor layer, the second sub-gate portion at least partially faces the peripheral side surface of the semiconductor layer, and the second sub-gate portion abuts and is electrically connected to the first gate.

[0010] Among them, the thin film transistor also includes a source and a drain, and the source and the drain include a first electrode portion and a second electrode portion. The first electrode portion is arranged on the side of the second gate away from the substrate, the first electrode portion extends to the edge of the second gate, and the second electrode portion is at least partially opposite to the peripheral side surface of the semiconductor layer.

[0011] Wherein, a portion of the second gate adjacent to the first gate and a portion of the first gate adjacent to the second gate have the same material;

[0012] A portion of the first electrode portion adjacent to the second gate and a portion of the second gate portion adjacent to the first electrode portion have the same material.

[0013] The semiconductor layer is a single-layer metal oxide layer, the metal oxide layer includes amorphous metal oxide or polycrystalline metal oxide, and the material of the metal oxide layer includes one or more of rare earth elements, indium, gallium and zinc.

[0014] Among them, the semiconductor layer includes a multilayer metal oxide layer, the multilayer metal oxide layer includes a first sublayer and a second sublayer stacked together, the first sublayer and the second sublayer have different mobilities, and the material of the metal oxide layer includes one or more of rare earth elements, indium, gallium and zinc.

[0015] Wherein, the thin film transistor further comprises:

[0016] A first insulating layer, the first insulating layer is sandwiched between the semiconductor layer and the first gate, the first insulating layer has a first through hole extending along a first direction, and the first direction is an arrangement direction of the substrate and the semiconductor layer; and

[0017] A second insulating layer, the second insulating layer is sandwiched between the semiconductor layer and the second gate, the second insulating layer has a second through hole extending along the first direction, the second through hole is at least partially opposite to the first through hole, and the second sub-gate portion is at least partially accommodated in the first through hole and the second through hole.

[0018] Among them, the thin film transistor also includes a third insulating layer, the third insulating layer is arranged on the side of the second gate away from the substrate, the third insulating layer has a third through hole, the second insulating layer also has a fourth through hole, the semiconductor layer is exposed in the fourth through hole, the fourth through hole is at least partially opposite to the third through hole, and the second electrode portion is at least partially accommodated in the third through hole and the fourth through hole.

[0019] The first insulating layer includes a first film layer and a second film layer which are stacked, the first film layer is disposed adjacent to the first gate, the second film layer is disposed adjacent to the second gate, and the material of the first film layer includes one of silicon nitride and silicon oxynitride, and the material of the second film layer includes aluminum oxide;

[0020] The second insulating layer is a single-layer film layer or a multi-layer film layer, and the third insulating layer is a single-layer film layer or a multi-layer film layer.

[0021] In a second aspect, the present application also provides a display panel, which includes a driving circuit and an array substrate, wherein the array substrate includes thin film transistors arranged in an array, and the driving circuit is electrically connected to the thin film transistors and is used to control the operation of the thin film transistors.

[0022] In a third aspect, the present application further provides a method for preparing a thin film transistor, the method comprising:

[0023] providing a substrate;

[0024] preparing a first gate, wherein the first gate is disposed on the substrate;

[0025] Prepare a semiconductor layer, the semiconductor layer is arranged on a side of the first gate away from the substrate, the semiconductor layer comprises a metal oxide, the semiconductor layer has a top surface, a peripheral side surface and a bottom surface connected in sequence, the bottom surface of the semiconductor layer faces the substrate, and the first gate at least partially faces the bottom surface of the semiconductor layer;

[0026] A second gate is prepared, wherein the second gate is arranged on a side of the semiconductor layer facing away from the first gate, and the second gate includes a first sub-gate portion and a second sub-gate portion, wherein the first sub-gate portion at least partially faces the top surface of the semiconductor layer, and the second sub-gate portion at least partially faces the peripheral side surface of the semiconductor layer, and the second sub-gate portion abuts against and is electrically connected to the first gate.

[0027] The method further comprises preparing a first insulating film layer on a surface of the first gate facing away from the substrate, and the preparing of the semiconductor layer comprises:

[0028] Depositing a semiconductor film layer on a surface of the first insulating film layer away from the first gate, wherein the semiconductor film layer is a single layer of amorphous metal oxide, or a single layer of polycrystalline metal oxide, or a multilayer of metal oxide, and the multilayer of metal oxide includes a first sublayer and a second sublayer stacked, and the first sublayer and the second sublayer have different mobilities;

[0029] The semiconductor film layer is annealed to obtain a semiconductor layer, wherein the annealing temperature ranges from 260° C. to 450° C., and the annealing time ranges from 30 min to 90 min.

[0030] Wherein, the method further comprises:

[0031] Forming a second insulating film layer on a surface of the semiconductor layer facing away from the substrate;

[0032] Punching the first insulating film layer and the second insulating film layer to obtain a first insulating layer and a second insulating layer, wherein the first insulating layer has a first through hole extending along a first direction, the first direction being the arrangement direction of the substrate and the semiconductor layer, and the second insulating layer has a second through hole extending along the first direction, and the second through hole at least partially faces the first through hole;

[0033] The second gate is prepared on the surface of the second insulating layer facing away from the semiconductor layer, and the second gate includes a first sub-gate portion and a second sub-gate portion, the first sub-gate portion at least partially faces the top surface of the semiconductor layer, and the second sub-gate portion is accommodated in the first through hole and the second through hole, and at least partially faces the peripheral side surface of the semiconductor layer.

[0034] The thin film transistor provided in this embodiment includes a substrate, a semiconductor layer, a first gate and a second gate, and the semiconductor layer includes a metal oxide, so that the thin film transistor achieves a device characteristic of higher mobility and meets the high requirements for the current driving capability of the thin film transistor. And the second sub-gate portion is arranged opposite to the peripheral side of the semiconductor layer and abuts against the first gate, so that the second gate cooperates with the first gate and reduces the exposure of the semiconductor layer to the top, bottom and side light of the thin film transistor, thereby avoiding the degradation of the characteristics of the thin film transistor due to the exposure of the semiconductor layer, and thus effectively ensuring the performance stability of the thin film transistor. The thin film transistor has both high mobility and device stability through the selection of semiconductor layer materials and the design of the device shading structure, thereby meeting the product requirements of high performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1is a schematic structural diagram of a display panel according to an embodiment of the present application;

[0037] Figure 2 yes Figure 1 A schematic diagram of a partial structure of a display panel along the AA line section provided in;

[0038] Figure 3 is a partial structural schematic diagram of a cross section of a thin film transistor along line AA according to Embodiment 1 of the present application;

[0039] Figure 4 is a partial structural schematic diagram of a cross section of a thin film transistor along line AA according to a second embodiment of the present application;

[0040] Figure 5 is a partial structural schematic diagram of a cross section of a thin film transistor along line AA according to a third embodiment of the present application;

[0041] Figure 6 is a schematic diagram of the steps of the method for preparing a thin film transistor according to the first embodiment of the present application;

[0042] Figure 7 is a schematic diagram of the steps of a method for preparing a thin film transistor according to the second embodiment of the present application;

[0043] Figure 8 It is a schematic diagram of the process structure of the thin film transistor manufacturing method of the second embodiment of the present application;

[0044] Fig. 9 is a schematic diagram of the steps of a method for preparing a thin film transistor according to the third embodiment of the present application;

[0045] Fig.10 It is a schematic diagram of the process structure of the thin film transistor manufacturing method of the third embodiment of the present application;

[0046] Fig.11 is a schematic diagram of the steps of a method for preparing a thin film transistor according to a fourth embodiment of the present application;

[0047] Fig.12 It is a schematic diagram of the process structure of the thin film transistor manufacturing method of the fourth embodiment of the present application.

[0048] Description of reference numerals:

[0049] 1-display panel, 10-thin film transistor, 20-driving circuit, 30-array substrate, 11-substrate, 12-semiconductor layer, 13-first gate, 14-second gate, 15-source and drain, 16-first insulating layer, 17-second insulating layer, 18-third insulating layer, 19-fourth insulating layer, 21-organic insulating layer, 22-anode, 121-top surface, 122-side surface, 123-bottom surface, 124-first sublayer, 125-second sublayer, 141-first subgate portion, 142-second subgate portion, 151-first electrode portion, 152-second electrode portion, 161-first through hole, 162-first film layer, 163-second film layer, 171-second through hole, 172-fourth through hole, 173-second insulating film layer, 181-third through hole. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0052] Reference to "embodiment" or "implementation" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment or implementation may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0053] Before introducing the technical solution of the present application, the technical problems in the related technology are introduced in detail.

[0054] Thin-Film Transistors (TFT) are a type of field effect transistor (FET) widely used in the display field. They have a basic structure and working principle similar to traditional silicon-based metal oxide semiconductor field effect transistors (MOSFETs). As the core device in the display system, both active liquid crystal display products (AMLCD) and active matrix organic light-emitting diode display products (AMOLED) must be involved in the switching and driving process of thin-film transistors. Therefore, the performance of thin-film transistors will directly affect the performance and life of display products. High-performance thin-film transistor backplane technology is a key link in improving the quality of display products.

[0055] According to the different semiconductor materials of the active layer of the thin film transistor, the current mainstream thin film transistor technology can be divided into hydrogenated amorphous silicon thin film transistor, low temperature polycrystalline silicon thin film transistor and amorphous oxide thin film transistor. Among them, the lower mobility of hydrogenated amorphous silicon thin film transistor (usually less than 1cm 2 / Vs) cannot meet the driving requirements of the next generation of display products, and the large-area uniformity of low-temperature polysilicon thin-film transistors is poor, so they are mainly used in small-size display products. Oxide thin-film transistors (Oxide TFTs) are considered to be the most likely to be used in the next generation of display products. In recent years, metal oxide thin-film transistors have attracted extensive attention from domestic and foreign research institutions and panel manufacturers due to their outstanding advantages in high mobility, good large-area uniformity, visible light transparency, and process compatibility.

[0056] With the increasing size of display panels, the development of ultra-high definition and high refresh rate, and the gradual maturity of high-performance display solutions such as Micro Light Emitting Diode Display (Micro-LED), TFT devices are required to have a field effect mobility greater than 40cm while maintaining a low off-state current. 2 / Vs, and have good performance stability, and oxide thin film transistors can meet the above requirements. In addition, oxide thin film transistors have a simple structure and low-temperature process flow, which greatly reduces investment and operating costs, so they have become a hot spot for development.

[0057] However, oxide thin-film transistors based on the bottom gate staggered structure, ESF structure, or top gate structure currently formed using the back channel etching process (BCE) will all have ion diffusion in the insulating dielectric layer and the insulating protection layer, which will cause the characteristics of the oxide thin-film transistor to shift and affect the stability of the device.

[0058] In view of this, in order to solve the above problems, the present application provides a thin film transistor 10 and a method for manufacturing the same, and a display panel 1. Figure 1 and Figure 2 , Figure 1 is a schematic structural diagram of a display panel according to an embodiment of the present application, Figure 2 yes Figure 1 A partial structural schematic diagram of a display panel along the AA line cross section provided in FIG. The thin film transistor 10 of this embodiment includes a substrate 11, a semiconductor layer 12, a first gate 13 and a second gate 14. The semiconductor layer 12 is disposed on the substrate 11, the semiconductor layer 12 includes a metal oxide, and the semiconductor layer 12 has a top surface 121, a peripheral side surface 122 and a bottom surface 123 connected in sequence, and the bottom surface 123 of the semiconductor layer 12 faces the substrate 11. The first gate 13 is disposed on a side of the semiconductor layer 12 adjacent to the substrate 11, and the first gate 13 at least partially faces the bottom surface 123 of the semiconductor layer 12. The second gate 14 is arranged on a side of the semiconductor layer 12 away from the first gate 13, and the second gate 14 includes a first sub-gate portion 141 and a second sub-gate portion 142. The first sub-gate portion 141 at least partially faces the top surface 121 of the semiconductor layer 12, and the second sub-gate portion 142 at least partially faces the peripheral side surface 122 of the semiconductor layer 12, and the second sub-gate portion 142 abuts and is electrically connected to the first gate 13.

[0059] Optionally, the thin film transistor 10 is applied to the display panel 1 and can control the display state of pixels in the display panel 1 .

[0060] Optionally, the substrate 11 is a transparent substrate 11 , and the substrate 11 is made of glass or other transparent materials.

[0061] The semiconductor layer 12 is disposed on a side of the first gate 13 away from the substrate 11 and is indirectly supported on the substrate 11. The semiconductor layer 12 has a top surface 121, a peripheral side surface 122 and a bottom surface 123 which are bent and connected in sequence. In other words, the top surface 121 is disposed opposite to the bottom surface 123, and the bottom surface 123 is disposed adjacent to and facing the substrate 11, one end of the peripheral side surface 122 is connected to the top surface 121, and the other end of the peripheral side surface 122 is connected to the bottom surface 123.

[0062] The semiconductor layer 12 is made of metal oxide, and the metal oxide includes but is not limited to amorphous metal oxide, polycrystalline metal oxide, or a combination of amorphous metal oxide and polycrystalline metal oxide.

[0063] Understandably, as consumers have higher requirements for viewing experience, the image quality requirements of the display panel 1 are getting higher and higher. For the display panel 1, resolution and frame rate are its main parameters, and it is easier to obtain a better viewing experience at high resolution and high frame rate. Similarly, as the frame rate increases, the current driving capability requirements of the thin film transistor 10 (TFT) are also getting higher and higher, and mobility is a key parameter to measure the current driving capability of the thin film transistor 10.

[0064] Preferably, in this embodiment, the metal oxide is composed of a material having certain semiconductor properties. For example, the metal oxide material contains elements including but not limited to indium (In), gallium (Ga), tin (Sn), zinc (Zn), oxygen (O) and rare earth elements to achieve device characteristics of the thin film transistor 10 with higher mobility.

[0065] Preferably, the mobility of the material of the semiconductor layer 12 reaches 5 cm 2 / Vs~50cm 2 / Vs, thereby meeting the high requirement on the current driving capability of the thin film transistor 10.

[0066] It should be noted that although the metal oxide semiconductor material has a high transmittance to visible light, the device characteristics of the thin film transistor 10 composed of metal oxides are easily degraded under light conditions, that is, the semiconductor layer 12 is unstable when exposed to light. Therefore, it is necessary to add a light shielding layer during the preparation process of the thin film transistor 10, but the introduction of the light shielding layer will not only increase the process cost, but also affect the device characteristics of the thin film transistor 10 itself.

[0067] In this embodiment, the first gate 13 is taken as an example to be illustrated, and the orthographic projection of the first gate 13 on the substrate 11 covers the orthographic projection of the bottom surface 123 on the substrate 11, so that the first gate 13 can completely or at least partially block the illumination of the semiconductor layer 12 by the light at the bottom of the thin film transistor 10, thereby reducing the influence of light on the semiconductor layer 12, and further improving the performance stability of the thin film transistor 10.

[0068] Optionally, in this embodiment, the bottom of the thin film transistor 10 refers to a side of the thin film transistor 10 adjacent to the substrate 11 .

[0069] Preferably, the first gate 13 is made of a non-light-transmitting material.

[0070] Optionally, the second gate 14 includes a first sub-gate portion 141 and a second gate portion 141 that are spaced apart. The first sub-gate portion 141 is disposed directly opposite to the top surface 121 of the semiconductor layer 12, and is capable of blocking the top light of the thin film transistor 10 from irradiating the semiconductor layer 12. The second sub-gate portion 142 is directly opposite to the peripheral side surface 122 of the semiconductor layer 12, and the second sub-gate portion 142 abuts against and is electrically connected to the first gate 13, and is capable of blocking the side light of the thin film transistor 10 from irradiating the semiconductor layer 12, and there is no need to introduce an additional light shielding layer structure.

[0071] Optionally, there are multiple second sub-gate portions 142 disposed opposite to the multiple peripheral side surfaces 122 of the semiconductor layer 12 . There may also be only one second sub-gate portion 142 disposed around the multiple peripheral side surfaces 122 of the semiconductor layer 12 .

[0072] Preferably, the second gate 14 is made of a non-light-transmitting material.

[0073] In summary, the thin film transistor 10 provided in this embodiment includes a substrate 11, a semiconductor layer 12, a first gate 13 and a second gate 14, and the semiconductor layer 12 includes a metal oxide, so that the thin film transistor 10 achieves a device characteristic of higher mobility, and meets the high requirements for the current driving capability of the thin film transistor 10. And the second sub-gate portion 142 is arranged opposite to the peripheral side surface 122 of the semiconductor layer 12 and abuts against the first gate 13, so that the second gate 14 cooperates with the first gate 13 and reduces the irradiation of the semiconductor layer 12 by the top, bottom and side light of the thin film transistor 10, thereby avoiding the degradation of the characteristics of the thin film transistor 10 due to the irradiation of the semiconductor layer 12, thereby effectively ensuring the performance stability of the thin film transistor 10. The thin film transistor 10 has both high mobility and device stability through the selection of the material of the semiconductor layer 12 and the device shading design, thereby meeting the product requirements of the high performance of the display panel 1.

[0074] Please refer again Figure 2 The thin film transistor 10 further includes a source-drain electrode 15 , and the source-drain electrode 15 includes a first electrode portion 151 and a second electrode portion 152 , wherein the first electrode portion 151 is disposed on a side of the second gate electrode 14 away from the substrate 11 , and the first electrode portion extends to an edge of the second gate electrode, and the second electrode portion 152 at least partially faces the peripheral side surface 122 of the semiconductor layer 12 .

[0075] Optionally, the source and drain electrodes 15 include a source electrode and a drain electrode that are spaced apart from each other, and the source electrode and the drain electrode are disposed on both sides of the semiconductor layer 12 .

[0076] Optionally, the first electrode portion 151 and the second electrode portion 152 are connected by bending, and the bending angle between the first electrode portion 151 and the second electrode portion 152 includes but is not limited to 90° or approximately 90°.

[0077] Optionally, the first electrode portion 151 is arranged on a side of the second gate 14 facing away from the substrate 11, and the orthographic projection of the first electrode portion 151 on the substrate 11 covers the orthographic projection of the second gate 14 on the substrate 11. In other words, the first electrode portion 151 extends to the edge of the second gate 14.

[0078] Optionally, the second electrode portion 152 is opposite to the peripheral side surface 122 of the semiconductor layer 12 , and the second electrode portion 152 abuts against the peripheral side surface 122 of the semiconductor layer 12 .

[0079] In this embodiment, the first electrode portion 151 of the source and drain electrode 15 extends to the edge structure of the second gate electrode 14, and the second electrode portion 152 extends to the peripheral side surface 122 of the semiconductor layer 12. The source and drain electrode 15, the second gate electrode 14 and the first gate electrode 13 of the thin film transistor 10 surround the semiconductor layer 12, thereby effectively preventing the top light and bottom light of the thin film transistor 10 from affecting the device characteristics and further improving the device stability of the thin film transistor 10.

[0080] Please refer again Figure 2 The portion of the second gate 14 adjacent to the first gate 13 and the portion of the first gate 13 adjacent to the second gate 14 have the same material. The portion of the first electrode portion 151 adjacent to the second gate 14 and the portion of the second gate 14 adjacent to the first electrode portion 151 have the same material.

[0081] Optionally, the first gate 13 is a single-layer film, or a double-layer film, or a triple-layer film, or more film layers, and the first gate 13 is made of a single metal, or a metal alloy, or a conductive oxide.

[0082] Furthermore, the material of the first gate 13 includes but is not limited to copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), niobium (Nb), magnesium (Mg), cobalt (Co), tungsten (W), indium (In) or other metal elements.

[0083] Optionally, the second gate 14 is a single-layer film, or a double-layer film, or a triple-layer film, or more film layers, and the second gate 14 is made of a single metal, or a metal alloy, or a conductive oxide.

[0084] Furthermore, the material of the second gate 14 includes but is not limited to copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), niobium (Nb), magnesium (Mg), cobalt (Co), tungsten (W), indium (In) or other metal elements.

[0085] Optionally, the source and drain electrodes 15 are single-layer films, double-layer films, triple-layer films, or more film layers, and the source and drain electrodes 15 are made of single metal, metal alloy, or conductive oxide.

[0086] Furthermore, the material of the source and drain 15 includes but is not limited to copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), niobium (Nb), magnesium (Mg), cobalt (Co), tungsten (W), indium (In), oxygen (O) or other elements.

[0087] In this embodiment, when the second gate 14 is a double-layer film structure or more film structure, the metal element in the film layer of the second gate 14 adjacent to the first gate 13 is consistent with the metal element of the first gate 13, thereby reducing the potential difference caused by the material difference between the second gate 14 and the first gate 13, thereby reducing the ion diffusion between the second gate 14 and the first gate 13. And when the source and drain 15 is a double-layer film structure or more film structure, the metal element in the film layer of the first electrode portion 151 of the source and drain 15 adjacent to the second gate 14 is consistent with the metal element of the second gate 14, thereby reducing the potential difference caused by the material difference between the source and drain 15 and the second gate 14, thereby reducing the ion diffusion between the source and drain 15 and the second gate 14, and avoiding the deviation of the characteristics of the thin film transistor 10, thereby ensuring the device stability of the thin film transistor 10.

[0088] Please refer again Figure 2 The semiconductor layer 12 is a single metal oxide layer, the metal oxide layer includes amorphous metal oxide or polycrystalline metal oxide, and the material of the metal oxide layer includes one or more of rare earth elements, indium, gallium and zinc.

[0089] In an optional implementation of the present application, the semiconductor layer 12 is a single-layer metal oxide layer, and the metal oxide layer is an amorphous metal oxide.

[0090] Preferably, in this embodiment, the metal oxide is made of a material having certain semiconductor properties, for example, the metal oxide contains oxygen (O) elements, and the elements contained in the metal oxide include but are not limited to one or more of rare earth elements, indium (In), gallium (Ga) and zinc (Zn). When the metal oxide material contains indium elements, the indium element content in the metal oxide material is different from the monomer content of other metal elements, so as to achieve a thin film transistor 10 device characteristic with higher mobility.

[0091] Furthermore, when the metal oxide contains rare earth elements, the rare earth elements contained in the metal oxide include but are not limited to one or more of lanthanum (La), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y).

[0092] Furthermore, in this embodiment, the mobility of the thin film transistor 10 can reach 15 cm 2 / Vs~30cm 2 / Vs.

[0093] In another optional embodiment of the present application, the semiconductor layer 12 is a single-layer metal oxide layer, and the metal oxide layer is a polycrystalline metal oxide.

[0094] Preferably, in this embodiment, the metal oxide is made of a material having certain semiconductor properties. For example, the metal oxide material contains elements including but not limited to indium (In), gallium (Ga), zinc (Zn), oxygen (O) and rare earth elements, and the indium content in the metal oxide material is different from the monomer content of other metal elements, so as to achieve a device characteristic of the thin film transistor 10 with a higher mobility. Furthermore, in this embodiment, the mobility of the thin film transistor 10 can reach 20cm 2 / Vs~50cm 2 / Vs, thereby meeting the high requirement on the current driving capability of the thin film transistor 10.

[0095] See also Figure 3 , Figure 3 1 is a partial structural schematic diagram of a cross section of a thin film transistor along line AA of the first embodiment of the present application. The semiconductor layer 12 includes a multi-layer metal oxide layer, the multi-layer metal oxide layer includes a first sub-layer 124 and a second sub-layer 125 stacked, the first sub-layer 124 and the second sub-layer 125 have different mobilities, and the material of the metal oxide layer includes one or more of rare earth elements, indium, gallium and zinc.

[0096] In another optional embodiment of the present application, the semiconductor layer 12 is formed by stacking multiple metal oxide layers. Specifically, the multiple metal oxide layers include at least a first sublayer 124 and a second sublayer 125, and along the arrangement direction of the substrate 11 and the semiconductor layer 12, the first sublayer 124 and the second sublayer 125 are stacked.

[0097] Preferably, the metal oxide is made of a material having certain semiconductor properties, for example, the metal oxide contains oxygen (O) elements, and the elements contained in the metal oxide include but are not limited to one or more of rare earth elements, indium (In), gallium (Ga) and zinc (Zn). When the metal oxide material contains indium elements, the content of indium elements in the metal oxide material is different from the monomer content of other metal elements, so as to achieve a thin film transistor 10 device characteristic with higher mobility.

[0098] Furthermore, when the metal oxide contains rare earth elements, the rare earth elements contained in the metal oxide include but are not limited to one or more of lanthanum (La), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc) and yttrium (Y).

[0099] Furthermore, the mobility of the thin film transistor 10 reaches 15 cm 2 / Vs~30cm 2 / Vs.

[0100] Optionally, the first sublayer 124 is composed of an amorphous metal oxide or a polycrystalline metal oxide, and the second sublayer 125 is composed of an amorphous metal oxide or a polycrystalline metal oxide. The first sublayer 124 and the second sublayer 125 can both be amorphous metal oxides, or both be polycrystalline metal oxides, or one layer is an amorphous metal oxide and the other is a polycrystalline metal oxide, as long as the first sublayer 124 and the second sublayer 125 have different mobilities.

[0101] Optionally, the multi-layer metal oxide layer may further include a third sub-layer, a fourth sub-layer, and more sub-layers with different mobilities, etc., which is not limited in the present application.

[0102] In this embodiment, the first sublayer 124 and the second sublayer 125 have different mobilities, that is, the semiconductor layer 12 is formed by stacking metal oxide layers with different mobilities, thereby ensuring the stability of the thin film transistor 10 device while maintaining the high mobility of the thin film transistor 10 device.

[0103] See also Figure 4 , Figure 4 It is a partial structural schematic diagram of the cross section of the thin film transistor along the AA line of the second embodiment of the present application. The thin film transistor 10 also includes a first insulating layer 16 and a second insulating layer 17. The first insulating layer 16 is sandwiched between the semiconductor layer 12 and the first gate 13, and the first insulating layer 16 has a first through hole 161 extending along a first direction, and the first direction is the arrangement direction of the substrate 11 and the semiconductor layer 12. The second insulating layer 17 is sandwiched between the semiconductor layer 12 and the second gate 14, and the second insulating layer 17 has a second through hole 171 extending along the first direction, and the second through hole 171 is at least partially opposite to the first through hole 161, and the second sub-gate portion 142 is at least partially accommodated in the first through hole 161 and the second through hole 171.

[0104] Optionally, the first insulating layer 16 covers the surface of the first gate 13 adjacent to the semiconductor layer 12, and the first insulating layer 16 is an insulating dielectric layer arranged between the first gate 13 and the semiconductor layer 12, and the first insulating layer 16 includes but is not limited to a film layer combination of silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0105] Optionally, the first direction is an arrangement direction of the substrate 11 and the semiconductor layer 12 . In other words, the first direction is a stacking direction of the substrate 11 and the semiconductor layer 12 .

[0106] Optionally, the number of the first through hole 161 is one, two, three, four, or more, and the first through hole 161 penetrates the first insulating layer 16 along the first direction. The first through hole 161 is used to receive part of the second gate 14 .

[0107] Optionally, the second insulating layer 17 covers the surface of the semiconductor layer 12 adjacent to the second gate 14 , and the second insulating layer 17 is an insulating dielectric layer disposed between the semiconductor layer 12 and the second gate 14 , and the second insulating layer 17 includes but is not limited to a thin film of silicon oxide or aluminum oxide material.

[0108] Optionally, the number of the second through hole 171 is one, two, three, four, or more, and the second through hole 171 penetrates the second insulating layer 17 along the first direction. The second through hole 171 is used to receive part of the second gate 14 .

[0109] In this embodiment, the second through hole 171 is arranged opposite to the first through hole 161, and part of the second sub-gate portion 142 is accommodated in the first through hole 161 and the second through hole 171, that is, the second sub-gate portion 142 is penetrated by the first through hole 161 and the second through hole 171 and connected to the first gate 13, so as to reduce the influence of the top light and bottom light of the thin film transistor 10 on the stability of the semiconductor layer 12 and effectively extend the service life of the thin film transistor 10.

[0110] Please refer again Figure 4 The thin film transistor 10 further includes a third insulating layer 18, which is disposed on a side of the second gate 14 away from the substrate 11, and has a third through hole 181. The second insulating layer 17 further includes a fourth through hole 172, and the semiconductor layer 12 is exposed in the fourth through hole 172. The fourth through hole 172 at least partially faces the third through hole 181, and the second electrode portion 152 is at least partially accommodated in the third through hole 181 and the fourth through hole 172.

[0111] Optionally, the third insulating layer 18 includes but is not limited to a thin film of silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, and may be a composite film layer of the above-mentioned multiple film layers.

[0112] Optionally, the third insulating layer 18 is disposed on a side of the second gate 14 away from the substrate 11 , and provides insulation protection for the second gate 14 to prevent the second gate 14 from being corroded by external water vapor.

[0113] Optionally, the number of the third through holes 181 is one, two, three, four, or more, and the third through holes 181 penetrate the third insulating layer 18 along the first direction.

[0114] Optionally, the number of the fourth through holes 172 is one, two, three, four, or more, and the fourth through holes 172 penetrate the second insulating layer 17 along the first direction. The semiconductor layer 12 is exposed in the fourth through holes 172, so that during the preparation process of the thin film transistor 10, it is convenient to inject doping into the semiconductor layer 12 through the fourth through holes 172.

[0115] In this embodiment, the fourth through hole 172 is opposite to the third through hole 181, and the second electrode portion 152 of the source and drain 15 is accommodated in the third through hole 181 and the fourth through hole 172, that is, the second electrode portion 152 is penetrated through the third through hole 181 and the fourth through hole 172 and abuts against the first insulating layer 16, so that the second electrode portion 152 can withstand the influence of the top light and bottom light of the thin film transistor 10 on the characteristics of the semiconductor layer 12, thereby ensuring the stability of the performance of the thin film transistor 10 and avoiding the degradation of the semiconductor layer 12 of the thin film transistor 10 under the action of light.

[0116] See also Figure 5 , Figure 5 1 is a partial structural schematic diagram of a cross section of a thin film transistor along line AA of the third embodiment of the present application. The first insulating layer 16 includes a first film layer 162 and a second film layer 163 which are stacked, the first film layer 162 is disposed adjacent to the first gate 13, the second film layer 163 is disposed adjacent to the second gate 14, and the material of the first film layer 162 includes one of silicon nitride and silicon oxynitride, and the material of the second film layer 163 includes aluminum oxide. The second insulating layer 17 is a single film layer or a multi-layer film layer, and the third insulating layer 18 is a single film layer or a multi-layer film layer.

[0117] Optionally, the first insulating layer 16 includes but is not limited to a film layer combination of silicon oxide material, silicon nitride material, silicon oxynitride material or aluminum oxide material, and the first insulating layer 16 is a composite film layer of at least two of the above film layers. In other words, the first insulating layer 16 includes a plurality of film layers stacked together. In the schematic diagram of the present embodiment, the first insulating layer 16 is illustrated as an example of a first film layer 162 and a second film layer 163 stacked together. It can be understood that in other embodiments of the present application, the first insulating layer 16 may also include a third film layer, a fourth film layer, or more film layers sandwiched between the first film layer 162 and the second film layer 163, and the present application does not limit this.

[0118] Optionally, the first film layer 162 is disposed adjacent to the first gate 13, and the second film layer 163 is disposed adjacent to the second gate 14. The material of the first film layer 162 is silicon nitride or silicon oxynitride, that is, the first film layer 162 is a silicon nitride film layer or a silicon oxynitride film layer, and the second film layer 163 is an aluminum oxide film layer, so that the first film layer 162 and the second film layer 163 can shield a variety of active elements. When the first insulating layer 16 is a single-layer film layer, the single-layer film layer thickness of the first insulating layer 16 is relatively thick, which is easy to cause damage to the film layer when bent and deformed, and cannot meet the shielding of a variety of active elements, and cannot meet the requirements of the first insulating layer 16 for the dielectric constant. Therefore, in this embodiment, the first insulating layer 16 includes a first film layer 162 and a second film layer 163 which are stacked. The first film layer 162 is a silicon nitride film layer or a silicon nitride oxide film layer, and the second film layer 163 is an aluminum oxide film layer, so that the thickness of a single film layer in the first insulating layer 16 is relatively thin, so that the first insulating layer 16 is not easily damaged during the bending process, and can meet the dielectric constant requirements of the first film layer 162 and the second film layer 163, and meet the shielding of various active elements, thereby being able to provide good protection for the first gate 13 and the semiconductor layer 12, and effectively improve the durability of the thin film transistor 10.

[0119] Optionally, the second insulating layer 17 is a single-layer thin film, or a combination of double-layer thin films, or a combination of multiple layers of thin films. The material of the second insulating layer 17 includes but is not limited to silicon oxide, aluminum oxide or other materials.

[0120] Optionally, the third insulating layer 18 is a single-layer film, a double-layer film combination, or a film combination of multiple layers. The material of the third insulating layer 18 includes but is not limited to one or more of silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0121] Preferably, the third insulating layer 18 is a composite film layer, and the third insulating layer 18 includes a plurality of silicon oxide film, silicon nitride film, silicon oxynitride film, or aluminum oxide film. Further, the third insulating layer 18 is aluminum oxide film or silicon oxide film near the active layer. In other words, the third insulating layer 18 is aluminum oxide film or silicon oxide film near the second gate 14 and the semiconductor layer 12, and the third insulating layer 18 is silicon oxide film, silicon nitride film, silicon oxynitride film, or aluminum oxide film on the side away from the semiconductor layer 12, so as to provide good insulation protection for the second gate 14.

[0122] Optionally, the thin film transistor 10 further includes a fourth insulating layer 19, which is disposed on a side of the source and drain electrodes 15 away from the substrate 11, and insulates and protects the source and drain electrodes 15 to prevent the source and drain electrodes 15 from being corroded by water and oxygen in the external environment. The material of the fourth insulating layer 19 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, and the fourth insulating layer 19 can be a single film layer or a composite film layer composed of the above-mentioned multiple materials.

[0123] Optionally, the thin film transistor 10 further includes an organic insulating layer 21, which is disposed on a side of the fourth insulating layer 19 away from the substrate 11 to further prevent the source and drain electrodes 15 from being corroded by water and oxygen in the external environment. The organic insulating layer 21 includes, but is not limited to, polymer materials such as polyphenols, polyesters, polyaromatic hydrocarbons, and polyorganosiloxanes.

[0124] Optionally, the thin film transistor 10 further includes an anode 22, the anode 22 is partially disposed on a side of the organic insulating layer 21 away from the substrate 11, the anode 22 is partially disposed through the organic insulating layer 21 and the fourth insulating layer 19, and is electrically connected to the source and drain electrodes 15. The anode 22 is a double-layer or multi-layer structure, the anode 22 is composed of a single metal, or an alloy, or an oxide, and the material of the anode 22 includes but is not limited to copper (Cu), or molybdenum (Mo), or aluminum (Al), or titanium (Ti), or niobium (Nb), or magnesium (Mg), or cobalt (Co), or tungsten (W), or indium (In), or oxygen (O), or zinc (Zn), or gallium (Ga) or one or more of other elements, as long as the anode 22 has good electrical conductivity.

[0125] See also Figure 1 and Figure 2 The present application also provides a display panel 1 , which includes a driving circuit 20 and an array substrate 30 . The array substrate 30 includes the thin film transistors 10 arranged in an array. The driving circuit 20 is electrically connected to the thin film transistors 10 and is used to control the operation of the thin film transistors 10 .

[0126] Specifically, the display panel 1 can be but is not limited to a liquid crystal display panel 1 (Liquid Crystal D display, LCD), or a light emitting diode (Light Emitting Diode, LED) display panel 1, or an organic electric laser display panel 1 (Organic Light-Emitting Diode, OLED), or a micro light emitting diode (Micro Light Emitting Diode, Micro LED) display panel 1, or a sub-millimeter light emitting diode (Mini Light-Emitting Diode, Mini-LED) display panel 1, or a quantum dot light emitting diode (Quantum Dots Light Emitting Diode Display, QD-OLED) display panel 1, or any other type of display panel 1, etc.

[0127] Optionally, the display panel 1 includes a driving circuit 20 and an array substrate 30, the array substrate 30 includes the thin film transistors 10 arranged in an array, and the display panel 1 also includes a plurality of pixel units. The driving circuit 20 is electrically connected to the thin film transistor 10 and controls the opening or closing of the thin film transistor 10, and the thin film transistor 10 can be arranged corresponding to the pixel unit and used to adjust the display state of the pixel unit.

[0128] In this embodiment, the thin film transistor 10 can prevent the semiconductor layer 12 from being degraded due to light exposure, so that the thin film transistor 10 has both high mobility and device stability, so that the display panel 1 can meet the product performance requirements of high refresh rate and can maintain good product stability during long-term use, thereby effectively ensuring that the display panel 1 has excellent display quality and durability.

[0129] See also Figure 6 , Figure 6 Schematic diagram of the steps of the method for preparing a thin film transistor according to the first embodiment of the present application. The present application also provides a method for preparing a thin film transistor 10, the method comprising step S101, step S102, step S103 and step S104, the details of which are as follows.

[0130] Step S101 , providing a substrate 11 .

[0131] Optionally, the substrate 11 is a glass substrate 11 or a transparent substrate 11 made of other materials.

[0132] Step S102 : preparing a first gate 13 , wherein the first gate 13 is disposed on the substrate 11 .

[0133] Optionally, preparing the first gate 13 includes: depositing a first gate 13 film layer on the glass substrate 11 by magnetron sputtering, and then patterning the first gate 13 film layer by coating, exposing, developing, and etching and stripping to obtain the first gate 13.

[0134] The etching and stripping process includes dry etching or wet etching. It is understandable that the first gate 13 can also be prepared by other process procedures, which is not limited in the present application.

[0135] Step S103, preparing a semiconductor layer 12, wherein the semiconductor layer 12 is disposed on a side of the first gate 13 facing away from the substrate 11, the semiconductor layer 12 comprises a metal oxide, and the semiconductor layer 12 has a top surface 121, a peripheral side surface 122 and a bottom surface 123 which are bent and connected in sequence, the bottom surface 123 of the semiconductor layer 12 faces the substrate 11, and the first gate 13 at least partially faces the bottom surface 123 of the semiconductor layer 12.

[0136] Optionally, after the first gate 13 is prepared, the first insulating film layer may be deposited on the surface of the first gate 13 away from the substrate 11 by using an enhanced chemical vapor deposition process or an atomic layer epitaxy technique.

[0137] Optionally, a semiconductor film layer is deposited on the surface of the first insulating film layer away from the first gate 13 by a magnetron sputtering process, and the semiconductor film layer is composed of a metal oxide. The elements of the metal oxide material include but are not limited to indium (In), gallium (Ga), tin (Sn), zinc (Zn), oxygen (O) and rare earth elements.

[0138] Optionally, the semiconductor film layer is a single layer of amorphous metal oxide, or a single layer of polycrystalline metal oxide, or a multilayer of metal oxide, and the multilayer of metal oxide includes a first sublayer and a second sublayer stacked together, and the first sublayer and the second sublayer have different mobilities.

[0139] Optionally, the semiconductor film layer is subjected to an annealing process, and the annealed semiconductor film layer is patterned by coating, developing and etching and stripping processes to obtain the semiconductor layer 12. The mobility of the semiconductor layer 12 satisfies 5 cm 2 / Vs~50cm 2 / Vs.

[0140] Preferably, in the annealing process of the semiconductor film layer, the annealing temperature range is 260°C to 450°C, and the annealing time range is 30min to 90min, so as to promote the transformation of the metal oxide in the semiconductor film layer from an amorphous state to a polycrystalline state, so that the lattice of the metal oxide is reorganized and the internal defects of the metal oxide are reduced, thereby effectively improving the mobility of the semiconductor film layer.

[0141] Preferably, the orthographic projection of the first gate 13 on the substrate 11 covers the orthographic projection of the semiconductor layer 12 on the substrate 11, and the material of the first gate 13 is an opaque material, so as to block the light incident from the side of the substrate 11 to the semiconductor layer 12, thereby reducing the performance degradation of the semiconductor layer 12 due to light exposure.

[0142] Step S104, preparing a second gate 14, wherein the second gate 14 is disposed on a side of the semiconductor layer 12 away from the first gate 13, and the second gate 14 includes a first sub-gate portion 141 and a second sub-gate portion 142, wherein the first sub-gate portion 141 at least partially faces the top surface 121 of the semiconductor layer 12, and the second sub-gate portion 142 at least partially faces the peripheral side surface 122 of the semiconductor layer 12, and the second sub-gate portion 142 abuts and is electrically connected to the first gate 13.

[0143] Optionally, after the semiconductor layer 12 is prepared, a second insulating film layer 173 is deposited on the surface of the semiconductor layer 12 away from the substrate 11 by a chemical vapor deposition process, and the second insulating film layer 173 is annealed. The annealed second insulating film layer 173 is then subjected to a coating, development, and etching stripping process.

[0144] Preferably, in the annealing process of the second insulating film layer 173, the annealing temperature range is 300°C to 450°C, and the annealing time range is 45min to 75min, so as to promote the movement and coupling of ions and defects inside the second insulating film layer 173, and can promote the volatilization of excess elements inside the second insulating film layer 173, and reduce the surface defects of the second insulating film layer 173, so that the obtained second insulating layer 17 has a better protective effect on the semiconductor layer 12, and reduces the particle diffusion generated by the second insulating layer 17 during the operation of the thin film transistor 10, thereby reducing the deviation of the device characteristics of the thin film transistor 10 and improving the device stability of the thin film transistor 10.

[0145] Optionally, the first insulating film layer and the second insulating film layer 173 are punched and etched to the surface of the first gate 13, and a first insulating layer 16 and a second insulating layer 17 are obtained. The first insulating layer 16 has a first through hole 161 extending along a first direction, and the first direction is the arrangement direction of the substrate and the semiconductor layer. The second insulating layer 17 has a second through hole 171 extending along the first direction, and the second through hole 171 is directly opposite to or partially directly opposite to the first through hole 161.

[0146] Optionally, after the second insulating layer 17 is prepared, a second gate 14 is deposited on the surface of the second insulating layer 17 away from the substrate 11, and the second gate 14 includes a first sub-gate portion 141 and a second sub-gate portion 142, the first sub-gate portion 141 is arranged directly opposite to the top surface 121 of the semiconductor layer 12, the second sub-gate portion 142 is received in the through hole of the second insulating layer 17, and is arranged directly opposite to the peripheral side surface 122 of the semiconductor layer 12, and the second sub-gate portion 142 abuts against and is electrically connected to the first gate 13. The second gate 14 can block the irradiation of the semiconductor layer 12 by the top surface 121 and side light of the thin film transistor 10, thereby further avoiding the situation where the performance of the semiconductor layer 12 is degraded due to light irradiation.

[0147] The top surface 121 of the thin film transistor 10 refers to a side of the thin film transistor 10 facing away from the substrate 11 .

[0148] Optionally, the second gate 14 film layer can be prepared by magnetron sputtering deposition, and then the second gate 14 film layer is patterned by coating, developing and etching and stripping methods to obtain the second gate 14. It can be understood that in other embodiments of the present application, the second gate 14 can also be prepared by other process methods, and the present application does not limit this.

[0149] See also Figure 7 and Figure 8 , Figure 7 is a schematic diagram of the steps of the method for preparing a thin film transistor according to the second embodiment of the present application, Figure 8 1 is a schematic diagram of the process structure of the thin film transistor manufacturing method of the second embodiment of the present application. In another embodiment of the present application, the manufacturing method of the thin film transistor 10 includes step S201, step S202, step S203, step S204, step S205, step S206, step S207, step S208, step S209 and step S210, the details of which are as follows.

[0150] S201, providing a substrate 11.

[0151] Optionally, the substrate 11 is a glass substrate 11 or a transparent substrate 11 made of other materials.

[0152] S202 , preparing a first gate 13 , wherein the first gate 13 is disposed on the substrate 11 .

[0153] Optionally, preparing the first gate 13 includes: depositing a first gate 13 film layer on the glass substrate 11 by magnetron sputtering, and then patterning the first gate 13 film layer by coating, exposing, developing, and etching and stripping to obtain the first gate 13.

[0154] The etching and stripping process includes dry etching or wet etching. It is understandable that the first gate 13 can also be prepared by other process procedures, which is not limited in the present application.

[0155] S203 , forming a first insulating layer 16 on a side of the first gate 13 facing away from the substrate 11 .

[0156] Optionally, the first insulating layer 16 is formed by deposition on a surface of the first gate 13 facing away from the substrate 11 using an enhanced chemical vapor deposition process or an atomic layer epitaxy technique.

[0157] S204, prepare a semiconductor layer 12, wherein the semiconductor layer 12 is disposed on a side of the first insulating layer 16 away from the substrate 11, the semiconductor layer 12 comprises a single layer of amorphous metal oxide, and the semiconductor layer 12 has a top surface 121, a peripheral side surface 122 and a bottom surface 123 which are bent and connected in sequence, the bottom surface 123 of the semiconductor layer 12 faces the substrate 11, and the first gate 13 at least partially faces the bottom surface 123 of the semiconductor layer 12.

[0158] Optionally, a semiconductor film layer is deposited on the surface of the first insulating layer 16 away from the first gate 13 by a magnetron sputtering process, and the semiconductor film layer is composed of a single layer of amorphous metal oxide. The elements of the metal oxide material include but are not limited to indium (In), gallium (Ga), zinc (Zn), oxygen (O) and rare earth elements.

[0159] Optionally, the semiconductor film layer is subjected to an annealing process, and the annealed semiconductor film layer is patterned by coating, developing and etching and stripping processes to obtain the semiconductor layer 12. The mobility of the semiconductor layer 12 satisfies 15 cm 2 / Vs~30cm 2 / Vs.

[0160] Preferably, in the annealing process of the semiconductor film layer, the annealing temperature range is 260°C to 450°C, and the annealing time range is 45min to 90min, so as to promote the transformation of the metal oxide in the semiconductor film layer from an amorphous state to a polycrystalline state, so that the lattice of the metal oxide is reorganized and the internal defects of the metal oxide are reduced, thereby effectively improving the mobility of the semiconductor film layer.

[0161] Preferably, the orthographic projection of the first gate 13 on the substrate 11 covers the orthographic projection of the semiconductor layer 12 on the substrate 11, and the material of the first gate 13 is an opaque material, so as to block the light incident from the side of the substrate 11 to the semiconductor layer 12, thereby reducing the performance degradation of the semiconductor layer 12 due to light exposure.

[0162] S205 , preparing a second insulating layer 17 on the surface of the semiconductor layer 12 facing away from the substrate 11 .

[0163] Optionally, a second insulating film layer 173 is deposited on the surface of the semiconductor layer 12 away from the substrate 11 by a chemical vapor deposition process, and the second insulating film layer 173 is annealed. Then, the annealed second insulating film layer 173 is subjected to a coating, development, and etching and stripping process, and the second insulating film layer 173 is punched and etched to the surface of the first gate 13 to obtain the second insulating layer 17.

[0164] S206, prepare a second gate 14, the second gate 14 includes a first sub-gate portion 141 and a second sub-gate portion 142, the first sub-gate portion 141 at least partially faces the top surface 121 of the semiconductor layer 12, the second sub-gate portion 142 at least partially faces the peripheral side surface 122 of the semiconductor layer 12, and the second sub-gate portion 142 abuts and is electrically connected to the first gate 13.

[0165] Optionally, a second gate 14 is deposited on the surface of the second insulating layer 17 away from the substrate 11, and the second gate 14 includes a first sub-gate portion 141 and a second sub-gate portion 142, the first sub-gate portion 141 is arranged opposite to the top surface 121 of the semiconductor layer 12, the second sub-gate portion 142 is received in the through hole of the second insulating layer 17, and is arranged opposite to the peripheral side surface 122 of the semiconductor layer 12, and the second sub-gate portion 142 abuts against and is electrically connected to the first gate 13. The second gate 14 can block the irradiation of the semiconductor layer 12 by the top surface 121 and side light of the thin film transistor 10, thereby further avoiding the situation where the performance of the semiconductor layer 12 is degraded due to the irradiation of light.

[0166] The top surface 121 of the thin film transistor 10 refers to a side of the thin film transistor 10 facing away from the substrate 11 .

[0167] Optionally, the second gate 14 film layer can be prepared by magnetron sputtering deposition, and then the second gate 14 film layer is patterned by coating, developing and etching and stripping methods to obtain the second gate 14. It can be understood that in other embodiments of the present application, the second gate 14 can also be prepared by other process methods, and the present application does not limit this.

[0168] S207 , forming a third insulating layer 18 on a surface of the second gate 14 facing away from the substrate 11 .

[0169] Optionally, a third insulating film layer is prepared by chemical vapor deposition, and then coated, exposed, developed, dry etched and stripped, and holes are punched and etched to the bottom surface 123 of the third insulating film layer adjacent to the substrate 11, thereby achieving patterning of the third insulating film layer and obtaining the third insulating layer 18.

[0170] Further optionally, after obtaining the third insulating layer 18 with through holes, ion implantation equipment can be used to implant doping into the amorphous metal oxide exposed by the holes, and the process gas used includes but is not limited to boron trifluoride (BF3), argon (Ar), or helium (He) and other gases.

[0171] S208, prepare a source-drain electrode 15 on the surface of the third insulating layer 18 away from the substrate 11, the source-drain electrode 15 includes a first electrode portion 151 and a second electrode portion 152 that are connected by bending, the first electrode portion 151 is arranged on the side of the second gate 14 away from the substrate 11, and the orthographic projection of the first electrode portion 151 on the substrate 11 at least partially covers the orthographic projection of the second gate 14 on the substrate 11, and the second electrode portion 152 is at least partially opposite to and abuts against the peripheral side surface 122 of the semiconductor layer 12.

[0172] Optionally, the source and drain electrode 15 base layer is prepared on the third insulating layer 18 by magnetron sputtering deposition, and then the source and drain electrode 15 base layer is patterned by processes such as glue coating, development, dry etching and stripping to obtain the source and drain electrode 15.

[0173] The first electrode portion 151 of the source-drain electrode 15 is disposed on a side of the second gate electrode 14 away from the substrate 11, and extends to the edge of the second gate electrode 14. The second electrode portion 152 of the source-drain electrode 15 is received in the through holes of the third insulating layer 18 and the second insulating layer 17, and extends to the peripheral side surface 122 of the semiconductor layer 12.

[0174] In this embodiment, the source and drain electrodes 15 , the second gate electrode 14 and the first gate electrode 13 surround the semiconductor layer 12 , thereby effectively preventing the top light and bottom light of the thin film transistor 10 from affecting the device characteristics and further improving the device stability of the thin film transistor 10 .

[0175] S209 , preparing a fourth insulating layer 19 and an organic insulating layer 21 on the surface of the source and drain electrodes 15 facing away from the substrate 11 , and the organic insulating layer 21 is disposed on a side of the fourth insulating layer 19 facing away from the substrate 11 .

[0176] Optionally, a fourth insulating film layer is formed on the surface of the source / drain electrode 15 and the surface of the third insulating layer 18 facing away from the substrate 11 by using a chemical vapor deposition process.

[0177] Optionally, a chemical vapor deposition process or other process methods are used to form an organic insulating film layer on the side of the fourth insulating film layer facing away from the substrate 11, and then a perforated structure of the fourth insulating film layer and the organic insulating film layer is formed by coating, developing, wet etching, etc., thereby obtaining the fourth insulating layer 19 and the organic insulating layer 21.

[0178] S210 , preparing an anode 22 on a surface of the organic insulating layer 21 facing away from the substrate 11 .

[0179] Optionally, an anode film layer is formed on the surface of the organic insulating layer 21 away from the substrate 11 by using a magnetron sputtering process, and the anode film layer is annealed to obtain the anode 22. The temperature range of the annealing process is 200°C to 280°C, and the time range of the annealing process is 25min to 45min.

[0180] See also Fig. 9 and Fig.10 , Fig. 9 is a schematic diagram of the steps of the method for preparing a thin film transistor according to the third embodiment of the present application, Fig.10 1 is a schematic diagram of the process structure of the thin film transistor manufacturing method of the third embodiment of the present application. In another embodiment of the present application, the manufacturing method of the thin film transistor 10 includes step S301, step S302, step S303, step S304, step S305, step S306, step S307, step S308, step S309 and step S310, the details of which are as follows.

[0181] S301, providing the substrate 11.

[0182] S302 , preparing a first gate 13 , wherein the first gate 13 is disposed on the substrate 11 .

[0183] S303 , forming a first insulating layer 16 on a side of the first gate 13 facing away from the substrate 11 .

[0184] S304, prepare a semiconductor layer 12, wherein the semiconductor layer 12 is disposed on a side of the first insulating layer 16 away from the substrate 11, the semiconductor layer 12 comprises a single layer of polycrystalline metal oxide, and the semiconductor layer 12 has a top surface 121, a peripheral side surface 122 and a bottom surface 123 which are bent and connected in sequence, the bottom surface 123 of the semiconductor layer 12 faces the substrate 11, and the first gate 13 at least partially faces the bottom surface 123 of the semiconductor layer 12.

[0185] Optionally, a semiconductor film layer is deposited on the surface of the first insulating layer 16 away from the first gate 13 by a magnetron sputtering process, and the semiconductor film layer is composed of a single layer of polycrystalline metal oxide. The elements of the metal oxide material include but are not limited to indium (In), gallium (Ga), zinc (Zn), oxygen (O) and rare earth elements.

[0186] Optionally, the semiconductor film layer is subjected to an annealing process, and the annealed semiconductor film layer is patterned by coating, developing and etching and stripping processes to obtain the semiconductor layer 12. The mobility of the semiconductor layer 12 satisfies 20 cm 2 / Vs~50cm 2 / Vs.

[0187] Preferably, in the annealing process of the semiconductor film layer, the annealing temperature range is 260°C to 450°C, and the annealing time range is 45min to 90min, so as to promote the transformation of the metal oxide in the semiconductor film layer from an amorphous state to a polycrystalline state, so that the lattice of the metal oxide is reorganized and the internal defects of the metal oxide are reduced, thereby effectively improving the mobility of the semiconductor film layer.

[0188] S305 , forming a second insulating layer 17 on the surface of the semiconductor layer 12 facing away from the substrate 11 .

[0189] S306, prepare a second gate 14, the second gate 14 includes a first sub-gate portion 141 and a second sub-gate portion 142, the first sub-gate portion 141 at least partially faces the top surface 121 of the semiconductor layer 12, the second sub-gate portion 142 at least partially faces the peripheral side surface 122 of the semiconductor layer 12, and the second sub-gate portion 142 abuts and is electrically connected to the first gate 13.

[0190] S307 , forming a third insulating layer 18 on a surface of the second gate 14 facing away from the substrate 11 .

[0191] S308, prepare a source-drain electrode 15 on the surface of the third insulating layer 18 away from the substrate 11, the source-drain electrode 15 includes a first electrode portion 151 and a second electrode portion 152 that are connected by bending, the first electrode portion 151 is arranged on the side of the second gate 14 away from the substrate 11, and the orthographic projection of the first electrode portion 151 on the substrate 11 at least partially covers the orthographic projection of the second gate 14 on the substrate 11, and the second electrode portion 152 is at least partially opposite to and abuts against the peripheral side surface 122 of the semiconductor layer 12.

[0192] S309 , preparing a fourth insulating layer 19 and an organic insulating layer 21 on the surface of the source and drain electrodes 15 facing away from the substrate 11 , and the organic insulating layer 21 is disposed on a side of the fourth insulating layer 19 facing away from the substrate 11 .

[0193] S310 , preparing an anode 22 on a surface of the organic insulating layer 21 facing away from the substrate 11 .

[0194] See also Fig.11 and Fig.12 , Fig.11 is a schematic diagram of the steps of a method for preparing a thin film transistor according to the fourth embodiment of the present application, Fig.12 Schematic diagram of the process structure of the thin film transistor manufacturing method of the fourth embodiment of the present application. In another embodiment of the present application, the manufacturing method of the thin film transistor 10 includes step S401, step S402, step S403, step S404, step S405, step S406, step S407, step S408, step S409 and step S410, the details of which are as follows.

[0195] S401, providing a substrate 11.

[0196] S402 , preparing a first gate 13 , wherein the first gate 13 is disposed on the substrate 11 .

[0197] S403 , forming a first insulating layer 16 on a side of the first gate 13 facing away from the substrate 11 .

[0198] S404, prepare a semiconductor layer 12, wherein the semiconductor layer 12 is disposed on a side of the first insulating layer 16 away from the substrate 11, the semiconductor layer 12 includes a plurality of metal oxide layers, the plurality of metal oxide layers include a first sublayer 124 and a second sublayer 125 which are stacked, the first sublayer 124 and the second sublayer 125 having different mobilities, the semiconductor layer 12 has a top surface 121, a peripheral side surface 122 and a bottom surface 123 which are bent and connected in sequence, the bottom surface 123 of the semiconductor layer 12 faces the substrate 11, and the first gate 13 at least partially faces the bottom surface 123 of the semiconductor layer 12.

[0199] Optionally, a stacked metal oxide material with different mobilities is deposited on the surface of the first insulating layer 16 away from the first gate 13 by a magnetron sputtering process to obtain the semiconductor film layer. The elements of the metal oxide material include but are not limited to indium (In), gallium (Ga), zinc (Zn), oxygen (O) and rare earth elements.

[0200] Optionally, the semiconductor film layer is subjected to an annealing process, and the annealed semiconductor film layer is patterned by coating, developing and etching and stripping processes to obtain the semiconductor layer 12. The mobility of the semiconductor layer 12 satisfies 20 cm 2 / Vs~50cm 2 / Vs.

[0201] Preferably, in the annealing process of the semiconductor film layer, the annealing temperature range is 260°C to 450°C, and the annealing time range is 45min to 90min, so as to promote the transformation of the metal oxide in the semiconductor film layer from an amorphous state to a polycrystalline state, so that the lattice of the metal oxide is reorganized and the internal defects of the metal oxide are reduced, thereby effectively improving the mobility of the semiconductor film layer.

[0202] S405 , forming a second insulating layer 17 on the surface of the semiconductor layer 12 facing away from the substrate 11 .

[0203] S406, prepare a second gate 14, the second gate 14 includes a first sub-gate portion 141 and a second sub-gate portion 142, the first sub-gate portion 141 at least partially faces the top surface 121 of the semiconductor layer 12, the second sub-gate portion 142 at least partially faces the peripheral side surface 122 of the semiconductor layer 12, and the second sub-gate portion 142 abuts and is electrically connected to the first gate 13.

[0204] S407 , forming a third insulating layer 18 on a surface of the second gate 14 facing away from the substrate 11 .

[0205] S408, prepare a source-drain electrode 15 on the surface of the third insulating layer 18 away from the substrate 11, the source-drain electrode 15 includes a first electrode portion 151 and a second electrode portion 152 that are connected by bending, the first electrode portion 151 is arranged on the side of the second gate 14 away from the substrate 11, and the orthographic projection of the first electrode portion 151 on the substrate 11 at least partially covers the orthographic projection of the second gate 14 on the substrate 11, and the second electrode portion 152 is at least partially opposite to and abuts against the peripheral side surface 122 of the semiconductor layer 12.

[0206] S409 , preparing a fourth insulating layer 19 and an organic insulating layer 21 on the surface of the source and drain electrodes 15 facing away from the substrate 11 , and the organic insulating layer 21 is disposed on a side of the fourth insulating layer 19 facing away from the substrate 11 .

[0207] S410 , preparing an anode 22 on a surface of the organic insulating layer 21 facing away from the substrate 11 .

[0208] Mentioning "embodiment" and "implementation method" in this application means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of the phrases in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments. In addition, it should also be understood that the features, structures or characteristics described in the various embodiments of the present application can be arbitrarily combined to form another embodiment that does not deviate from the spirit and scope of the technical solution of the present application, provided that there is no contradiction between them.

[0209] Finally, it should be noted that the above implementation modes are only used to illustrate the technical solution of the present application and are not intended to limit it. Although the present application has been described in detail with reference to the above preferred implementation modes, a person of ordinary skill in the art should understand that the technical solution of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present application.

Claims

1. A thin film transistor, characterized in that: The thin film transistor comprises: substrate; A semiconductor layer, wherein the semiconductor layer is disposed on the substrate, the semiconductor layer comprises a metal oxide, and the semiconductor layer has a top surface, a peripheral side surface and a bottom surface which are sequentially connected, and the bottom surface of the semiconductor layer faces the substrate; a first gate, the first gate being disposed on a side of the semiconductor layer adjacent to the substrate, and at least a portion of the first gate being directly opposite to a bottom surface of the semiconductor layer; and a second gate, the second gate being disposed on a side of the semiconductor layer away from the first gate, the second gate comprising a first sub-gate portion and a second sub-gate portion, the first sub-gate portion at least partially facing the top surface of the semiconductor layer, the second sub-gate portion at least partially facing the peripheral side surface of the semiconductor layer, and the second sub-gate portion abutting against and electrically connected to the first gate; The source and drain include a first electrode portion and a second electrode portion, the first electrode portion is arranged on the side of the second gate away from the substrate, the first electrode portion extends to the edge of the second gate, and the second electrode portion at least partially faces the peripheral side surface of the semiconductor layer.

2. The thin film transistor according to claim 1, wherein: A portion of the second gate adjacent to the first gate and a portion of the first gate adjacent to the second gate have the same material; A portion of the first electrode portion adjacent to the second gate and a portion of the second gate portion adjacent to the first electrode portion have the same material.

3. The thin film transistor according to claim 1, wherein: The semiconductor layer is a single-layer metal oxide layer, the metal oxide layer includes amorphous metal oxide or polycrystalline metal oxide, and the material of the metal oxide layer includes one or more of rare earth elements, indium, gallium and zinc.

4. The thin film transistor according to claim 1, wherein: The semiconductor layer includes a multilayer metal oxide layer, the multilayer metal oxide layer includes a first sublayer and a second sublayer stacked together, the first sublayer and the second sublayer have different mobilities, and the material of the metal oxide layer includes one or more of rare earth elements, indium, gallium and zinc.

5. The thin film transistor according to claim 2, wherein: The thin film transistor further comprises: A first insulating layer, the first insulating layer is sandwiched between the semiconductor layer and the first gate, the first insulating layer has a first through hole extending along a first direction, and the first direction is an arrangement direction of the substrate and the semiconductor layer; and A second insulating layer, the second insulating layer is sandwiched between the semiconductor layer and the second gate, the second insulating layer has a second through hole extending along the first direction, the second through hole is at least partially opposite to the first through hole, and the second sub-gate portion is at least partially accommodated in the first through hole and the second through hole.

6. The thin film transistor according to claim 5, characterized in that: The thin film transistor further comprises a third insulating layer, the third insulating layer is arranged on a side of the second gate away from the substrate, the third insulating layer has a third through hole, the second insulating layer further has a fourth through hole, the semiconductor layer is exposed in the fourth through hole, the fourth through hole at least partially faces the third through hole, and the second electrode portion is at least partially accommodated in the third through hole and the fourth through hole; The first insulating layer includes a first film layer and a second film layer which are stacked, the first film layer is disposed adjacent to the first gate, the second film layer is disposed adjacent to the second gate, and the material of the first film layer includes one of silicon nitride and silicon oxynitride, and the material of the second film layer includes aluminum oxide; The second insulating layer is a single-layer film layer or a multi-layer film layer, and the third insulating layer is a single-layer film layer or a multi-layer film layer.

7. A display panel, characterized in that: The display panel includes a driving circuit and an array substrate, the array substrate includes thin film transistors as described in any one of claims 1 to 6 arranged in an array, the driving circuit is electrically connected to the thin film transistors and is used to control the operation of the thin film transistors.

8. A method for preparing a thin film transistor, characterized in that: The method comprises: providing a substrate; preparing a first gate, wherein the first gate is disposed on the substrate; Prepare a semiconductor layer, the semiconductor layer is arranged on a side of the first gate away from the substrate, the semiconductor layer comprises a metal oxide, the semiconductor layer has a top surface, a peripheral side surface and a bottom surface connected in sequence, the bottom surface of the semiconductor layer faces the substrate, and the first gate at least partially faces the bottom surface of the semiconductor layer; Prepare a second gate, the second gate is disposed on a side of the semiconductor layer away from the first gate, the second gate includes a first sub-gate portion and a second sub-gate portion, the first sub-gate portion at least partially faces the top surface of the semiconductor layer, the second sub-gate portion at least partially faces the peripheral side surface of the semiconductor layer, and the second sub-gate portion abuts against and is electrically connected to the first gate; Prepare a source and drain, the source and drain comprising a first electrode portion and a second electrode portion, the first electrode portion is arranged on the side of the second gate away from the substrate, the first electrode portion extends to the edge of the second gate, and the second electrode portion at least partially faces the peripheral side of the semiconductor layer.

9. The method for preparing a thin film transistor according to claim 8, characterized in that: The method further includes preparing a first insulating film layer on a surface of the first gate facing away from the substrate, and preparing the semiconductor layer includes: Depositing a semiconductor film layer on a surface of the first insulating film layer away from the first gate, wherein the semiconductor film layer is a single layer of amorphous metal oxide, or a single layer of polycrystalline metal oxide, or a multilayer of metal oxide, and the multilayer of metal oxide includes a first sublayer and a second sublayer stacked, and the first sublayer and the second sublayer have different mobilities; The semiconductor film layer is annealed to obtain a semiconductor layer, wherein the annealing temperature ranges from 260° C. to 450° C., and the annealing time ranges from 30 min to 90 min.

10. The method for preparing a thin film transistor according to claim 9, wherein: The method further comprises: Forming a second insulating film layer on a surface of the semiconductor layer facing away from the substrate; Punching the first insulating film layer and the second insulating film layer to obtain a first insulating layer and a second insulating layer, wherein the first insulating layer has a first through hole extending along a first direction, the first direction being the arrangement direction of the substrate and the semiconductor layer, and the second insulating layer has a second through hole extending along the first direction, and the second through hole at least partially faces the first through hole; The second gate is prepared on the surface of the second insulating layer facing away from the semiconductor layer, and the second gate includes a first sub-gate portion and a second sub-gate portion, the first sub-gate portion at least partially faces the top surface of the semiconductor layer, and the second sub-gate portion is accommodated in the first through hole and the second through hole, and at least partially faces the peripheral side surface of the semiconductor layer.

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