A high-density and high-reliability in-memory computing circuit based on eDRAM

Abstract

The present invention discloses a high-density and high-reliability in-memory computing circuit based on eDRAM. The circuit includes: an eDRAM storage computing circuit, an ADC circuit, a calculation result register and an integrator capacitor reading circuit. In the calculation mode, the original data and the weight value stored in the eDRAM storage computing circuit complete the multiplication and accumulation operation, and then the multiplication and accumulation result is converted into analog to digital through the ADC circuit, and the conversion result is stored in the output result register. In the capacitor reading mode: the integrator capacitor reading circuit reads the capacitance value of each basic unit of the eDRAM storage computing circuit one by one. The present invention effectively avoids the problems of leakage current of eDRAM units, nonlinear calculation, etc. through the capacitor charging and discharging characteristics, and has the advantages of high density, high reliability, low power consumption, etc., and can be used for the computing core of neuromorphic chips, and is particularly suitable for end-side devices with high requirements for energy consumption and reliability, to achieve large-scale parallel computing.

Description

Technical Field

[0001] The present invention relates to the fields of neuromorphic circuits, in-memory computing circuits, eDRAM circuits, and in particular to the field of high-density and high-reliability in-memory computing circuit design, and specifically to a high-density and high-reliability in-memory computing circuit based on eDRAM. Background Art

[0002] With the rapid development of artificial intelligence and big data applications, the need to process large-scale data has become more urgent. The bottleneck between the memory and the processor in the traditional von Neumann computer architecture leads to low data transmission efficiency and is difficult to meet the requirements of today's large-scale data processing. The increasing complexity of artificial intelligence algorithms and the explosive growth of data volumes further emphasize the need for efficient storage and processing.

[0003] In-memory computing technology combines memory and processor, which can greatly reduce the demand for data transmission and improve computing efficiency. Existing in-memory computing technology can be simply divided into digital in-memory computing and analog in-memory computing according to the signal type. Digital in-memory computing represented by static random access memory (SRAM) has the advantages of fast speed and high reliability, but it also faces problems such as high manufacturing cost, low density and high energy consumption. Analog in-memory computing represented by non-volatile memory has the advantages of high density and low power consumption, but due to the current process, the reliability of analog in-memory computing needs to be further improved. Embedded dynamic random access memory (eDRAM) has the advantages of high density, low power consumption and high reliability, and can be used to realize high-density and high-reliability in-memory computing circuits. Summary of the invention

[0004] The purpose of the present invention is to provide a high-density and high-reliability in-memory computing circuit based on eDRAM for key multiplication and accumulation operations in neuromorphic chips, thereby achieving large-scale parallel computing and improving hardware computing efficiency while ensuring high reliability.

[0005] The technical solution of the present invention is:

[0006] A high-density and high-reliability in-memory computing circuit based on eDRAM, comprising an eDRAM memory computing circuit, an ADC circuit, a computing result register, a control circuit and an integrator capacitor reading circuit;

[0007] The control circuit is used to control the working mode of the in-memory computing circuit, and the working mode is a computing mode or a capacitance reading mode;

[0008] The eDRAM storage and calculation circuit includes an array composed of a plurality of basic units, and the eDRAM storage and calculation circuit stores pre-written weights; in the calculation mode, the eDRAM storage and calculation circuit performs multiplication and accumulation operations on the external input raw data according to the internally stored weights, and inputs the calculation results into the ADC circuit;

[0009] The ADC circuit is used to receive the calculation result of the eDRAM storage circuit and convert the calculation result into a digital signal;

[0010] The calculation result register is used to store the calculation result after conversion by the ADC circuit;

[0011] The integrator capacitance reading circuit is used to read the actual capacitance value of each basic unit of the eDRAM storage and calculation circuit in the capacitance reading mode, and correct the calculation result according to the actual capacitance value.

[0012] Furthermore, the basic unit is composed of three field effect transistors M1, M2, M3 and a capacitor, the drain of M1 is connected to the base of M2, and a weight storage node is formed at the connection point, the base of M1 is the write control terminal of the basic unit, which is used to receive the row selection signal, and the source of M1 is the weight write terminal of the basic unit, which is used to write the weight; the drain of M2 is connected to the drain of M3 and one end of the capacitor, and a capacitor reference node is formed at the connection point, and the other end of the capacitor is the result output terminal of the basic unit, and its voltage represents the calculation result of the basic unit, and the source of M2 is the data input terminal of the basic unit, which is used to input the original data during the calculation process; the source of M3 is connected to the power supply voltage, and the base of M3 is the calculation control terminal of the basic unit, which is used to control the reset of the capacitor reference node voltage during the calculation process.

[0013] Furthermore, the weight is a multi-bit binary number, the number of columns of basic units in the eDRAM storage and computing circuit is twice the number of weight bits, and every two columns of basic units store the same bit of the weight; the original data are multiple single-bit binary numbers, the number of rows of basic units in the eDRAM storage and computing circuit is equal to the number of original data, and multiple original data are input into each row of basic units at the same time.

[0014] Furthermore, the eDRAM storage and calculation circuit needs to pre-write weights before performing the multiplication and addition operation. When writing the weights, the write control terminal of the basic unit is connected to a low level, the data input terminal is connected to a high level, the calculation control terminal is connected to a low level, and the weights are input bit by bit from the weight write terminal of each column of the basic unit in sequence and stored in the weight storage node of the basic unit; when performing the multiplication and addition operation, the write control terminal of the basic unit is connected to a high level, the weight write terminal is left floating, the calculation control terminal is connected to a high level, and the original data is input in reverse from the data input terminal.

[0015] Furthermore, in the eDRAM storage and calculation circuit, the write control terminal of the eDRAM unit in each row is connected to the same word line, the data input terminal is connected to the same source line, and the calculation control terminal is connected to the same capacitor reset line; the weight write terminal of the eDRAM unit in each column is connected to the same write bit line, and the result output terminal is connected to the same read bit line;

[0016] The word line is used to receive the row selection signal of the eDRAM storage circuit, the source line is used to input the voltage representing the original data, the capacitor reset line is used to reset the voltage of the capacitor reference node, the write bit line is used to write the weight value, and the read bit line is used to output the analog voltage of each bit representing the calculation result of the eDRAM storage circuit.

[0017] Furthermore, a reset switch S2, a column weighted switch S3 and a charge redistribution switch S4 are simultaneously provided on the read bit line, the reset switch S2 is connected to the ground, the column weighted switch S3 is used to implement different weights for different read bit lines, and the charge redistribution switch S4 is connected to the eDRAM storage circuit and the ADC circuit to implement charge redistribution and ADC sampling;

[0018] When performing a multiplication-accumulation operation, the reset switch S2 is first closed to reset the read bit line voltage, and the calculation control terminals of all basic units connected to the read bit line are connected to a high level. The basic units perform weighted calculations on the original data according to their stored weights. Finally, the reset switch S2 is opened, and the basic units in each column redistribute the charge. After the voltage stabilizes, the voltage on the read bit line is the calculation result of the multiplication-accumulation operation, which is also the calculation result of the eDRAM storage and calculation circuit.

[0019] Furthermore, the ADC circuit is composed of multiple differential successive approximation ADCs, and the positive sampling port and negative sampling port of each differential successive approximation ADC are respectively connected to 8 read bit lines. During the calculation process, the differential successive approximation ADC sampling capacitor participates in charge redistribution. After the calculation is completed, the differential successive approximation ADC converts the analog voltage on the read bit line into a digital signal.

[0020] Furthermore, the integrator capacitance reading circuit is composed of a column selection switch group and an integrator. The column selection switch group is connected to the eDRAM storage and calculation circuit, and each column of basic units of the eDRAM storage and calculation circuit is selected in turn. Each time, two columns of basic units with the same weight are stored. The integrator is composed of an operational amplifier and an integrating capacitor. The calculation results of the two selected columns of basic units are integrated and output, thereby reading the corresponding actual capacitance value.

[0021] Furthermore, the in-memory computing circuit also includes an input / output interface circuit for receiving original data and transmitting it to the eDRAM memory computing circuit, and also for reading out the calculation results stored in the calculation result register.

[0022] The present invention aims to solve the bottleneck problem between storage and computing circuits in the prior art, and achieves higher integration and more reliable in-memory computing circuits by improving the eDRAM structure and introducing innovative circuit design. Through the present invention, not only can the data storage density be effectively improved, but also high reliability can be maintained during the computing process, providing a new solution for future applications in high-performance computing and artificial intelligence.

[0023] The beneficial effects of the present invention are:

[0024] The present invention provides a high-density and high-reliability in-memory computing circuit based on eDRAM. Compared with the traditional von Neumann structure, it has the advantage of close integration of memory and processor, and can avoid repeated transmission of data between the memory and the processor, thereby greatly improving computing efficiency. Compared with the current in-memory computing circuit, the present invention proposes an eDRAM basic unit and computing circuit suitable for in-memory computing, which realizes multiplication and accumulation calculations through the capacitor charging and discharging process, and realizes weighting of different weight bits and different input bits by using column weighting technology and charge redistribution technology. It has a simple structure and is easy to control, and effectively solves the problem that the existing in-memory computing circuit is difficult to be compatible with high density and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a high-density and high-reliability in-memory computing circuit structure diagram based on eDRAM proposed by the present invention;

[0026] Figure 2 It is a basic unit structure diagram of the eDRAM storage and computing circuit proposed by the present invention;

[0027] Figure 3 It is a structural diagram of the eDRAM storage and computing circuit proposed by the present invention;

[0028] Figure 4 Schematic diagram of the multiplication and accumulation of the eDRAM storage and calculation circuit proposed by the present invention, wherein (a) is multiplication and (b) is accumulation;

[0029] Figure 5 Schematic diagram of the weighted operation of charge redistribution proposed by the present invention;

[0030] Figure 6 It is a structural diagram of the integrator capacitance reading circuit proposed by the present invention. DETAILED DESCRIPTION

[0031] The present invention is further described and illustrated below in conjunction with specific embodiments. The embodiments are merely exemplary of the present disclosure and do not define the scope of limitation. The technical features of each embodiment of the present invention may be combined accordingly without conflicting with each other.

[0032] like Figure 1 As shown, the specific implementation includes an input interface circuit, an eDRAM storage and calculation circuit, an ADC circuit, a calculation result register, a control circuit, and an integrator capacitor reading circuit. The input interface circuit is used to receive the original data and transmit it to the eDRAM storage and calculation circuit for calculation. The eDRAM storage and calculation circuit includes multiple basic units, and the pre-written weight values ​​are stored inside. The circuit is divided into a calculation mode and a capacitor reading mode:

[0033] In the calculation mode, the original data is input from the input interface circuit, and under the control of the control circuit, the multiplication and accumulation operation is completed with the weight value stored in the eDRAM storage and calculation circuit, and then the multiplication and accumulation result is converted to digital through the ADC circuit, and the conversion result is stored in the output result register, and finally the calculation result is read out through the input / output interface circuit;

[0034] In capacitor reading mode: In actual scenarios, there is a certain deviation between the actual capacitance of the capacitor in the eDRAM storage circuit and the marked capacitance. Under the action of the controller, the integrator capacitor reading circuit selects the corresponding two columns of the eDRAM storage circuit each time, reads the actual capacitance value of each basic unit one by one and outputs it, so that the calculation result can be corrected according to the actual capacitance value to improve the calculation accuracy.

[0035] like Figure 2 As shown, the basic unit of the eDRAM storage and calculation circuit is composed of three field effect transistors M1, M2, M3 and a capacitor. The drain of M1 is connected to the base of M2 to form a weight storage node. The base of M1 is the write control terminal of the basic unit for receiving a row selection signal, and the source of M1 is the weight write terminal of the basic unit for writing weights; the drain of M2 is connected to the drain of M3 and one end of the capacitor, and the source of M2 is the data input terminal of the basic unit for inputting original data during the calculation process; the source of M3 is connected to the power supply voltage, and the base of M3 is the calculation control terminal of the basic unit for controlling the voltage reset of one end of the capacitor connected to M2 and M3 (capacitor reference node) during the calculation process; the other end of the capacitor is the result output terminal of the basic unit, and its voltage represents the calculation result.

[0036] Specifically, when writing weights, the base of M1 is connected to a low level, the source of M2 is connected to a high level, and the base of M3 is connected to a low level. At this time, the capacitor reference node voltage is a high level (V c =V DD), the weight value to be written will be input from the source of M1 and stored in the weight storage node (w); if the weight value is 1, the source of M1 is connected to a high level, and w is a high level at this time; if the weight value is 0, the source of M1 is connected to a low level, and w is a low level at this time.

[0037] Furthermore, when calculating, the base of M1 is connected to a high level, the source is suspended, and the original data is inverted from the source of M2. At this time, the base of M3 is connected to a high level; if the original data is 1, the source of M2 is connected to a low level, and if the original data is 0, the source of M2 is connected to a high level; if w is a low level, that is, the weight value is 0, then M2 is cut off, V c =V DD unchanged; if w is high, M2 is turned on. If the original data is 1, the capacitor is discharged through M2, Vc = 0. If the original data is 0, the capacitor is not discharged, Vc = V DD .

[0038] like Figure 3 As shown, the eDRAM storage and calculation circuit is composed of a plurality of basic units connected horizontally and vertically to form a two-dimensional structure; the base of each row of basic units M1 is connected to the same word line (WL), the source of M2 is connected to the same source line (SL), and the base of M3 is connected to the same capacitor reset line (RL); the source of each column of basic units M1 is connected to the same write bit line (BLW), and the result output end of each column of basic units is connected to the same read bit line (BLR); in the weight writing process, the word line is used to receive the row selection signal of the eDRAM storage and calculation circuit, and the write bit line is used to receive the weight value of the eDRAM storage and calculation circuit; in the calculation process, the source line is used to input the voltage representing the original data, the capacitor reset line is used to control the reset of the capacitor reference node voltage, and the read bit line is used to output the analog voltage representing the calculation result.

[0039] Furthermore, a reset switch S2, a column weighted switch S3 and a charge redistribution switch S4 are simultaneously provided on the read bit line, S2 is used to reset the voltage of the read bit line to ground, S3 is provided at different positions of the read bit line to realize weighting of different bits of different read bit line weights, and S4 is connected to the sampling capacitors of the eDRAM storage and calculation circuit and the ADC circuit to realize charge redistribution and ADC sampling.

[0040] like Figure 4 As shown, in the specific implementation process, for a 1-column m-row eDRAM circuit, the stored weight values ​​are all 1. Before calculation, RL=0, S2 is closed, and all capacitor reference node voltages V c =V DD , the output voltage V BL =0; then RL=1, and the calculation begins. There are i rows of SL=0 inputs, and mi rows of SL=1 inputs. At this time, there are i capacitors with Vc =0, according to the charge formula of capacitor, the charge Q stored in a column of basic units is:

[0041] Q=i(0-0)C+(mi)(V DD -0)C=(mi)V DD C

[0042] Where C is the capacitance of a single capacitor, m is the total number of rows in the eDRAM circuit, i is the number of rows with original data of 0, V DD is the power supply voltage; after the calculation process is completed, S2 is disconnected to make the write bit line suspended, and then RL=0, and the voltage of all capacitor reference nodes V c =1, due to the conservation of charge stored in the capacitor, the charge Q' stored in a column of basic units can be expressed as:

[0043] Q′=m(V DD -V BL )C

[0044] Q=Q′

[0045] According to the amount of charge stored in the basic unit during and after the calculation, the multiplication and accumulation calculation result of the 1-column and m-row eDRAM circuit can be obtained, that is, the voltage value V at the output end of the basic unit BL :

[0046]

[0047] like Figure 5 As shown, in the specific implementation process, each column obtains the corresponding multiplication and accumulation result V BL After that, the column weight switch S3 is turned off, and each 16 columns form a group, which are 8 columns of positive calculation results (V BLP7 ~V BLP0 ) and 8 columns of negative value calculation results (V BLN7 ~V BLN0 ), the differential successive approximation ADC of the ADC circuit includes the ADC positive sampling capacitor (C sp ) and the ADC negative sampling capacitor (C sn ), the positive calculation result and the negative calculation result are connected to the ADC positive sampling capacitor and the ADC negative sampling capacitor respectively, and the sampling capacitor size is C sp =C sn =256C. According to the weight position from high to low, the number of basic units connected to the ADC positive sampling capacitor or the ADC negative sampling capacitor in each column of the eDRAM circuit is 128, 64, ..., 2, and 1, respectively, thereby realizing the weighting process of different positions of the 8-bit weight:

[0048] W=2 7 w7+2 6w6+…+2 0 w0

[0049] Among them, W is the 8-bit weight value, w7~w0 is the value of each bit of the 8-bit weight, which is 1 or 0. Then, the charge redistribution switch S4 is closed, and the capacitor of the eDRAM storage circuit and the ADC sampling capacitor are charged redistributed. The voltage V c is the power supply voltage V DD , therefore, the positive output voltage V O+ And the negative output voltage Vo- can be expressed as:

[0050] V O+ =2 -1 V BLP7 +2 -2 V BLP6 +…+2 -8 V BLP

[0051] V o- =2 -1 V BLN7 +2 -2 V BLN +…+2 -8 V BLN0

[0052] Among them, V BLP7 ~V BLP0 is the result of 8 columns of positive value calculation, V BLN7 ~V BLN0 Calculate the results for 8 columns of negative values.

[0053] After the charge redistribution is completed, S4 is disconnected, and the ADC sampling capacitor holds the sampled result. After repeating the above multiplication and accumulation-redistribution process 7 times, the differential successive approximation ADC performs analog-to-digital conversion on the sampled voltage and stores the converted calculation result in the calculation result register.

[0054] like Figure 6 As shown, in a specific implementation process, the integrator capacitance reading circuit is composed of a column selection switch group, an operational amplifier and an integration capacitor. The column selection switch group is connected to the eDRAM storage and calculation circuit. Each time, two columns corresponding to the same weight are selected. The operational amplifier and the integration capacitor constitute an integrator, which integrates the input from the eDRAM storage and calculation circuit and outputs it, thereby reading the corresponding actual capacitance value, thereby correcting the calculation result obtained by the ADC circuit in the calculation mode.

[0055] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the specific implementation modes of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be included in the scope of the claims of the present invention.

[0056] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. For ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A high-density and high-reliability in-memory computing circuit based on eDRAM, characterized in that: It includes an eDRAM storage circuit, an ADC circuit, a calculation result register, a control circuit, and an integrator capacitor reading circuit; The control circuit is used to control the working mode of the in-memory computing circuit, and the working mode is a computing mode or a capacitance reading mode; The eDRAM storage and calculation circuit includes an array composed of a plurality of basic units, and the eDRAM storage and calculation circuit stores pre-written weights; in the calculation mode, the eDRAM storage and calculation circuit performs multiplication and accumulation operations on the external input raw data according to the internally stored weights, and inputs the calculation results into the ADC circuit; The ADC circuit is used to receive the calculation result of the eDRAM storage circuit and convert the calculation result into a digital signal; The calculation result register is used to store the calculation result after conversion by the ADC circuit; The integrator capacitance reading circuit is used to read the actual capacitance value of each basic unit of the eDRAM storage and calculation circuit in the capacitance reading mode, and correct the calculation result converted by the ADC circuit according to the actual capacitance value; In the eDRAM storage and calculation circuit, the write control terminal of the basic unit in each row is connected to the same word line, the data input terminal is connected to the same source line, and the calculation control terminal is connected to the same capacitor reset line; the weight write terminal of the basic unit in each column is connected to the same write bit line, and the result output terminal is connected to the same read bit line; The word line is used to receive the row selection signal of the eDRAM storage circuit, the source line is used to input the voltage representing the original data, the capacitor reset line is used to reset the voltage of the capacitor reference node, the write bit line is used to write the weight value, and the read bit line is used to output the analog voltage of each bit representing the calculation result of the eDRAM storage circuit; The read bit line is provided with a reset switch S2, a column weighted switch S3 and a charge redistribution switch S4 at the same time, the reset switch S2 is connected to the ground, the column weighted switch S3 is used to implement different weights for different read bit lines, and the charge redistribution switch S4 is connected to the eDRAM storage circuit and the ADC circuit to implement charge redistribution and ADC sampling; When performing a multiplication-accumulation operation, the reset switch S2 is first closed to reset the read bit line voltage, and the calculation control terminals of all basic units connected to the read bit line are connected to a high level. The basic units perform weighted calculations on the original data according to their stored weights. Finally, the reset switch S2 is opened, and the basic units in each column redistribute the charge. After the voltage stabilizes, the voltage on the read bit line is the calculation result of the multiplication-accumulation operation, which is also the calculation result of the eDRAM storage and calculation circuit.

2. The high-density and high-reliability in-memory computing circuit based on eDRAM according to claim 1, characterized in that: The basic unit is composed of three field effect transistors M1, M2, M3 and a capacitor. The drain of M1 is connected to the base of M2, and a weight storage node is formed at the connection. The base of M1 is the write control terminal of the basic unit, which is used to receive a row selection signal. The source of M1 is the weight write terminal of the basic unit, which is used to write weights. The drain of M2 is connected to the drain of M3 and one end of the capacitor, and a capacitor reference node is formed at the connection. The other end of the capacitor is the result output terminal of the basic unit, and its voltage represents the calculation result of the basic unit. The source of M2 is the data input terminal of the basic unit, which is used to input original data during the calculation process. The source of M3 is connected to the power supply voltage, and the base of M3 is the calculation control terminal of the basic unit, which is used to control the reset of the capacitor reference node voltage during the calculation process.

3. The high-density and high-reliability in-memory computing circuit based on eDRAM according to claim 1, characterized in that: The weight is a multi-bit binary number, the number of columns of basic units in the eDRAM storage and computing circuit is twice the number of weight bits, and every two columns of basic units store the same bit of the weight; the original data is multiple single-bit binary numbers, and the number of rows of basic units in the eDRAM storage and computing circuit is equal to the number of original data.

4. The high-density and high-reliability in-memory computing circuit based on eDRAM according to claim 2, characterized in that: The eDRAM storage and calculation circuit needs to pre-write weights before performing the multiplication and accumulation operation. When writing the weights, the write control terminal of the basic unit is connected to a low level, the data input terminal is connected to a high level, the calculation control terminal is connected to a low level, and the weights are input bit by bit from the weight write terminal of each column of the basic unit in sequence and stored in the weight storage node of the basic unit; when performing the multiplication and accumulation operation, the write control terminal of the basic unit is connected to a high level, the weight write terminal is left floating, the calculation control terminal is connected to a high level, and the original data is input in reverse from the data input terminal.

5. The high-density and high-reliability in-memory computing circuit based on eDRAM according to claim 1, characterized in that: The ADC circuit is composed of multiple differential successive approximation ADCs, and the positive sampling port and negative sampling port of each differential successive approximation ADC are respectively connected to 8 read bit lines. During the calculation process, the differential successive approximation ADC sampling capacitor participates in charge redistribution. After the calculation is completed, the differential successive approximation ADC converts the analog voltage on the read bit line into a digital signal.

6. The high-density and high-reliability in-memory computing circuit based on eDRAM according to claim 1, characterized in that: The integrator capacitance reading circuit is composed of a column selection switch group and an integrator. The column selection switch group is connected to the eDRAM storage and calculation circuit, and each column of the basic unit of the eDRAM storage and calculation circuit is selected in turn. Each time two columns of basic units with the same weight are stored, and the integrator is composed of an operational amplifier and an integrating capacitor. The calculation results of the two selected columns of basic units are integrated and output, thereby reading the actual capacitance value.

7. The high-density and high-reliability in-memory computing circuit based on eDRAM according to claim 1, characterized in that: The in-memory computing circuit also includes an input / output interface circuit for receiving original data and transmitting it to the eDRAM memory computing circuit, and also for reading out the computing results stored in the computing result register.

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