Unified switching system for multi-die packaged chips

Abstract

The present invention discloses a unified switching system applicable to Multi-die packaged chips, comprising: a receiving scheduling module, a data caching module, a data arbitration module, a switching module and a sending scheduling module; the receiving scheduling module parses the message header of the received network message and performs scheduling signal processing based on the parsed destination address; the data caching module caches the network message into a cache area according to the scheduling command of the receiving scheduling module; the data arbitration module arbitrates according to the destination address of the network message to complete the matching of the network switch egress and ingress; the switching module establishes a data channel of the corresponding port to transmit data; the sending scheduling module sends a back pressure request to the ingress according to the network congestion situation to complete a certain congestion buffer. The unified switching system applicable to Multi-die packaged chips of the present invention greatly reduces the connection between bare chips of the network switching chip under the Multi-die package architecture through methods such as buffer mapping, distributed Crossbar cross switch and unified interface.

Description

Technical Field

[0001] The present invention belongs to the field of network technology and FPGA technology, and specifically relates to a unified switching system suitable for Multi-die packaged chips. Background Art

[0002] In an environment where computing power and networks are developing rapidly, higher requirements are placed on network switches. Network switches need to assume the data transmission function of large computing systems, which requires a lot of computing power and programmability, which places strict requirements on the performance of switching chips. However, in recent years, Moore's Law has gradually failed, the speed of chip performance improvement has slowed down, and maintaining the rapid development of chips requires higher costs. In order to meet this challenge, advanced packaging technology has become an important strategy for rapidly improving chip performance at low cost. Multi-Die technology is becoming a solution that goes beyond Moore's Law and solves the challenges of system complexity by using multiple smaller packages to connect to each other to build large systems. It can achieve faster expansion of system functions, reduce risks, shorten product time to market, achieve higher throughput with lower power consumption, and quickly create new product categories in a cost-effective way. In the past few years, various Multi-die technologies have been gradually integrated into the manufacturing process.

[0003] The introduction of the Multi-die architecture has successfully solved the complexity issues involved in connecting numerous chips, significantly increased chip yields, and enabled larger virtual chips. These advanced chips have excellent performance and an expanded surface area, creating an ideal environment for the implementation of high-performance switches. However, when integrating switches into multi-chip package chips, some problems will arise, with the main obstacle being the limited connectivity between chips. Since network switching requires data transmission channels to be established between various interfaces. Limited interconnection between packages will make it impossible to efficiently implement existing switching architectures in the Multi-die packaging architecture. Summary of the invention

[0004] The present invention provides a unified switching system applicable to Multi-die packaged chips to solve the above-mentioned technical problems, and specifically adopts the following technical solutions:

[0005] A unified switching system suitable for Multi-die packaged chips, comprising: a receiving scheduling module, a data buffer module, a data arbitration module, a switching module and a sending scheduling module;

[0006] The receiving scheduling module is used to parse the message header of the received network message and perform scheduling signal processing based on the parsed destination address;

[0007] The data cache module is used to cache the network message into the cache area according to the scheduling command of the receiving scheduling module;

[0008] The data arbitration module is used to perform many-to-one arbitration according to the destination address of the network message to complete the matching of the egress and ingress of the network switch;

[0009] The switching module establishes a data channel of a corresponding port to transmit data according to the matching of the data arbitration module;

[0010] The sending scheduling module is used to send a back pressure request to the inlet end according to the network congestion situation, complete a certain congestion buffer, and ensure the fairness of each port under the congestion situation.

[0011] Further, the receiving scheduling module includes a receiving data parsing module and a data cache scheduling module;

[0012] The received data parsing module is used to determine the validity of the received network message and parse the destination address in the network message header;

[0013] The data cache scheduling module is used to determine the address of the network message cache according to the destination address of the network message obtained by parsing, and send the network message to the subsequent data cache module.

[0014] Furthermore, the data cache scheduling module sends the messages with destination addresses of different chips to the local chip, the southbound chip and the northbound chip respectively.

[0015] Furthermore, the data cache module performs unified resource management on the local cache, southbound cache and northbound cache, and sends a back pressure request to the port in time when the cache resources are insufficient to prevent data loss.

[0016] Furthermore, the data cache module maps the local cache to different bare chips, and manages the storage conditions of the local cache, the southbound cache, and the northbound cache.

[0017] Furthermore, the data cache module caches the data of the receiving end into respective caches according to the scheduling instruction given by the receiving scheduling module.

[0018] Furthermore, the data cache module is provided with a read-write pointer RD_POINT / WR_POINT, which is used to indicate the cache address of the receiving end data and the cache address of the data given to the next module.

[0019] Further, the data arbitration module includes a request sending module and an arbitration processing module;

[0020] The request sending module is used to receive the destination address information obtained by the receiving data parsing module in the receiving scheduling module, and send a data sending request to each export end;

[0021] The arbitration processing module is used to collect requests initiated by each entry end at each exit end, and to determine the validity of all collected requests. When a request from an entry end is authorized, the entry end will be allowed to send data to its corresponding exit end in the subsequent data transmission cycle, and the authorized entry end will be given the lowest priority in the subsequent arbitration cycle after its request is met, and a no-request flag will be inserted for the entry that has not sent a request.

[0022] Furthermore, the switching module establishes a cross-connection relationship between all inlet ports and outlet ports through a Crossbar structure, provides a data path from the inlet port to the outlet port, and takes data out of the data cache module and sends it to the outlet port according to the matching relationship between the inlet port and the outlet port obtained by the data arbitration module.

[0023] Further, the sending scheduling module includes a sending data buffer module and a congestion back pressure processing module;

[0024] The sending data buffer module is used to buffer the data sent from the switching module to prevent the loss of data due to congestion at the network switch outlet;

[0025] The congestion back pressure processing module is used to provide data flow back pressure to the inlet end when the network is congested, so as to maintain the fairness of data transmission of the network switch.

[0026] The invention is beneficial in that the unified switching system for Multi-die packaged chips provided greatly reduces the connections between bare chips of network switching chips under the Multi-die package architecture through methods such as buffer mapping, distributed Crossbar crossbar switches and unified interfaces. The invention establishes a basic and scalable logical framework, which provides a good foundation for realizing high-performance switching networks in Multi-die designs.

[0027] The invention is also beneficial in that the high-performance network exchange framework provided is highly decoupled from the network protocol, and various network protocols can be built on the network exchange framework. At the same time, an efficient and complete cache logic strategy is provided, and an input queue structure, an output queue structure, an input and output combined queue structure, etc. can be used. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0029] Figure 1 This is a schematic diagram of the overall structure of a unified switching system applicable to Multi-die packaged chips of the present invention;

[0030] Figure 2 This is a schematic diagram of the structure of a receiving scheduling module of a unified switching system applicable to a Multi-die packaged chip of the present invention;

[0031] Figure 3 A schematic diagram of parsing information of a receiving data parsing module of a unified switching system applicable to a Multi-die packaged chip of the present invention;

[0032] Figure 4 This is a schematic diagram of the structure of a data cache module of a unified switching system suitable for a Multi-die packaged chip according to the present invention;

[0033] Figure 5 This is a schematic diagram of the structure of a data arbitration module of a unified switching system applicable to a Multi-die packaged chip of the present invention;

[0034] Figure 6 A schematic diagram of the structure of a switching module of a unified switching system applicable to a Multi-die packaged chip according to the present invention;

[0035] Figure 7 The present invention is a schematic diagram of the structure of a sending scheduling module of a unified switching system suitable for Multi-die packaged chips. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0037] The “network protocols” described in this application refer to three common network protocols, namely, Ethernet transmission protocol, Infiniband (IB) transmission protocol and Fibre Channel (FC) transmission protocol.

[0038] Figure 1The present invention shows a unified switching system suitable for Multi-die packaged chips, comprising: a receiving scheduling module, a data cache module, a data arbitration module, a switching module and a sending scheduling module. Specifically, the receiving scheduling module parses the message header of the received network message based on the network protocol of the port, and performs scheduling signal processing based on the parsed destination address. The data cache module maps the cache area between different bare chips and maintains and manages multiple cache addresses. The data cache module caches the network message into the cache area according to the scheduling command of the receiving scheduling module. The data arbitration module performs many-to-one arbitration according to the destination address of the network message to complete the matching of the network switch entrance and exit. The switching module maintains the Crossbar cross switch between the entrance and exit, and establishes the data channel of the corresponding port to transmit data according to the matching of the data arbitration module. The sending scheduling module caches the sent data to prevent data loss caused by port congestion, and maintains fairness among all ports when congestion occurs. Specifically, the sending scheduling module sends a back pressure request to the entrance end according to the network congestion situation, completes a certain congestion buffer, and ensures the fairness of each port under congestion.

[0039] like Figure 2 As shown, as a preferred implementation, the receiving scheduling module includes: a receiving data parsing module and a data cache scheduling module. Among them, the receiving data parsing module is used to determine the validity of the received network message, and parse the destination address in the network message header according to the port network protocol and the relevant delimiter of the network message. The data cache scheduling module manages and maintains the ports of the network switch and their corresponding positions locally and in the south-to-north direction, determines the location of the network message cache according to the destination address of the network message obtained by parsing, and sends the network message to the subsequent cache module.

[0040] Specifically, the receiving data parsing module has a corresponding instantiation deployment on each port in the network switch, which is responsible for parsing the network messages received through each port. The receiving data parsing module supports multiple network protocols, including Ethernet, Infiniband and Fibre Channel, etc. The data packet formats that it can process are as follows: Figure 3As shown. The receiving data parsing module first identifies and verifies the type and correctness of the received network message through a predefined set of keywords and parsing rules. This step ensures the integrity and credibility of the data and provides a basis for subsequent processing. Once the network message is successfully identified, the receiving data parsing module will then extract key information from the message, such as the destination address. The destination address information is crucial to the operation of the network switch because it determines the routing direction of the data packet. The receiving data parsing module passes the parsed destination address information to other modules of the network switch, such as the data cache module mentioned above. This information will be used to guide key operations such as routing decisions, cache management, and flow control of data packets.

[0041] The data cache scheduling module is connected to the receiving data parsing module, and intelligently sends network data packets to the appropriate cache location based on the destination address information in the received network message. The core function of the data cache scheduling module is to determine the specific location where the network message should be cached or the specific path to be sent based on the destination address information. Specifically, after the receiving data parsing module parses the destination address of the network message, the data cache scheduling module will perform the following operations:

[0042] 1. If the egress port pointed to by the destination address is located on the local chip, the network message will be cached in the local cache. This allows the local port to process and forward data efficiently, reducing the delay of data transmission within the chip.

[0043] 2. If the destination address points to an egress port located on the southbound chip, the network message will be sent to the southbound chip-to-chip interaction interface. This operation ensures that data can flow correctly in the southbound direction in the multi-chip system to reach the correct destination.

[0044] 3. If the destination address points to an egress port on the northbound chip, the network message will be sent to the northbound chip-to-chip interaction interface. Similar to the southbound path, this operation ensures that data can flow correctly in the northbound direction in the system.

[0045] The data cache scheduling module uses a full pipeline method to process network messages. This means that in the entire process of receiving, parsing, and scheduling messages, each step is performed continuously without waiting for the previous step to be fully completed. This pipeline processing method greatly improves the speed and efficiency of data processing, ensuring that the network switch can reduce data processing latency while maintaining high throughput.

[0046] like Figure 4As shown, as a preferred embodiment, the data cache module maps the local cache to different bare chips and manages the storage of the local cache, southbound cache and northbound cache at the same time. The data cache module caches the data of the receiving end to their respective caches according to the scheduling instructions given by the receiving scheduling module. Specifically, the data cache module is responsible for managing and maintaining multiple caches inside the network switch, including local cache, southbound cache and northbound cache. The data cache module schedules the storage of network messages by receiving control information to ensure efficient processing of data streams. During normal operation, when each cache area has free capacity, the data cache management module will decide which cache to write the network message to according to the cache command provided by the receiving data scheduling module. This process involves the dynamic allocation of network messages to optimize the use of cache resources and improve the speed and efficiency of data processing. In the case of high network load or tight cache resources, the data cache module has the function of monitoring the cache capacity and can issue a notification in time when insufficient cache is detected. This mechanism can instruct the data source to pause or slow down the data sending rate by sending a signal or command back to the source address when the cache is about to be full. This back pressure measure is dynamic and can be adjusted according to the current status and performance indicators of the network switch to ensure the stable operation of the network. The data cache module is equipped with a read-write pointer RD_POINT / WR_POINT, which is used to indicate the cache address of the receiving end data and the cache address of the data given to the next module.

[0047] like Figure 5 As shown, as a preferred implementation, the data arbitration module includes: a request sending module and an arbitration processing module. Among them, it is used to receive the destination address information obtained by the receiving data parsing module in the receiving scheduling module, and send a data sending request to each exit port. The request sending module decides whether to issue an arbitration request based on the destination address of the network message of each port and the cache status of its destination port, and at the same time, performs no request processing for the port that has not issued a request. The arbitration processing module collects the requests sent by each port, and according to the principle of fair polling, sends a signal to each request end whether to authorize. For unicast data, one exit port only sends an authorization signal to one entry port to establish a conflict-free match between the entry port and the exit port.

[0048] The request sending module is configured at each inlet of the network switch. Each request sending module contains and maintains a routing table, which records the mapping information of the destination address to the outlet, so that each request sending module can determine the corresponding outlet according to the destination address of the data packet. When the data packet arrives at the inlet, the request sending module resolves the destination address in the data packet by querying the maintained routing table. The resolution process involves matching the destination address with the record in the routing table to determine the specific outlet to which the data packet should be sent. Once the outlet corresponding to the destination address is determined, the request sending module initiates a matching request to the outlet so as to correctly route the data packet to its final destination. In addition, since each request sending module independently maintains its own routing table, such a distributed architecture improves the scalability and fault tolerance of the system because it allows the routing table of a single inlet to be updated or modified without affecting other parts of the network switch. In an embodiment, the routing table can be updated regularly or as needed to reflect changes in the network topology or optimize routing decisions.

[0049] The arbitration processing module is configured at multiple exit ports to achieve effective management of data flow. Specifically, each entry port is designed with the ability to send a data transmission request to the corresponding exit port, wherein the request may be a request for data transmission or a non-request signal. The arbitration processing module is responsible for receiving and sorting these data transmission requests from each entry port for unified processing. After collecting and sorting the data transmission requests issued by all entry ports, the arbitration processing module adopts an algorithm based on a fair polling strategy to determine the authorization of the request. The fair polling strategy ensures that each request has an equal chance of being authorized, thereby achieving fairness in request processing. Once the request of a certain entry port is authorized, the entry port will be allowed to send data to its corresponding exit port in the subsequent data transmission cycle. In order to maintain the fairness and efficiency of the entire system, the authorized entry port will be given the lowest priority in the subsequent arbitration cycle after its request is satisfied. This means that the entry port will be the last port considered for authorization in the next round of arbitration processing, unless no other entry port issues a data transmission request. This mechanism ensures balance in long-term operation and avoids continuous preference for any single entry port, thereby enhancing the performance and stability of the entire system. The arbitration processing module inserts a no request flag for the entry that has not sent a request.

[0050] like Figure 6As shown, as a preferred implementation, the switching module realizes efficient data exchange through the Crossbar structure. The Crossbar structure provides a flexible cross-connection relationship between all inlet ports and outlet ports in the network switch, thereby realizing a data path from any inlet port to any outlet port. Specifically, the switching module includes multiple crosspoints, each of which can be independently configured to connect a certain inlet port to a certain outlet port. During the data transmission process, the data arbitration module determines the matching relationship between each inlet port and outlet port according to network traffic, priority and other strategies. Once the arbitration module determines the matching relationship, the switching module establishes a data path from the inlet port to the outlet port by configuring the corresponding crosspoints according to this decision. When the data path is established, the switching module will take out the corresponding network data packet from the data cache module and send it to the target outlet port through the aforementioned established data path. The data transmission operation involved in this process is managed by the control logic inside the switching module to ensure that the data packet can be quickly and accurately taken out of the cache and delivered to the specified outlet port. The design of the switching module allows multiple data paths to exist simultaneously and operate independently, so that multiple data packets can be transmitted in parallel, greatly improving the data processing capability and efficiency of the network switch. In addition, the use of the Crossbar structure also improves the flexibility of network switches in handling various communication modes, including point-to-point, multicast and multicast.

[0051] like Figure 7 As shown, as a preferred embodiment, the sending scheduling module includes a sending data cache module and a congestion back pressure processing module. The sending data cache module independently manages a data cache, which is used to cache the network messages transmitted from the switching module to prevent data loss due to congestion at the network switch outlet. The congestion back pressure module is used to back pressure the data at the outlet to the inlet when the network is congested, and the back pressure signal acts on the arbitration module to maintain the fairness of the network switch.

[0052] The send data buffer module is set at each outlet of the network switch. The send data buffer module is designed to buffer the data sent from the switch module. The main purpose of this module is to prevent data loss when congestion occurs at the outlet of the network switch. By providing a buffer area at the outlet, when the outlet cannot process all the incoming data due to instantaneous traffic peak or other reasons, the send data buffer module can temporarily store the data. In this way, once the outlet is able to process the data again, the data in the buffer can be sent smoothly, thereby avoiding data loss that may occur due to congestion.

[0053] The congestion back pressure processing module can apply back pressure to the data flow at the inlet port when the network congestion is detected. This back pressure mechanism can reduce the amount of data sent to the congested area, thereby alleviating the congestion. The congestion back pressure processing module dynamically adjusts the rate at which data flows to these outlets by monitoring the flow conditions of each outlet port of the network switch. In addition, the module is also responsible for maintaining the fairness of data transmission of the network switch, ensuring that certain data flows or inlet ports are not treated unfairly when back pressure is performed.

[0054] The combined use of the sending data buffer module and the congestion back pressure processing module of the present invention not only improves the robustness of the network switch when facing high traffic pressure, but also ensures that the network switch can process data fairly and efficiently under different network conditions through an effective congestion management mechanism.

[0055] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A unified switching system suitable for Multi-die packaged chips, characterized in that: It includes: receiving scheduling module, data buffering module, data arbitration module, switching module and sending scheduling module; The receiving scheduling module is used to parse the message header of the received network message and perform scheduling signal processing based on the parsed destination address; The data cache module is used to cache the network message into the cache area according to the scheduling command of the receiving scheduling module; The data arbitration module is used to perform many-to-one arbitration according to the destination address of the network message to complete the matching of the egress and ingress of the network switch; The switching module establishes a data channel of a corresponding port to transmit data according to the matching of the data arbitration module; The sending scheduling module is used to send a back pressure request to the inlet end according to the network congestion situation, complete a certain congestion buffer, and ensure the fairness of each port under congestion conditions; The data arbitration module includes a request sending module and an arbitration processing module; The request sending module is used to receive the destination address information obtained by the receiving data parsing module in the receiving scheduling module, and send a data sending request to each export end; The arbitration processing module is used to collect requests initiated by each inlet at each outlet, and to determine the validity of all collected requests. When a request of an inlet is authorized, the inlet will be allowed to send data to its corresponding outlet in the subsequent data transmission cycle, and the authorized inlet will be given the lowest priority in the subsequent arbitration cycle after its request is satisfied, and a no-request mark is inserted for the inlet that has not sent a request; The switching module establishes a cross-connection relationship between all inlet ports and outlet ports through a crossbar structure, provides a data path from the inlet port to the outlet port, and takes data out of the data cache module and sends it to the outlet port according to the matching relationship between the inlet port and the outlet port obtained by the data arbitration module; The sending scheduling module includes a sending data buffer module and a congestion back pressure processing module; The sending data buffer module is used to buffer the data sent from the switching module to prevent the loss of data due to congestion at the network switch outlet; The congestion back pressure processing module is used to provide data flow back pressure to the inlet end when the network is congested, so as to maintain the fairness of data transmission of the network switch.

2. The unified switching system applicable to Multi-die packaged chips according to claim 1, characterized in that: The receiving scheduling module includes a receiving data parsing module and a data cache scheduling module; The received data parsing module is used to determine the validity of the received network message and parse the destination address in the network message header; The data cache scheduling module is used to determine the address of the network message cache according to the destination address of the network message obtained by parsing, and send the network message to the subsequent data cache module.

3. The unified switching system applicable to Multi-die packaged chips according to claim 2, characterized in that: The data cache scheduling module sends the messages with destination addresses of different chips to the local chip, the southbound chip and the northbound chip respectively.

4. The unified switching system applicable to Multi-die packaged chips according to claim 1, characterized in that: The data cache module performs unified resource management on the local cache, southbound cache and northbound cache, and sends a back pressure request to the port in time when the cache resources are insufficient to prevent data loss.

5. The unified switching system applicable to Multi-die packaged chips according to claim 4, characterized in that: The data cache module maps the local cache to different bare chips and manages the storage conditions of the local cache, southbound cache and northbound cache.

6. The unified switching system applicable to Multi-die packaged chips according to claim 4, characterized in that: The data cache module caches the data of the receiving end into respective caches according to the scheduling instructions given by the receiving scheduling module.

7. The unified switching system applicable to Multi-die packaged chips according to claim 6, characterized in that: The data cache module is provided with a read-write pointer RD_POINT / WR_POINT, which is used to indicate the cache address of the receiving end data and the cache address of the data given to the next module.

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