Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for preparing the same, the method comprising: providing a substrate, forming a drift region in the substrate; forming a plurality of channel spacing regions in the drift region, with a spacing between every two channel spacing regions to form a channel region; forming a source contact region, a drain contact region and a gate contact region in the drift region, and forming a substrate contact region in the substrate, with the substrate contact region and the drift region being spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel region connects the source contact region and the drain contact region. The scheme of the present invention forms a plurality of channel spacing regions, with a spacing between every two channel spacing regions to form a channel region, and can adjust the pinch-off voltage of the device by adjusting the width of the channel region while ensuring that the device has a sufficiently high on-current when it is turned on, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the continuous development of integrated circuits, in order to save area, multiple devices are often prepared on the same substrate at the same time. For example, in the BCD (Bipolar-CMOS-DMOS) process, high-voltage power devices such as bipolar, complementary metal oxide semiconductor (CMOS) and diffused metal oxide semiconductor (DMOS) can be prepared on the same substrate. The BCD process has been widely used in mobile devices, home appliances, displays, automobiles, data centers and other fields.

[0003] The Junction Field Effect Transistor (JFET) is a device commonly used in the BCD process. It has a very high input impedance, allowing a high degree of isolation between the input and output circuits, without the inherent noise of electron tubes and transistors, and can avoid the risk of thermal runaway due to its negative temperature coefficient. In addition, it also has a very high power gain.

[0004] In JFET, pinch-off voltage is a very important parameter, which plays a key role in regulating the current from source to drain and controlling the working state of JFET. However, the pinch-off voltage of JFET in related art is generally not adjustable, or, although the pinch-off voltage can be adjusted, when the pinch-off voltage is small, the on-current of JFET is low, which leads to an increase in the on-resistance of JFET, thereby increasing the power consumption of JFET in practical applications and reducing the performance of the device. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In view of the existing problems, the present invention provides a method for preparing a semiconductor device, comprising:

[0007] a substrate having a first conductivity type;

[0008] A drift region extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type;

[0009] A plurality of channel spacers, located in the drift region and exposed to the first surface, wherein a gap exists between each two adjacent channel spacers to form a channel region, and the channel spacers have a first conductivity type;

[0010] A source contact region, a drain contact region and a gate contact region are located in the drift region, the gate contact region is located between the source contact region and the drain contact region, the channel region is connected to the source contact region and the drain contact region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type;

[0011] A substrate contact region is located in the substrate and is spaced apart from the drift region, and the substrate contact region has the first conductivity type.

[0012] In one embodiment, the drain contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or,

[0013] The source contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

[0014] In one embodiment, the semiconductor device further comprises:

[0015] A first field oxide layer and a second field oxide layer are located in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region;

[0016] A first gate structure and a second gate structure, wherein the first gate structure is located on the first field oxide layer and partially extends onto the drift region, and the second gate structure is located on the first field oxide layer and on a side of the first gate structure close to the drain contact region.

[0017] In one embodiment, the second gate structure is a floating gate structure.

[0018] In one embodiment, the semiconductor device also includes a source gradual change region and a drain gradual change region located in the drift region, the source contact region is located in the source gradual change region, the drain contact region is located in the drain gradual change region, and the source contact region and the drain contact region have the second conductivity type.

[0019] Another aspect of an embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0020] providing a substrate having a first conductivity type;

[0021] forming a drift region in the substrate extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type;

[0022] forming a plurality of channel spacer regions of the first conductivity type in the drift region, wherein a gap exists between every two of the channel spacer regions to form a channel region;

[0023] A source contact region, a drain contact region and a gate contact region with a first conductivity type are formed in the drift region, and a substrate contact region with a first conductivity type is formed in the substrate, wherein the substrate contact region and the drift region are spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel region connects the source contact region and the drain contact region.

[0024] In one embodiment, the drain contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or,

[0025] The source contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

[0026] In one embodiment, the method further comprises:

[0027] forming a first field oxide layer and a second field oxide layer in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region;

[0028] A first gate structure and a second gate structure are formed, wherein the first gate structure is located on the first field oxide layer and partially extends onto the drift region, and the second gate structure is located on the first field oxide layer and on a side of the first gate structure close to the drain contact region.

[0029] In one embodiment, the second gate structure is a floating gate structure.

[0030] In one embodiment, before forming the source contact region and the drain contact region, the method further includes:

[0031] A source graded region and a drain graded region of the second conductivity type are formed in the drift region, the source contact region is located in the source graded region, and the drain contact region is located in the drain graded region.

[0032] The semiconductor device and preparation method of the embodiment of the present invention form a plurality of channel spacer regions, wherein there is a gap between each two adjacent channel spacer regions to form a channel region, and each channel region can be pinched off from two directions. While adjusting the pinch-off voltage of the device by adjusting the width of the channel region, it is possible to ensure that the device has a sufficiently high on-current when it is turned on, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0034] In the attached figure:

[0035] Figure 1 A flowchart showing a method for preparing a semiconductor device according to a specific embodiment of the present invention is shown;

[0036] Figure 2A-2J A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for preparing a semiconductor device according to a specific embodiment of the present invention is shown;

[0037] Figure 3 A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for preparing a semiconductor device according to another specific embodiment of the present invention is shown;

[0038] Figure 4 A schematic diagram of a layout of a semiconductor device obtained by sequentially implementing a method for preparing a semiconductor device according to a specific embodiment of the present invention is shown;

[0039] Figure 5 A schematic top view of a semiconductor device when pinched off according to a specific embodiment of the present invention is shown;

[0040] Figure 6 A schematic top view of a semiconductor device when it is pinched off according to another specific embodiment of the present invention is shown;

[0041] Figure 7 A cross-sectional schematic diagram of a semiconductor device when pinched off according to a specific embodiment of the present invention is shown;

[0042] Figure 8 A cross-sectional schematic diagram of a semiconductor device according to another specific embodiment of the present invention is shown;

[0043] Fig. 9 A cross-sectional schematic diagram of a semiconductor device when pinched off according to another specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0044] Next, the present invention will be more fully described in conjunction with the accompanying drawings, in which embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0045] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0046] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present invention. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined as such herein.

[0050] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0051] In view of the existence of the aforementioned technical problems, an embodiment of the present invention provides a semiconductor device, comprising: a substrate, the substrate having a first conductivity type;

[0052] A drift region extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type;

[0053] A plurality of channel spacers, located in the drift region and exposed to the first surface, wherein a gap exists between each two adjacent channel spacers to form a channel region, and the channel spacers have a first conductivity type;

[0054] A source contact region, a drain contact region and a gate contact region are located in the drift region, the gate contact region is located between the source contact region and the drain contact region, the channel region is connected to the source contact region and the drain contact region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type;

[0055] A substrate contact region is located in the substrate and is spaced apart from the drift region, and the substrate contact region has the first conductivity type.

[0056] The present invention also provides a method for preparing a semiconductor device, which mainly comprises the following steps:

[0057] Providing a substrate, the substrate having a first conductivity type, and forming a drift region having a second conductivity type extending from a first surface of the substrate into the substrate;

[0058] forming a plurality of channel spacer regions of a first conductivity type in the drift region, wherein a gap exists between each two adjacent channel spacer regions to form a channel region;

[0059] A source contact region, a drain contact region and a gate contact region with a first conductivity type are formed in the drift region, and a substrate contact region with a first conductivity type is formed in the substrate and extends from the first surface of the substrate to the substrate, the substrate contact region and the drift region are spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel region connects the source contact region and the drain contact region.

[0060] The semiconductor device and preparation method of the embodiment of the present invention form a plurality of channel spacer regions, wherein there is a space between each two adjacent channel spacer regions to form a channel region, and each channel region is connected to a source contact region and a drain contact region to form a current channel. The device can adjust the pinch-off voltage of the device by adjusting the width of the channel region, while ensuring that the device has a sufficiently high on-current when it is turned on, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the device performance.

[0061] Embodiment 1

[0062] Below, reference Figures 1 to 9 The method for preparing the semiconductor device of the present invention is described in detail, wherein: Figure 1A flowchart of a method for preparing a semiconductor device according to a specific embodiment of the present invention is shown. Figure 2A-2J A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for preparing a semiconductor device according to a specific embodiment of the present invention is shown; Figure 3 A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for preparing a semiconductor device according to another specific embodiment of the present invention is shown; Figure 4 A schematic diagram of a layout of a semiconductor device obtained by sequentially implementing a method for preparing a semiconductor device according to a specific embodiment of the present invention is shown. Figure 5 FIG. 1 is a schematic top view of a semiconductor device when it is pinched off according to a specific embodiment of the present invention. Figure 6 FIG. 1 is a top view schematic diagram of a semiconductor device when it is pinched off according to another specific embodiment of the present invention, Figure 7 FIG. 1 is a cross-sectional schematic diagram of a semiconductor device when pinched off according to a specific embodiment of the present invention, Figure 8 A cross-sectional schematic diagram of a semiconductor device according to another specific embodiment of the present invention is shown. Fig. 9 A cross-sectional schematic diagram of a semiconductor device when pinched off according to another specific embodiment of the present invention is shown.

[0063] Illustratively, the method for preparing a semiconductor device according to an embodiment of the present invention comprises the following steps:

[0064] First, step S1 is performed to provide a substrate, wherein the substrate has a first conductivity type; and a drift region having a second conductivity type is formed in the substrate and extends from a first surface of the substrate to the inside of the substrate.

[0065] Exemplarily, the semiconductor device of the present application includes a JFET device, and the semiconductor device may be any suitable device known to those skilled in the art. In this embodiment, the technical solution of the present application is mainly explained and illustrated by taking the case where the semiconductor device is a JFET device as an example.

[0066] In one example, if Figure 2A As shown, the substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 200 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 200 are described herein, any material that can be used as the substrate 200 falls within the spirit and scope of the present application.

[0067] Exemplarily, the substrate 200 includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. Optionally, the semiconductor substrate and the epitaxial layer may have the same conductivity type. Exemplarily, the semiconductor substrate and the epitaxial layer may have different doping concentrations, for example, the doping concentration of the epitaxial layer may be lower than the doping concentration of the semiconductor substrate. Exemplarily, the substrate 200 has a first conductivity type, the first conductivity type may be N-type, or the first conductivity type may also be P-type.

[0068] In one example, if Figure 2A As shown, before forming the drift region 202, it also includes: forming a shallow trench isolation structure 201. Exemplarily, forming the shallow trench isolation structure 201 may include the following steps: etching the substrate 200 to a certain depth from the first surface of the substrate 200 to form a shallow trench; forming a silicon oxide layer in the shallow trench to form the shallow trench isolation structure 201. Exemplarily, the shallow trench isolation structure 201 is located between the active regions of the device.

[0069] In one example, if Figure 2B As shown, a drift region 202 having a second conductivity type is formed in the substrate 200 and extends from the first surface of the substrate 200 to the substrate 200. Specifically, the drift region 202 can be formed by the following steps: forming a patterned mask layer on the first surface of the substrate 200; performing an ion implantation process with the mask layer as a mask to form the drift region 202; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, when the first conductivity type is a P-type conductivity type, the second conductivity type is an N-type conductivity type; when the first conductivity type is an N-type conductivity type, the second conductivity type is a P-type conductivity type. Exemplarily, the doping concentration of the drift region 202 is greater than the doping concentration of the substrate 200, and therefore has a lower resistivity. Exemplarily, the drift region 202 is located in the active region of the device.

[0070] like Figure 2D As shown, after forming the drift region 202 and before performing step S2, the method of the present application further includes: forming a first injection region 204 in the drift region 202, and the first injection region 204 has a second conductivity type. Specifically, the first injection region 204 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process with the mask layer as a mask to form the first injection region 204; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the doping concentration of the first injection region 204 is greater than the doping concentration of the drift region 202, which can further reduce the resistivity.

[0071] Next, step S2 is performed to form a plurality of channel spacer regions of the first conductivity type in the drift region, wherein a gap exists between every two adjacent channel spacer regions to form a channel region.

[0072] Specifically, Figure 2E , Figure 4 as well as Figure 5 , Figure 6 As shown, a plurality of channel spacers 205 having a first conductivity type are formed in the drift region 202, the plurality of channel spacers 205 are exposed to the first surface of the substrate, and are arranged at intervals along the first surface of the substrate; there is a gap between every two adjacent channel spacers 205 to form a channel region, and when a first injection region 204 is formed in the drift region 202, the gap between every two channel spacers 205 is the first injection region 204, or the first injection region 204 between every two channel spacers 205 is the channel region.

[0073] In one example, if Figure 2E As shown, the channel spacer 205 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the channel spacer 205; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer.

[0074] In one example, if Figure 2E and Figure 5 , Figure 6 As shown, the depth of the channel spacer 205 is less than the depth of the drift region 202. Furthermore, the depth of the channel spacer 205 is also less than the depth of the first implant region 204. In this case, the first implant region 204 and the drift region 202 between the channel spacer 205 and the substrate 200 are also channel regions. In other examples, the depth of the channel spacer 205 may also be greater than or equal to the depth of the drift region 202. In this case, the channel region is located between two adjacent channel spacers 205.

[0075] Next, execute step S3, such as Figure 2H As shown, a source contact region 211 and a drain contact region 210 of the second conductivity type are formed in the drift region, and the channel region connects the source contact region 211 and the drain contact region 210. Specifically, the source contact region 211 and the drain contact region 210 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the source contact region 211 and the drain contact region 210; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer.

[0076] like Fig.2IAs shown, a gate contact region 212 having a first conductivity type is formed in the drift region, and a substrate contact region 213 having a first conductivity type is formed in the substrate 200 and extends from the first surface of the substrate 200 to the substrate 200, wherein the gate contact region 212 is located between the source contact region 211 and the drain contact region 210, and the substrate contact region 213 and the drift region 202 are spaced apart from each other. Specifically, the gate contact region 212 and the substrate contact region 213 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the gate contact region 212 and the substrate contact region 213; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the source contact region 211, the drain contact region 210, the gate contact region 212 and the substrate contact region 213 are all heavily doped regions, so that the contact resistance can be effectively reduced when they are subsequently electrically connected to the contact plug 214. Exemplarily, the substrate contact region 213 is located between the shallow trench isolation structures 201 .

[0077] In one example, if Figure 2C and Figure 2G As shown, the method of the present application also includes: forming a first field oxide layer 2031 and a second field oxide layer 2032 in the drift region 202, wherein the first field oxide layer 2031 is located between the gate contact region 212 and the drain contact region 210, and the second field oxide layer 2032 is located between the gate contact region 212 and the source contact region 211; forming a first gate structure 2091 and a second gate structure 2092, wherein the first gate structure 2091 is located on the first field oxide layer 2031 and partially extends onto the drift region 202, and the second gate structure 2092 is located on the first field oxide layer 2031 and on a side of the first gate structure 2091 close to the drain contact region 210.

[0078] For example, the first field oxide layer 2031 and the second field oxide layer 2032 may be formed by any suitable method known to those skilled in the art, for example, by thermal oxidation.

[0079] Exemplarily, the first gate structure 2091 and the second gate structure 2092 both include a gate layer and sidewalls located on both sides of the gate layer. Exemplarily, the gate layer is composed of polysilicon material, and metal, metal nitride, metal silicide or similar compounds can generally be used as the material of the gate layer. Exemplarily, the material of the sidewall includes insulating materials such as silicon nitride, silicon oxide or silicon oxynitride, and the sidewall can be a single-layer structure or a multi-layer structure.

[0080] In one example, if Figure 2JAs shown, the gate contact region 212 and the first gate structure 2091 are electrically connected to the same external metal layer through contact plugs to form a gate, that is, the gate contact region 212 and the first gate structure 2091 are electrically connected through the contact plugs, so that when a bias voltage is applied to the gate, the first gate structure 2091 and the first field oxide layer 2031 can form a bias field plate structure to increase the average electric field of the drift region 202 and reduce the electric field peak, thereby achieving the purpose of suppressing the hot carrier effect and improving the breakdown voltage. Exemplarily, the second gate structure 2092 is a floating gate structure, that is, the second gate structure 2092 does not need to be connected to an external electrode, and the second gate structure 2092 can form a floating field plate structure with the first field oxide layer 2031, so that the electric field distribution in the drift region 202 is more uniform, ensuring that the corner where the electric field is concentrated is not easy to be broken down, thereby further improving the breakdown voltage.

[0081] In one example, if Figure 2J As shown, the contact plug 214 is also electrically connected to the source contact region 211 and the external metal layer to form a source, the contact plug 214 is also electrically connected to the drain contact region 210 and the external metal layer to form a drain, and the contact plug 214 is also electrically connected to the substrate contact region 213 and the external metal layer to lead out the substrate 200 to form a substrate terminal. Exemplarily, the material of the contact plug 214 includes but is not limited to copper, tungsten, gold, silver, aluminum, etc.

[0082] In one example, if Figure 2F As shown, before forming the source contact region 211 and the drain contact region 210, the method of the present application further includes: forming a source gradual change region 208 and a drain gradual change region 207 having a second conductivity type in the drift region 202, the source contact region 211 is located in the source gradual change region 208, and the drain contact region 210 is located in the drain gradual change region 207. Specifically, the source gradual change region 208 and the drain gradual change region 207 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the source gradual change region 208 and the drain gradual change region 207; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the doping concentration of the source gradual change region 208 is less than the doping concentration of the source contact region 211, and the doping concentration of the drain gradual change region 207 is less than the doping concentration of the drain contact region 210. By forming the source gradual change region 208 and the drain gradual change region 207, the antistatic performance of the device can be increased, and the phenomenon of excessive carrier concentration can be effectively changed, thereby effectively alleviating the thermoelectric effect. Exemplarily, the first field oxide layer 2031 and the second field oxide layer 2032 can be formed first, and then the source gradual change region 208 and the drain gradual change region 207 are formed, and then the first gate structure 2091 and the second gate structure 2092 are formed.

[0083] In one example, if Figure 2EAs shown, the method of the present application also includes: forming a second implantation region 206 in the substrate 200, and the substrate contact region 213 is located in the second implantation region 206. Specifically, the second implantation region 206 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process with the mask layer as a mask to form the second implantation region 206; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the second implantation region 206 has a first conductivity type.

[0084] In one example, the comprehensive Figure 2J and Figure 4 As shown, the drain contact region 210 and the gate contact region 212 are ring-shaped, the gate contact region 212 surrounds the outside of the source contact region 211, and the drain contact region 210 surrounds the outside of the gate contact region 212; or, as shown Figure 3 As shown, the source contact region 211 and the gate contact region 212 are ring-shaped, the gate contact region 212 surrounds the outside of the drain contact region 210, and the source contact region 211 surrounds the outside of the gate contact region 212, wherein, Figure 3 The cross-sectional view of a semiconductor device obtained by another embodiment of the present application is shown, which can achieve the same Figure 2A-2J The semiconductor device obtained has the same function. This overall ring-shaped surrounding structure can effectively save the area of ​​the device. For example, at this time, the first gate structure 2091 and the second gate structure 2092 are also ring-shaped structures. For example, Figure 5 As shown, the gate contact region 212 may also be located in the channel spacer region 205 instead of in the first implantation region 204. In this case, the gate contact region 212 is in the shape of a ring with intervals arranged therebetween.

[0085] In one example, each region formed by the ion implantation process is subjected to a rapid temperature rise annealing process immediately after the ion implantation process to activate the dopants in the ion implanted region and simultaneously repair the lattice structure damaged in the ion implantation process.

[0086] In one example, the pinch-off voltage of the device may be adjusted by adjusting the width of the channel region between the channel spacers 205 to meet actual requirements.

[0087] In one example, if Figure 5 As shown, the gate contact region 212 may be located in the channel spacer region 205 instead of in the first implant region 204. Alternatively, as shown in FIG. Figure 6 As shown, the gate contact region 212 may be located in the channel spacer region 205 and the first implant region 204 .

[0088] In one example, if Figure 4 and Figure 5 , Figure 6As shown, taking the case where the first conductivity type is P-type conductivity type and the second conductivity type is N-type conductivity type as an example, when the reverse bias voltage is not applied to the gate and the substrate end, the current can flow from the source through the channel region between the channel spacer regions 205 to the drain. Since the present application forms channel regions between the channel spacer regions 205, multiple current channels can be formed, thereby ensuring that the device can still have a higher on-current when having a smaller pinch-off voltage, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the device performance. When the reverse bias voltage is applied to the gate and the substrate end, the depletion layer between the channel spacer region 205 and the channel region gradually widens until it completely covers the channel region. At this time, the channel region is pinched off and the device is also in a pinch-off state. Figure 5 and Figure 6 The arrow shown in the figure is the direction in which the depletion layer pinches off the channel region.

[0089] For example, Figure 7 As shown, when the depth of the channel spacer 205 is less than the depth of the drift region 202, a channel region can also be formed between the channel spacer 205 and the substrate 200, and the channel region between the channel spacer 205 and the substrate 200 can also form a current channel, thereby further improving the on-current of the device. Figure 7 The arrow in is the direction in which the depletion layer pinches off the channel region between the channel spacer region 205 and the substrate 200. For example, Figure 8 As shown, when the depth of the channel spacer region 205 is equal to or greater than the depth of the drift region 202 , a channel region cannot be formed between the channel spacer region 205 and the substrate 200 .

[0090] In addition, if Fig. 9 As shown, when the gate contact region 212 is located in the channel spacer 205 and the first injection region 204, between adjacent channel spacers 205, the conductivity types of the gate contact region 212 and the substrate 200 are both P-type, and the conductivity type of the first injection region 204 between the two is N-type, so a channel region can also be formed between the gate contact region 212 and the substrate 200. Specifically, the first injection region 204 between the gate contact region 212 and the substrate 200 can form a channel region, and the channel region between the gate contact region 212 and the substrate 200 is pinched off simultaneously by the gate contact region 212 and the substrate 200 and the channel spacers 205 on both sides of the first injection region 204. Fig. 9 The arrow in is the direction in which the depletion layer pinches off the channel region between the gate contact region 212 and the substrate 200 .

[0091] So far, the description of the key steps of the method for preparing the semiconductor device of the present invention has been completed. The preparation of a complete semiconductor device may also include other steps, which will not be described one by one here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0092] In summary, the method for preparing a semiconductor device of an embodiment of the present invention forms a plurality of channel spacers, and there is a space between every two channel spacers to form a channel region, and each channel region is connected to the source contact region and the drain contact region to form a current channel, that is, multiple current channels can be formed, and the pinch-off voltage of the device can be adjusted by adjusting the width of the channel region, while ensuring that the device has a sufficiently high on-current when it is turned on, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the device performance. Exemplarily, when the depth of the channel spacer is less than the depth of the drift region, a channel region is also formed between the channel spacer and the substrate, and a current channel can also be formed, thereby further improving the on-current of the device. Exemplarily, the drain contact region and the gate contact region are annular, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or, the source contact region and the gate contact region are annular, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region. This annular surrounding structure can effectively save the area of ​​the device. Exemplarily, the second gate structure can form a biased field plate structure with the first field oxide layer, which can increase the average electric field in the drift region and reduce the electric field peak, thereby achieving the purpose of suppressing the hot carrier effect and increasing the breakdown voltage; the second gate structure can form a floating field plate structure with the first field oxide layer, so that the electric field distribution in the drift region is more uniform, ensuring that the corners where the electric field is concentrated are not easily broken down, thereby further increasing the breakdown voltage.

[0093] Embodiment 2

[0094] The present invention also provides a semiconductor device, which can be prepared by the method in the above-mentioned embodiment 1. Specifically, Figure 2J As shown, the semiconductor device comprises:

[0095] A substrate 200, the substrate 200 has a first conductivity type;

[0096] A drift region 202 extending from the first surface of the substrate 200 into the substrate 200 , and the drift region 202 has a second conductivity type;

[0097] A plurality of channel spacers 205 are located in the drift region 202 and exposed to the first surface of the substrate, and there is a gap between every two channel spacers 205 to form a channel region. The channel spacers 205 have a first conductivity type;

[0098] The source contact region 211, the drain contact region 210 and the gate contact region 212 are located in the drift region 202, the gate contact region 212 is located between the source contact region 211 and the drain contact region 210, the channel region connects the source contact region 211 and the drain contact region 210, the source contact region 211 and the drain contact region 210 have the second conductivity type, and the gate contact region 212 has the first conductivity type;

[0099] The substrate contact region 213 extends from the first surface of the substrate 200 into the substrate 200 and is spaced apart from the drift region 202 . The substrate contact region 213 has a first conductivity type.

[0100] Exemplarily, the substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 200 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 200 are described herein, any material that can be used as the substrate 200 falls within the spirit and scope of the present application.

[0101] Exemplarily, the first conductivity type may be N-type, and the second conductivity type may be P-type; or the first conductivity type may also be P-type, and the second conductivity type may be N-type.

[0102] In one example, if Figure 2J As shown, the semiconductor device of the present application further includes a first implantation region 204 located in the drift region 202, and the first implantation region 204 has a second conductivity type. Exemplarily, when the first implantation region 204 is formed in the drift region 202, the interval between every two channel spacer regions 205 is the first implantation region 204, or the first implantation region 204 between every two channel spacer regions 205 is the channel region.

[0103] In one example, the depth of the channel spacer 205 is less than the depth of the drift region 202. Furthermore, the depth of the channel spacer 205 is also less than the depth of the first implant region 204. In this case, the first implant region 204 and the drift region 202 between the channel spacer 205 and the substrate 200 are also channel regions. In other examples, the depth of the channel spacer 205 may also be greater than or equal to the depth of the drift region 202.

[0104] In one example, the semiconductor device of the present application further includes a shallow trench isolation structure 201, and the shallow trench isolation structure 201 is located between the active regions of the device. Exemplarily, the substrate contact region 213 is located between the shallow trench isolation structures 201. Exemplarily, the drift region 202 is located in the active region of the device.

[0105] In one example, the semiconductor device of the present application also includes a first field oxide layer 2031 and a second field oxide layer 2032 located in the drift region 202, wherein the first field oxide layer 2031 is located between the gate contact region 212 and the drain contact region 210, and the second field oxide layer 2032 is located between the gate contact region 212 and the source contact region 211; at the same time, the semiconductor device of the present application also includes a first gate structure 2091 and a second gate structure 2092, wherein the first gate structure 2091 is located on the first field oxide layer 2031 and partially extends onto the drift region 202, and the second gate structure 2092 is located on the first field oxide layer 2031 and on the side of the first gate structure 2091 close to the drain contact region 210.

[0106] In one example, both the first gate structure 2091 and the second gate structure 2092 include a gate layer and sidewalls located on both sides of the gate layer.

[0107] In one example, the gate contact region 212 and the first gate structure 2091 are respectively electrically connected to the same external metal layer through a contact plug to form a gate, that is, the gate contact region 212 and the first gate structure 2091 are electrically connected through the contact plug, so that when a bias voltage is applied to the gate, the first gate structure 2091 and the first field oxide layer 2031 can form a bias field plate structure to increase the average electric field of the drift region 202 and reduce the electric field peak, thereby achieving the purpose of suppressing the hot carrier effect and improving the breakdown voltage. Exemplarily, the second gate structure 2092 is a floating gate structure, that is, the second gate structure 2092 does not need to be connected to an external electrode, and the second gate structure 2092 can form a floating field plate structure with the first field oxide layer 2031, so that the electric field distribution in the drift region 202 is more uniform, ensuring that the corner where the electric field is concentrated is not easily broken down, thereby further improving the breakdown voltage.

[0108] In one example, the gate contact region 212 and the first gate structure 2091 are respectively electrically connected to the same external metal layer through a contact plug to form a gate, that is, the gate contact region 212 and the first gate structure 2091 are electrically connected through the contact plug, so that when a bias voltage is applied to the gate, the first gate structure 2091 and the first field oxide layer 2031 can form a bias field plate structure to increase the average electric field of the drift region 202 and reduce the electric field peak, thereby achieving the purpose of suppressing the hot carrier effect and improving the breakdown voltage. Exemplarily, the second gate structure 2092 is a floating gate structure, that is, the second gate structure 2092 does not need to be connected to an external electrode, and the second gate structure 2092 can form a floating field plate structure with the first field oxide layer 2031, so that the electric field distribution in the drift region 202 is more uniform, ensuring that the corner where the electric field is concentrated is not easily broken down, thereby further improving the breakdown voltage.

[0109] In one example, if Figure 2J As shown, the contact plug 214 is also electrically connected to the source contact region 211 and the external metal layer to form a source, the contact plug 214 is also electrically connected to the drain contact region 210 and the external metal layer to form a drain, and the contact plug 214 is also electrically connected to the substrate contact region 213 and the external metal layer to lead out the substrate 200 to form a substrate terminal. Exemplarily, the material of the contact plug 214 includes but is not limited to copper, tungsten, gold, silver, aluminum, etc.

[0110] In one example, if Figure 2F As shown, the semiconductor device of the present application further includes a source gradual change region 208 and a drain gradual change region 207 located in the drift region 202, a source contact region 211 is located in the source gradual change region 208, a drain contact region 210 is located in the drain gradual change region 207, and the source gradual change region 208 and the drain gradual change region 207 have a second conductivity type. Exemplarily, the doping concentration of the source gradual change region 208 is less than the doping concentration of the source contact region 211, and the doping concentration of the drain gradual change region 207 is less than the doping concentration of the drain contact region 210. By forming the source gradual change region 208 and the drain gradual change region 207, the antistatic performance of the device can be increased, and the phenomenon of excessive concentration of carriers can be effectively changed, thereby effectively alleviating the thermoelectric effect.

[0111] In one example, if Figure 2E As shown, the semiconductor device of the present application further includes a second implantation region 206 , the substrate contact region 213 is located in the second implantation region 206 , and the second implantation region 206 has the first conductivity type.

[0112] In one example, the comprehensive Figure 2J and Figure 4As shown, the drain contact region 210 and the gate contact region 212 are ring-shaped, the gate contact region 212 surrounds the outside of the source contact region 211, and the drain contact region 210 surrounds the outside of the gate contact region 212; or, as shown Figure 3 As shown, the source contact region 211 and the gate contact region 212 are ring-shaped, the gate contact region 212 surrounds the outside of the drain contact region 210, and the source contact region 211 surrounds the outside of the gate contact region 212, wherein, Figure 3 The cross-sectional view of a semiconductor device obtained by another embodiment of the present application is shown, which can achieve the same Figure 2A-2J The semiconductor device obtained has the same function. This overall ring-shaped surrounding structure can effectively save the area of ​​the device. For example, at this time, the first gate structure 2091 and the second gate structure 2092 are also ring-shaped structures. For example, Figure 5 As shown, the gate contact region 212 may also be located in the channel spacer region 205 instead of in the first implantation region 204. In this case, the gate contact region 212 is in the shape of a ring with intervals arranged therebetween.

[0113] In one example, the pinch-off voltage of the device may be adjusted by adjusting the width of the channel region between the channel spacers 205 to meet actual requirements.

[0114] In one example, if Figure 5 As shown, the gate contact region 212 may be located in the channel spacer region 205 instead of in the first implant region 204. Alternatively, as shown in FIG. Figure 6 As shown, the gate contact region 212 may be located in the channel spacer region 205 and the first implant region 204 .

[0115] In one example, if Figure 4 and Figure 5 , Figure 6 As shown, taking the case where the first conductivity type is P-type conductivity type and the second conductivity type is N-type conductivity type as an example, when the reverse bias voltage is not applied to the gate and the substrate end, the current can flow from the source through the channel region between the channel spacer regions 205 to the drain. Since the present application forms channel regions between the channel spacer regions 205, multiple current channels can be formed, thereby ensuring that the device can still have a higher on-current when having a smaller pinch-off voltage, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the device performance. When the reverse bias voltage is applied to the gate and the substrate end, the depletion layer between the channel spacer region 205 and the channel region gradually widens until it completely covers the channel region. At this time, the channel region is pinched off and the device is also in a pinch-off state. Figure 5 and Figure 6 The arrow shown in the figure is the direction in which the depletion layer pinches off the channel region.

[0116] For example, Figure 7As shown, when the depth of the channel spacer 205 is less than the depth of the drift region 202, a channel region can also be formed between the channel spacer 205 and the substrate 200, and the channel region between the channel spacer 205 and the substrate 200 can also form a current channel, thereby further improving the on-current of the device. Figure 7 The arrow in is the direction in which the depletion layer pinches off the channel region between the channel spacer region 205 and the substrate 200. For example, Figure 8 As shown, when the depth of the channel spacer region 205 is equal to or greater than the depth of the drift region 202 , a channel region cannot be formed between the channel spacer region 205 and the substrate 200 .

[0117] In addition, if Fig. 9 As shown, when the gate contact region 212 is located in the channel spacer 205 and the first injection region 204, between adjacent channel spacers 205, the conductivity types of the gate contact region 212 and the substrate 200 are both P-type, and the conductivity type of the first injection region 204 between the two is N-type, so a channel region can also be formed between the gate contact region 212 and the substrate 200. Specifically, the first injection region 204 between the gate contact region 212 and the substrate 200 can form a channel region, and the channel region between the gate contact region 212 and the substrate 200 is pinched off simultaneously by the gate contact region 212 and the substrate 200 and the channel spacers 205 on both sides of the first injection region 204. Fig. 9 The arrow in is the direction in which the depletion layer pinches off the channel region between the gate contact region 212 and the substrate 200 .

[0118] Exemplarily, the semiconductor device of the present application includes a JFET device, and the semiconductor device may be any suitable device known to those skilled in the art. In this embodiment, the technical solution of the application is mainly explained and illustrated by taking the case where the semiconductor device is a JFET device as an example.

[0119] The structure of the semiconductor device of the present invention has been introduced so far. The complete device may also include other component structures, which will not be described in detail here.

[0120] Embodiment 3

[0121] Another embodiment of the present invention provides an electronic device including the aforementioned semiconductor device.

[0122] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including the semiconductor device. The electronic device of the embodiment of the present invention has better performance due to the use of the semiconductor device.

[0123] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed in the present invention. More particularly, various modifications and changes may be made to the arrangements and / or components of the combined arrangements of the subject matter within the scope of the present disclosure, the drawings, and the appended claims. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious option for those skilled in the art.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; A drift region extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type; A plurality of channel spacers, located in the drift region and exposed to the first surface, wherein a gap exists between each two adjacent channel spacers to form a channel region, and the channel spacers have a first conductivity type; A source contact region, a drain contact region and a gate contact region are located in the drift region, the gate contact region is located between the source contact region and the drain contact region, the channel region is connected to the source contact region and the drain contact region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type; a substrate contact region, located in the substrate and spaced apart from the drift region, the substrate contact region having the first conductivity type; A first field oxide layer and a second field oxide layer are located in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region; A first gate structure and a second gate structure, wherein the first gate structure is located on the first field oxide layer and partially extends onto the drift region, and the second gate structure is located on the first field oxide layer and on a side of the first gate structure close to the drain contact region.

2. The semiconductor device according to claim 1, wherein: The drain contact region and the gate contact region are in a ring shape, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or, The source contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

3. The semiconductor device according to claim 1, wherein: The second gate structure is a floating gate structure.

4. The semiconductor device according to claim 1, wherein: It also includes a source gradual change region and a drain gradual change region located in the drift region, the source contact region is located in the source gradual change region, the drain contact region is located in the drain gradual change region, and the source contact region and the drain contact region have the second conductivity type.

5. A method for preparing a semiconductor device, characterized in that: The method comprises: providing a substrate having a first conductivity type; forming a drift region in the substrate extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type; forming a plurality of channel spacer regions of the first conductivity type in the drift region, wherein a gap exists between every two of the channel spacer regions to form a channel region; A source contact region, a drain contact region and a gate contact region of the first conductivity type are formed in the drift region, and a substrate contact region of the first conductivity type is formed in the substrate, wherein the substrate contact region and the drift region are spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel region communicates with the source contact region and the drain contact region; The method further comprises: forming a first field oxide layer and a second field oxide layer in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region; A first gate structure and a second gate structure are formed, wherein the first gate structure is located on the first field oxide layer and partially extends onto the drift region, and the second gate structure is located on the first field oxide layer and on a side of the first gate structure close to the drain contact region.

6. The preparation method according to claim 5, characterized in that: The drain contact region and the gate contact region are in a ring shape, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or, The source contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

7. The preparation method according to claim 5, characterized in that: The second gate structure is a floating gate structure.

8. The preparation method according to claim 5, characterized in that: Before forming the source contact region and the drain contact region, the method further includes: A source graded region and a drain graded region of the second conductivity type are formed in the drift region, the source contact region is located in the source graded region, and the drain contact region is located in the drain graded region.

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