Column-level low-error single-slope analog-to-digital conversion circuit, analog-to-digital converter and electronic equipment

Abstract

The present invention provides a column-level low-error single-slope analog-to-digital conversion circuit, an analog-to-digital converter, and an electronic device, and relates to the field of integrated circuits. The present invention comprises: a plurality of unit groups and an on-chip phase-locked loop. Each unit group is electrically connected to a pre-stage circuit arranged on a column in an array in a one-to-one correspondence. Each unit group comprises: two latches, a counter, and an encoder. A latch is electrically connected to the on-chip phase-locked loop, the pre-stage circuit, and the encoder. The counter is electrically connected to the on-chip phase-locked loop, the pre-stage circuit, and another latch. The output end of the encoder is electrically connected to another latch, and the other latch outputs the digital quantity obtained by quantization to the outside of the chip. The consistency of coarse and fine quantization of the present invention will not cause bit errors, improve the accuracy of quantization results, and reduce the quantization nonlinearity caused by uneven quantization steps. In combination with the consistency of coarse and fine quantization, which will not cause bit errors, the accuracy of the quantization results is improved as a whole, and the requirements of higher accuracy are met.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a column-level low-error single-slope analog-to-digital conversion circuit, an analog-to-digital converter and electronic equipment. Background Art

[0002] At present, infrared thermal imagers are widely used in thermal imaging fields such as medical imaging, surveillance, and night vision. In recent years, readout circuits (ROICs) with on-chip analog-to-digital converters (ADCs) have been widely used due to their better noise performance and reduced system complexity, and they have shorter analog signal paths compared to traditional analog readouts.

[0003] With the development of science and technology, the readout circuit of the on-chip analog-to-digital converter has a larger array structure while being miniaturized. In general, when the traditional large-scale array readout circuit adopts the column-level analog-to-digital conversion method, a single-slope analog-to-digital conversion circuit is often used. However, single-slope analog-to-digital conversion often means that low power consumption and high precision are incompatible. That is, high precision is obtained by consuming huge power consumption, or low power consumption is consumed, but the precision is naturally low.

[0004] Therefore, there is an urgent need to propose a low-power and high-precision large-scale array readout circuit. Summary of the invention

[0005] In view of the above problems, the present invention is proposed to provide a column-level low-error single-slope analog-to-digital conversion circuit, an analog-to-digital converter and an electronic device that solve the above problems or partially solve the above problems.

[0006] A first aspect of an embodiment of the present invention provides a column-level low-error single-slope analog-to-digital conversion circuit, which is applied to a large-scale array readout circuit. The column-level low-error single-slope analog-to-digital conversion circuit comprises: a plurality of unit groups and an on-chip phase-locked loop; the on-chip phase-locked loop comprises: a phase-locked loop unit and a trigger unit;

[0007] Each of the plurality of unit groups is electrically connected to a front-stage circuit arranged on a column in the array in a one-to-one correspondence;

[0008] One end of the phase-locked loop unit receives a high-frequency master clock signal, and the other end is electrically connected to the input end of the trigger unit;

[0009] The output end of the trigger unit is electrically connected to each of the unit groups;

[0010] Each unit group includes: N-bit latch, M-bit counter, encoder and L-bit latch;

[0011] One input end of the N-bit latch is electrically connected to the output end of the trigger unit, another input end is electrically connected to the previous stage circuit, and an output end is electrically connected to the input end of the encoder;

[0012] One input end of the M-bit counter is electrically connected to the output end of the trigger unit, another input end is electrically connected to the previous stage circuit, and an output end is electrically connected to the input end of the L-bit latch and the input end of the encoder respectively;

[0013] The output end of the encoder is electrically connected to the input end of the L-bit latch, and the output end of the L-bit latch outputs the quantized digital quantity to the outside of the chip;

[0014] The value of N is determined by the number of bits of the on-chip phase-locked loop output signal, the value of L is determined by the requirement of quantization accuracy, and the value of M is determined by the values ​​of L and N.

[0015] Optionally, the on-chip phase-locked loop is configured to generate a second delayed clock signal based on the high-frequency main clock signal and transmit the second delayed clock signal to the plurality of unit groups;

[0016] Wherein, the phase-locked loop unit is configured to generate a first delayed clock signal based on the high-frequency main clock signal and transmit the first delayed clock signal to the trigger unit;

[0017] The trigger unit performs a two-frequency division operation on the first delayed clock signal to obtain the second delayed clock signal and transmits it to the plurality of unit groups;

[0018] The least significant bit signal in the second delayed clock signal is transmitted to the M-bit counter separately;

[0019] The remaining second delayed clock signals except the least significant bit signal are transmitted to the N-bit latch.

[0020] Optionally, the front-stage circuit includes: a comparator;

[0021] The comparator comprises: two input terminals;

[0022] The two input ends are respectively configured such that one of the input ends receives a sampling signal, and the other input end is electrically connected to a single slope signal generating module to receive a single slope signal, wherein the sampling signal is a signal obtained by sampling a column in the array;

[0023] The comparator is configured to generate a comparison signal according to a comparison result between the sampling signal and the single ramp signal, and transmit the comparison signal to the N-bit latch and the M-bit counter respectively.

[0024] Optionally, the N-bit latch is configured to obtain the phase of the remaining second delayed clock signals based on the comparison signal, and form a corresponding N-bit code value according to the phase to transmit to the encoder.

[0025] Optionally, the M-bit counter is configured to obtain a cycle count of the least significant bit signal based on the comparison signal, and form a corresponding M-bit code value according to the cycle count and transmit it to the L-bit latch, and transmit the least significant bit code value of the M-bit code value to the encoder;

[0026] The signal frequency corresponding to the lowest bit code value of the M-bit code value is the same as the frequency of the lowest bit signal.

[0027] Optionally, the encoder is configured to generate a corresponding binary code value based on the N-bit code value and the lowest bit code value of the M-bit code value and transmit it to the L-bit latch.

[0028] Optionally, the L-bit latch is configured to perform synthesis processing on the M-bit code value and the binary code value to obtain the digital quantity and output it outside the chip.

[0029] Optionally, L is greater than M, and L is equal to or not equal to N;

[0030] N is equal to or not equal to M.

[0031] A second aspect of an embodiment of the present invention provides an analog-to-digital converter, the analog-to-digital converter comprising a column-level low-error single-slope analog-to-digital conversion circuit as described in any one of the first aspects.

[0032] A third aspect of an embodiment of the present invention provides an electronic device, comprising: the analog-to-digital converter as described in the second aspect.

[0033] The column-level low-error single-slope analog-to-digital conversion circuit provided by the present invention is applied to a large-scale array readout circuit, and includes: a plurality of unit groups and an on-chip phase-locked loop. The on-chip phase-locked loop includes: a phase-locked loop unit and a trigger unit. Each unit group in the plurality of unit groups is electrically connected to a pre-stage circuit arranged on a column in the array in a one-to-one correspondence; that is, each column is provided with a pre-stage circuit, and is electrically connected to a unit group through the pre-stage circuit.

[0034] One end of the phase-locked loop unit in the on-chip phase-locked loop receives a high-frequency main clock signal, and the other end is electrically connected to the input end of the trigger unit; the output end of the trigger unit is electrically connected to each unit group.

[0035] Each unit group includes: an N-bit latch, an M-bit counter, an encoder and an L-bit latch. One input end of the N-bit latch is electrically connected to the on-chip phase-locked loop, the other input end is electrically connected to the front-stage circuit, and the output end is electrically connected to the input end of the encoder. One input end of the M-bit counter is electrically connected to the on-chip phase-locked loop, the other input end is electrically connected to the front-stage circuit, and the output end is electrically connected to the input end of the L-bit latch and the input end of the encoder respectively.

[0036] The output of the encoder is electrically connected to the input of the L-bit latch, and the output of the L-bit latch outputs the quantized digital quantity to the outside of the chip. The value of N is determined by the number of bits of the output signal of the on-chip phase-locked loop, the value of L is determined by the requirement of quantization accuracy, and the value of M is determined by the values ​​of L and N.

[0037] The column-level low-error single-slope analog-to-digital conversion circuit proposed in the present invention creatively proposes a unit group structure, in which a latch and an encoder structure are used to cooperate with a counter to achieve fine quantization, and a coarse quantization is achieved by combining the counter. Since the first delayed clock signal generates a second delayed clock signal through a two-frequency division, the frequency of the lowest bit signal of the second delayed clock signal is the same as the frequency of the signal corresponding to the lowest bit code value of the counter, eliminating the phase delay between the lowest bit signal of the first delayed clock signal and the signal corresponding to the lowest bit code value of the counter. Therefore, the signal to be measured will not fall within the delay range, so that when the lowest bit of the coarse quantization counter jumps, the fine quantization also jumps at the same time, and the consistency of the coarse and fine quantization will not cause bit errors, thereby improving the accuracy of the quantization result.

[0038] And the inaccurate 50% duty cycle of the first delayed signal is divided by two to obtain a signal with an accurate 50% duty cycle, that is, the duty cycle of the second delayed signal is 50%, thereby solving the problem of uneven fine quantization step length and reducing the quantization nonlinearity caused by uneven quantization step length. The consistency of coarse and fine quantization will not cause bit errors, which improves the accuracy of the quantization result as a whole, meets the requirements of higher accuracy, and has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0040] Figure 1 It is a schematic diagram of the architecture of a conventional large-scale array readout circuit;

[0041] Figure 2It is the 16-bit (CK0-CK15) encoding method and counter clock timing diagram under the existing circuit architecture;

[0042] Figure 3 is a structural schematic diagram of an exemplary column-level low-error single-slope analog-to-digital conversion circuit in an embodiment of the present invention;

[0043] Figure 4 16-bit (CK0'-CK15') encoding method and counter clock timing diagram under the circuit architecture proposed in the embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The inventors have found that the conventional large-scale array readout circuits often use a single slope analog-to-digital conversion circuit when using column-level analog-to-digital conversion, but single slope analog-to-digital conversion often means that low power consumption and high precision are incompatible, that is, high precision is obtained by consuming huge power consumption, or low power consumption is consumed, but the precision is naturally low.

[0046] For example, refer to Figure 1 The schematic diagram of the architecture of the conventional large-scale array readout circuit is shown in FIG. For each column in the array, there is a sampling unit that samples the signal (generally a voltage signal, analog quantity) on the column to which it is electrically connected, and obtains a sampling signal V SH And transmitted to the comparator, the comparator's in-phase terminal receives the sampling signal V SH , the inverting terminal of the comparator and the single ramp signal generating module ( Figure 1 ) is electrically connected to receive a single ramp signal V RAMP .

[0047] The comparator samples the signal V SH , single ramp signal V RAMP Compare and get the comparison signal CMP OUT And transmitted to the counter, the counter compares the signal CMP OUT The memory continuously samples and stores the counting code value of the counter, and finally outputs the digital value D corresponding to the sampling signal. OUT To outside the film.

[0048] Depend on Figure 1It can be seen that the traditional column-level single-slope analog-to-digital converter needs to implement a counter at the column level. Each column has a counter and a memory, and both work continuously. When the quantization time is fixed, the frequency of the clock signal determines the quantization accuracy. However, high-frequency clock signals are often difficult to transmit in large-array column-level circuits. This is because there are interference factors such as parasitic capacitance that are difficult to avoid in large-array column-level circuits. Therefore, high-frequency clock signals will cause signal distortion and deformation as the transmission continues, reducing the quantization accuracy. In order to prevent the signal distortion and deformation of the high-frequency clock, huge power consumption is required. And a single-column counter that implements a high-frequency clock signal also means huge power consumption. Therefore, power consumption and accuracy are difficult to be compatible.

[0049] Since high-frequency clocks are difficult to transmit and the quantization time of SSADC (single slope analog-to-digital converter) is often more stringent, this will also lead to insufficient quantization accuracy of SSADC. Based on this problem, a solution currently adopted is to use a high-bit counter plus a low-bit TDC method to realize a high-speed and high-precision analog-to-digital converter. That is, the counter is used to achieve coarse quantization, and the latch plus encoder (regarded as realizing the TDC function) is used to achieve fine quantization. However, since different counting methods are used for high and low bits, such a circuit architecture will cause errors in the code value, resulting in low accuracy of the quantization result.

[0050] The inventors further studied and found that the cause of the above problem is that since the counter clock and the multi-phase delay clock of the segmented TDC have different transmission paths, when the lowest bit of the coarse quantization counter jumps, the inconsistency of coarse and fine quantization easily causes bit errors.

[0051] by Figure 2 The 16-bit (CK0-CK15) encoding method and counter clock timing diagram under the existing circuit architecture shown in the figure are taken as an example: the lowest bit CNT of the coarse quantization counter <0> There is a delay between the lowest bit CK0 and the multi-phase delayed clock signal. In the worst case, if the signal to be measured falls within the delay range, CNT <0> It has been flipped, but CK0 has not changed, the number of bit errors is as high as five bits, and the result of the bit error will directly affect the lower 5 bits of the overall quantization result.

[0052] In addition, from Figure 2 It can be seen that the duty cycle of the multi-phase delayed clock signal is not exactly 50%. This is because the multi-phase delayed clock signal is generated by an on-chip phase-locked loop, and the circuit structure of the on-chip phase-locked loop itself will cause this problem. This problem will cause uneven fine quantization steps, thereby affecting the linearity of fine quantization.

[0053] Therefore, the lowest bit CNT of the above coarse quantization counter <0> There is a delay between the lowest bit CK0 in the multi-phase delayed clock signal, which may cause bit errors; and the duty cycle of the multi-phase delayed clock signal is not exactly 50%, which causes uneven fine quantization steps, thus affecting the fine quantization linearity. Overall, the quantization result of the high-speed and high-precision analog-to-digital converter using a high-bit counter plus a low-bit TDC is less accurate.

[0054] In view of the above problems, the inventors have creatively proposed a column-level low-error single-slope analog-to-digital conversion circuit, an analog-to-digital converter and an electronic device of the present invention after in-depth research. The technical solution proposed by the present invention is explained and illustrated in detail below.

[0055] The column-level low-error single-slope analog-to-digital conversion circuit of the present invention is particularly suitable for large-scale array readout circuits. The column-level low-error single-slope analog-to-digital conversion circuit includes: a plurality of unit groups and an on-chip phase-locked loop. The on-chip phase-locked loop includes: a phase-locked loop unit and a trigger unit. Each unit group in the plurality of unit groups is electrically connected to a pre-stage circuit arranged on a column in the array in a one-to-one correspondence; that is, each column is provided with a pre-stage circuit, which is electrically connected to a unit group through the pre-stage circuit. For the on-chip phase-locked loop, one end of the phase-locked loop unit receives a high-frequency master clock signal, and the other end is electrically connected to the input end of the trigger unit; the output end of the trigger unit is electrically connected to each unit group. The on-chip phase-locked loop is not one for each column, and only a single one is required.

[0056] Each of the multiple unit groups includes: an N-bit latch, an M-bit counter, an encoder and an L-bit latch. Among them, the N-bit latch has two input ends, one of which is electrically connected to the on-chip phase-locked loop, and the other input end is electrically connected to the previous stage circuit, and the output end of the N-bit latch is electrically connected to the input end of the encoder.

[0057] The M-bit counter also has two input terminals, one of which is electrically connected to the on-chip phase-locked loop, and the other is electrically connected to the previous stage circuit. The output terminal of the M-bit counter is electrically connected to the input terminal of the L-bit latch and the input terminal of the encoder respectively.

[0058] The output end of the encoder is electrically connected to the input end of the L-bit latch, and the output end of the L-bit latch outputs the quantized digital quantity to the outside of the chip.

[0059] For the respective values ​​of N, M, and L: the value of N is determined by the number of bits of the on-chip phase-locked loop output signal, the value of L is determined by the requirement of quantization accuracy, and the value of M is determined by the value of L and the value of N. For example: if the number of bits of the on-chip phase-locked loop output signal is 8 bits, then the value of N is 8-1=7 bits (because the second delayed clock signal except the lowest bit signal of the second delayed clock signal is transmitted to the 7-bit latch); if the requirement of quantization accuracy is 18 bits, then the value of L is 18; and the value of M is determined by the value of L 18 and the value of N: if the value of N is 7, then the corresponding output bit number of the encoder is 3, then the value of M is 18-3=15, that is, the value of M is 15. There are more detailed explanations and descriptions about the value of M below, so I will not go into details here.

[0060] In order to solve the problems of distortion and deformation of high-frequency clock signals during transmission and low precision of circuit architecture quantization results, an on-chip phase-locked loop is first set. It should be noted that in some existing circuit structures, a phase-locked loop or a structure that can realize the function of a phase-locked loop may have been set up. In this case, the structure or the phase-locked loop can be used without setting up an additional on-chip phase-locked loop, which indirectly saves costs and device layout.

[0061] The on-chip phase-locked loop is configured to generate a delayed clock signal based on a high-frequency main clock signal and transmit it to multiple unit groups; that is, the high-frequency main clock signal is processed to generate a corresponding second delayed clock signal. Among them, the phase-locked loop unit is configured to generate a first delayed clock signal based on the high-frequency main clock signal and transmit it to the trigger unit; that is, there is a delay between the lowest bit signal of the first delayed clock signal generated by the phase-locked loop unit and the lowest bit signal of the M-bit counter. The trigger unit is preferably composed of a D trigger, which performs a two-way frequency division operation on the first delayed clock signal to obtain a second delayed clock signal and transmit it to multiple unit groups. The frequency between the lowest bit signal of the second delayed clock signal after the two-way frequency division operation and the lowest bit signal of the M-bit counter is the same, and there is no delay between the two, that is, the delay is eliminated.

[0062] The lowest bit signal of the generated second delayed clock signal is transmitted to the M-bit counter alone; and the rest of the second delayed clock signals except the lowest bit signal are transmitted to the N-bit latch. For example: if the corresponding first delayed clock signal is CK0-CK15, then the second delayed signal is defined as CK0'-CK15', the lowest bit signal CK0' is transmitted to the M-bit counter alone, and the rest of the second delayed clock signals CK1'-CK15' are transmitted to the N-bit latch.

[0063] For the front-stage circuit, it can be implemented by using a comparator, which includes: two input terminals; the two input terminals are respectively configured such that one of the input terminals receives a sampling signal, and the other input terminal is electrically connected to a single slope signal generating module to receive a single slope signal, and the sampling signal is a signal obtained by sampling a column in the array. In general, the sampling signal is obtained by the sampling unit and transmitted to the inverting terminal of the comparator, and the single slope signal is received by the non-inverting terminal of the comparator.

[0064] The comparator is configured to generate a comparison signal according to a comparison result between the sampling signal and the single ramp signal and transmit the comparison signal to the N-bit latch and the M-bit counter respectively.

[0065] The N-bit latch is configured to obtain the phase of the remaining second delayed clock signals based on the comparison signal. For example, if the remaining second delayed clock signals are CK1'-CK15', then the N-bit latch is configured to obtain the respective phases of CK1'-CK15' based on the comparison signal, and form the corresponding N-bit according to the respective phases of CK1'-CK15', that is, the 15-bit code value is transmitted to the encoder.

[0066] The encoder is configured to generate a corresponding binary code value based on the lowest bit code value of the N-bit code value and the M-bit code value, and transmit it to the L-bit latch. Since the encoder outputs binary code values ​​based on the N-bit code value, the encoder needs to determine how many bits of code value to convert to how many bits of binary code value according to the value of N+1. For example: N is 15, and the lowest bit code value of the M-bit counter code value is also transmitted to the encoder. Therefore, according to the structure of 15+1=16, the encoder has a corresponding binary code value of 4 bits, that is, the encoder is a 16-4 encoder. Assuming N is 31 (the second delayed clock signal is 32 bits), the corresponding binary code value is 5, that is, the encoder is a 32-5 encoder. That is, N+1=2 W , W is the number of bits of the binary code value.

[0067] The M-bit counter is configured to obtain the period of the least significant bit signal based on the comparison signal, that is, the M-bit counter counts the period of the least significant bit signal, and forms a corresponding M-bit code value according to the obtained period count and transmits it to the L-bit latch, and transmits the least significant bit code value of the M-bit code value to the encoder. According to the above description: the value of N is determined by the number of bits of the output signal of the on-chip phase-locked loop, the value of L is determined by the requirement of quantization accuracy, and the value of M is jointly determined by the value of L and the value of N. Since the value of L is determined by the requirement of quantization accuracy, that is, if the requirement of quantization accuracy is 8 bits, then L=8, and if the requirement of quantization accuracy is 16 bits, then L=16.

[0068] The L-bit latch is configured to synthesize the M-bit code value and the binary code value to obtain a digital value and output it off-chip. Therefore, L = M + the number of bits of the binary code value, that is, M = L - the number of bits of the binary code value. It can be seen that: L is greater than M, and L is equal to or not equal to N; N is equal to or not equal to M. For example: L = 16, N = 15, then the encoder is a 16-4 encoder, the number of bits of the binary code value is 4, then M = 12; assuming L = 16, N = 7, then the encoder is an 8-3 encoder, the number of bits of the binary code value is 3, then M = 13, and the rest of the cases are similar and will not be described one by one.

[0069] In terms of overall structure, each of the above-mentioned unit groups can be understood as a counter plus TDC circuit formed by an M-bit counter, an N-bit latch, an L-bit latch, and an encoder. This is because the use of a separate counter for a single column in the traditional structure will lead to high power consumption. Therefore, the present invention uses a column-level counter and a TDC frequency division signal, which can significantly reduce the clock frequency of the counter, thereby significantly reducing the power consumption of the counter compared to the traditional structure.

[0070] In order to better understand the structure of the above column-level low error single slope analog-to-digital conversion circuit, refer to Figure 3 A schematic diagram of an exemplary column-level low-error single-slope analog-to-digital conversion circuit is shown. Figure 3 For the sake of simplicity, N=15, M=12, L=16 are used as an example. For more information on quantization accuracy requirements, refer to Figure 3 The structure shown can be obtained through simple reasoning and will not be elaborated on here.

[0071] Figure 3 Medium V TH Represents the sampling signal, V P represents a single ramp signal, and both are transmitted to the comparator as two input signals of the comparator in the previous circuit. The comparator TH , single ramp signal V P The comparison result generates a comparison signal V O .

[0072] Figure 3 Wherein MCK represents the main clock signal, which generates the second delayed clock signal CK0'-CK15' through the on-chip phase-locked loop On-chip DLL (including the phase-locked loop unit and the trigger unit, which are not specifically identified for the simplicity of the diagram), wherein the remaining second delayed clock signals CK1'-CK15' except the lowest bit CK0' are transmitted to the 15-bit latch 15-bit Latch in the upper left corner of the dotted box, and the lowest bit CK0' of the second delayed clock signal is separately transmitted to the 12-bit counter 12-bit Counter in the lower left corner of the dotted box.

[0073] The 15-bit latch 15-bit Latch in the upper left corner of the dotted box processes the delayed clock signals CK1'-CK15' to obtain their respective phases and form corresponding code values ​​according to their respective phases. F <1:15>, transmitted to the 16-4 encoder 16-4Decoder in the upper right corner of the dotted box. The 12-bit counter 12-bit Counter in the lower left corner of the dotted box counts the cycle of the lowest bit CK0' of the delayed clock signal, and forms the corresponding code value CNT<0:11> according to the result of the cycle counting, and transmits it to the 16-bit latch 16-bit Latch in the lower right corner of the dotted box, and transmits the lowest bit code value CNT<0> of the 12-bit code value to the 16-4 encoder 16-4Decoder.

[0074] The 16-4 encoder in the upper right corner of the virtual box has a code value of 0. F <1:16> and CNT<0> are processed to obtain the corresponding binary code value Dout F <0:3> is also transmitted to the 16-bit latch 16-bitLatch in the lower right corner of the dotted box.

[0075] Finally, the 16-bit latch in the lower right corner of the virtual box converts the code value CNT<0:11> and the binary code value Dout F <0:3> is synthesized to form the digital quantity OUT<0:15> corresponding to the target column signal (which is an analog quantity) and output it outside the chip.

[0076] Reference Figure 4 The 16-bit (CK0'-CK15') encoding method and counter clock timing diagram under the circuit architecture of the present invention are shown, Figure 4 For better comparison, Figure 2 Timing Figure 1 The Traditional Coding Method above is the 16-bit (CK0–CK15) coding method under the existing circuit architecture, and the Proposed Coding Method below is the 16-bit (CK0'–CK15') coding method under the circuit architecture of the present invention.

[0077] Depend on Figure 4It can be seen that the frequency between the lowest bit signal CK0' of the second delayed clock signal and the lowest bit signal CNT<0> of the 12-bit counter is the same, and there is no delay between the two, that is, the delay is eliminated. <0> The lowest bit CK0' of the new delayed clock is used for decoding, thereby controlling the bit error within 1 bit. In addition, although the duty cycle of the multi-phase first delayed clock CK0-CK15 is not exactly 50%, the period of CK0-CK15 is 8ns, so after the trigger unit divides the frequency by two, the duty cycle of the new delayed clock CK0'-CK15' is 50%, thereby reducing the quantization nonlinearity caused by the uneven quantization step size.

[0078] Through the above structure, the entire column-level low-error single-slope analog-to-digital conversion circuit uses a unit group to achieve quantization in each column of the array. The unit group uses a structure of two latches and an encoder, and cooperates with a counter to achieve fine quantization. Combined with the coarse quantization achieved by the single slope signal, the quantization accuracy is improved to meet the high-precision requirements. The architecture of the column-level counter and the TDC frequency division signal is adopted to significantly reduce the clock frequency of the counter, thereby greatly reducing the power consumption of the counter part. In this way, the high-precision quantization requirements are achieved on the basis of achieving lower power consumption.

[0079] Based on the above-mentioned column-level low-error single-slope analog-to-digital conversion circuit, an embodiment of the present invention further provides an analog-to-digital converter, which includes any column-level low-error single-slope analog-to-digital conversion circuit as described above.

[0080] Based on the above-mentioned column-level low-error single-slope analog-to-digital conversion circuit, an embodiment of the present invention further provides an electronic device, which includes: the above-mentioned analog-to-digital converter.

[0081] Through the above embodiments, the column-level low-error single-slope analog-to-digital conversion circuit provided by the present invention is applied to a large-scale array readout circuit, which includes: multiple unit groups and an on-chip phase-locked loop. The on-chip phase-locked loop includes: a phase-locked loop unit and a trigger unit. Each unit group in the multiple unit groups is electrically connected to a pre-stage circuit set on a column in the array in a one-to-one correspondence; that is, each column has a pre-stage circuit, which is electrically connected to a unit group through the pre-stage circuit.

[0082] One end of the phase-locked loop unit in the on-chip phase-locked loop receives a high-frequency main clock signal, and the other end is electrically connected to the input end of the trigger unit; the output end of the trigger unit is electrically connected to each unit group.

[0083] Each unit group includes: an N-bit latch, an M-bit counter, an encoder and an L-bit latch. One input end of the N-bit latch is electrically connected to the on-chip phase-locked loop, the other input end is electrically connected to the front-stage circuit, and the output end is electrically connected to the input end of the encoder. One input end of the M-bit counter is electrically connected to the on-chip phase-locked loop, the other input end is electrically connected to the front-stage circuit, and the output end is electrically connected to the input end of the L-bit latch and the input end of the encoder respectively.

[0084] The output of the encoder is electrically connected to the input of the L-bit latch, and the output of the L-bit latch outputs the quantized digital quantity to the outside of the chip. The value of N is determined by the number of bits of the output signal of the on-chip phase-locked loop, the value of L is determined by the requirement of quantization accuracy, and the value of M is determined by the values ​​of L and N.

[0085] The column-level low-error single-slope analog-to-digital conversion circuit proposed in the present invention creatively proposes a unit group structure, in which a latch and an encoder structure are used to cooperate with a counter to achieve fine quantization, and a coarse quantization is achieved by combining the counter. Since the first delayed clock signal generates a second delayed clock signal through a two-frequency division, the frequency of the lowest bit signal of the second delayed clock signal is the same as the frequency of the signal corresponding to the lowest bit code value of the counter, eliminating the phase delay between the lowest bit signal of the first delayed clock signal and the signal corresponding to the lowest bit code value of the counter. Therefore, the signal to be measured will not fall within the delay range, so that when the lowest bit of the coarse quantization counter jumps, the fine quantization also jumps at the same time, and the consistency of the coarse and fine quantization will not cause bit errors, thereby improving the accuracy of the quantization result.

[0086] And the inaccurate 50% duty cycle of the first delayed signal is divided by two to obtain a signal with an accurate 50% duty cycle, that is, the duty cycle of the second delayed signal is 50%, thereby solving the problem of uneven fine quantization step length and reducing the quantization nonlinearity caused by uneven quantization step length. The consistency of coarse and fine quantization will not cause bit errors, which improves the accuracy of the quantization result as a whole and meets the requirements of higher accuracy.

[0087] At the same time, it is different from the traditional large-scale array that each single column uses a separate counter structure to achieve quantization, which significantly reduces the clock frequency of the counter, thereby greatly reducing the power consumption of the counter part. In this way, high-precision quantization requirements are achieved on the basis of low power consumption, which has high practicality.

[0088] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0089] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A column-level low-error single-slope analog-to-digital conversion circuit, characterized in that: The column-level low-error single-slope analog-to-digital conversion circuit is applied to a large-scale array readout circuit. The column-level low-error single-slope analog-to-digital conversion circuit comprises: a plurality of unit groups and an on-chip phase-locked loop; the on-chip phase-locked loop comprises: a phase-locked loop unit and a trigger unit; Each of the plurality of unit groups is electrically connected to a front-stage circuit arranged on a column in the array in a one-to-one correspondence; One end of the phase-locked loop unit receives a high-frequency master clock signal, and the other end is electrically connected to the input end of the trigger unit; The output end of the trigger unit is electrically connected to each of the unit groups; Each unit group includes: N-bit latch, M-bit counter, encoder and L-bit latch; One input end of the N-bit latch is electrically connected to the output end of the trigger unit, another input end is electrically connected to the previous stage circuit, and an output end is electrically connected to the input end of the encoder; One input end of the M-bit counter is electrically connected to the output end of the trigger unit, another input end is electrically connected to the previous stage circuit, and an output end is electrically connected to the input end of the L-bit latch and the input end of the encoder respectively; The output end of the encoder is electrically connected to the input end of the L-bit latch, and the output end of the L-bit latch outputs the quantized digital quantity to the outside of the chip; The value of N is determined by the number of bits of the on-chip phase-locked loop output signal, the value of L is determined by the requirement of quantization accuracy, and the value of M is determined by the values ​​of L and N. The front-stage circuit comprises: a comparator; The comparator comprises: two input terminals; The two input ends are respectively configured such that one of the input ends receives a sampling signal, and the other input end is electrically connected to a single slope signal generating module to receive a single slope signal, wherein the sampling signal is a signal obtained by sampling a column in the array; The comparator is configured to generate a comparison signal according to a comparison result between the sampling signal and the single ramp signal, and transmit the comparison signal to the N-bit latch and the M-bit counter respectively.

2. The column-level low-error single-slope analog-to-digital conversion circuit according to claim 1, characterized in that: The on-chip phase-locked loop is configured to generate a second delayed clock signal based on the high-frequency main clock signal and transmit the second delayed clock signal to the plurality of unit groups; Wherein, the phase-locked loop unit is configured to generate a first delayed clock signal based on the high-frequency main clock signal and transmit the first delayed clock signal to the trigger unit; The trigger unit performs a two-frequency division operation on the first delayed clock signal to obtain the second delayed clock signal and transmits it to the plurality of unit groups; The least significant bit signal in the second delayed clock signal is transmitted to the M-bit counter separately; The remaining second delayed clock signals except the least significant bit signal are transmitted to the N-bit latch.

3. The column-level low-error single-slope analog-to-digital conversion circuit according to claim 2, characterized in that: The N-bit latch is configured to obtain the phase of the remaining second delayed clock signals based on the comparison signal, and form a corresponding N-bit code value according to the phase and transmit it to the encoder.

4. The column-level low-error single-slope analog-to-digital conversion circuit according to claim 3, characterized in that: The M-bit counter is configured to obtain a cycle count of the least significant bit signal based on the comparison signal, and to form a corresponding M-bit code value according to the cycle count and transmit it to the L-bit latch, and to transmit the least significant bit code value of the M-bit code value to the encoder; The signal frequency corresponding to the lowest bit code value of the M-bit code value is the same as the frequency of the lowest bit signal.

5. The column-level low-error single-slope analog-to-digital conversion circuit according to claim 4, characterized in that: The encoder is configured to generate a corresponding binary code value based on the N-bit code value and the least significant bit code value of the M-bit code value and transmit it to the L-bit latch.

6. The column-level low-error single-slope analog-to-digital conversion circuit according to claim 5, characterized in that: The L-bit latch is configured to perform synthesis processing on the M-bit code value and the binary code value to obtain the digital value and output it outside the chip.

7. The column-level low-error single-slope analog-to-digital conversion circuit according to claim 1, characterized in that: L is greater than M, and L is equal to or not equal to N; N is equal to or not equal to M.

8. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises a column-level low-error single-slope analog-to-digital conversion circuit as described in any one of claims 1-7.

9. An electronic device, characterized in that: The electronic device comprises: the analog-to-digital converter as claimed in claim 8.

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