Inverter and chip based on carbon-based transistor

Abstract

An inverter based on a carbon-based transistor and a chip are disclosed. An inverter based on a carbon-based transistor includes: a substrate; a first-type carbon-based transistor and a second-type carbon-based transistor on the substrate, wherein the first-type carbon-based transistor includes a first source and a first drain, and the second-type carbon-based transistor includes a second source and a second drain, wherein the first source and the first drain and the second source and the second drain are stacked individually in a direction perpendicular to the substrate, or the first source and the first drain are stacked together with the second source and the second drain in a direction perpendicular to the substrate; and wherein the first drain and the second drain are coupled to the same output terminal, one of the first source and the second source is coupled to a power supply voltage terminal, and the other is coupled to a ground voltage terminal.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, in particular to the field of carbon-based transistor technology, and specifically to an inverter based on a carbon-based transistor, and a chip. Background Art

[0002] As a standard unit of digital circuits in integrated circuits, inverters play a fundamental role in chip design. Traditional inverters are mainly manufactured based on silicon-based processes. In recent years, research on carbon-based transistors (CNTFETs) has gradually emerged in the industry, and how to realize inverters in carbon-based transistor processes is one of the hot issues of concern in the industry. Summary of the invention

[0003] The present disclosure provides an inverter based on a carbon-based transistor and a chip.

[0004] According to one aspect of the present disclosure, there is provided an inverter based on a carbon-based transistor, comprising: a substrate; a first type of carbon-based transistor and a second type of carbon-based transistor on the substrate, wherein the first type of carbon-based transistor comprises a first source and a first drain, and the second type of carbon-based transistor comprises a second source and a second drain, wherein the first source and the first drain and the second source and the second drain are individually stacked along a direction perpendicular to the substrate, or the first source and the first drain are commonly stacked along a direction perpendicular to the substrate with the second source and the second drain; and wherein the first drain and the second drain are coupled to the same output terminal, one of the first source and the second source is coupled to a power supply voltage terminal, and the other is coupled to a ground voltage terminal.

[0005] According to another aspect of the present disclosure, a chip is provided. The chip includes the inverter as described above.

[0006] According to one or more embodiments of the present disclosure, a carbon-based transistor-based inverter having a simple structure and high integration can be provided.

[0007] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A schematic diagram showing the circuit structure of an inverter;

[0010] Figure 2 A schematic perspective view showing an inverter based on a carbon-based transistor according to an embodiment of the present disclosure;

[0011] Figure 3 A schematic perspective view showing an inverter based on a carbon-based transistor according to another embodiment of the present disclosure;

[0012] Figure 4 A schematic perspective view of an inverter based on a carbon-based transistor according to yet another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0013] It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part without departing from the teaching of the present disclosure.

[0014] Spatially relative terms such as "below," "beneath," "lower," "below," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figure. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as "below other elements or features" or "below other elements or features" or "below other elements or features" will be oriented to "above other elements or features." Therefore, the exemplary terms "below" and "below" can cover both orientations above and below. Terms such as "before" or "before" and "after" or "followed by" can be similarly used, for example, to indicate the order in which light passes through the elements. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between two layers,” it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0015] The terms used herein are only for the purpose of describing a specific embodiment and are not intended to limit the present disclosure. As used herein, the singular forms "one", "one" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the existence of the features, integral bodies, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups or add one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" refers to only A, only B, or both A and B.

[0016] It will be understood that when an element or layer is referred to as being "on another element or layer," "connected to another element or layer," "coupled to another element or layer," or "adjacent to another element or layer," it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent to another element or layer," there are no intermediate elements or layers. However, in no case should "on..." or "directly on..." be interpreted as requiring that one layer completely cover the layer below.

[0017] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the zones of the device and are not intended to limit the scope of the present disclosure.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0019] As used herein, the term "substrate" may refer to the substrate of a cut wafer, or may indicate the substrate of an uncut wafer. Similarly, the terms chip and die may be used interchangeably unless such interchange would cause a conflict. It should be understood that the term "layer" includes thin films and should not be interpreted as indicating vertical or horizontal thickness unless otherwise specified.

[0020] In the related art, inverters are common circuit elements in silicon-based CMOS processes. However, the technology for implementing inverters in the field of carbon-based transistors is still immature, which restricts the development and application of carbon-based CMOS processes.

[0021] In view of the above problems, according to one aspect of an embodiment of the present disclosure, an inverter based on a carbon-based transistor is provided.

[0022] Before describing in detail the inverter based on carbon-based transistors according to the embodiments of the present disclosure, the basic circuit principle of the inverter is first introduced.

[0023] Figure 1 A schematic diagram showing the circuit structure of an inverter.

[0024] like Figure 1 As shown, the inverter 100 includes an NMOS transistor 102 and a PMOS transistor 104. The NMOS transistor 102 includes a source 102a, a drain 102b, and a gate 102c, and the PMOS transistor 104 includes a source 104a, a drain 104b, and a gate 104c.

[0025] The source 102 a of the NMOS transistor 102 is coupled to the ground voltage terminal Vss, the drain 102 b and the drain 104 b of the PMOS transistor 104 are commonly coupled to the output terminal Vout, and the gate 102 c and the gate 104 c of the PMOS transistor 104 are commonly coupled to the input terminal Vin.

[0026] The source 104 a of the PMOS transistor 104 is coupled to the power supply voltage terminal Vdd, the drain 104 b and the drain 102 b of the NMOS transistor 102 are commonly coupled to the output terminal Vout, and the gate 104 c and the gate 102 c of the NMOS transistor 102 are commonly coupled to the input terminal Vin.

[0027] When a high-level signal ("1") is input via the input terminal Vin, the output terminal Vout outputs a low-level signal ("0"). Conversely, when a low-level signal ("0") is input via the input terminal Vin, the output terminal Vout outputs a high-level signal ("1"). Thus, the inversion function from the input signal to the output signal can be realized.

[0028] The inverter based on the carbon-based transistor provided by the embodiment of the present disclosure is implemented based on a stacking structure. The inverter includes a substrate and a first type of carbon-based transistor and a second type of carbon-based transistor on the substrate. The first type of carbon-based transistor includes a first source and a first drain, and the second type of carbon-based transistor includes a second source and a second drain. The first source and the first drain and the second source and the second drain are stacked separately in a direction perpendicular to the substrate, or the first source and the first drain are stacked together with the second source and the second drain in a direction perpendicular to the substrate. The first drain and the second drain are coupled to the same output terminal, one of the first source and the second source is coupled to the power supply voltage terminal, and the other is coupled to the ground voltage terminal.

[0029] In some embodiments, the first source and the first drain and the second source and the second drain are stacked separately in a direction perpendicular to the substrate, which may mean that the first source and the first drain form a stacked structure, and the second source and the second drain form a stacked structure. That is, the first type carbon-based transistor and the second type carbon-based transistor are each formed in a stacked manner.

[0030] In some embodiments, the first source and the first drain are stacked together with the second source and the second drain in a direction perpendicular to the substrate, which may mean that the first source and the first drain form a stacked structure with the second source and the second drain as a whole. That is, the first type carbon-based transistor and the second type carbon-based transistor are stacked together to form a stacked structure.

[0031] Through the above-mentioned method, the embodiment of the present disclosure provides an inverter based on carbon-based transistors with a stacked structure. The inverter has a simple structure, a simplified circuit, a small area and a high degree of integration.

[0032] Figure 2 A schematic perspective view of an inverter based on a carbon-based transistor according to an embodiment of the present disclosure is shown.

[0033] like Figure 2 As shown, the inverter 200 includes a substrate 201 and a first type carbon-based transistor 202 and a second type carbon-based transistor 203 on the substrate 201. The first type carbon-based transistor 202 includes a first source 202a and a first drain 202b. The second type carbon-based transistor 203 includes a second source 203a and a second drain 203b. The first drain 202b and the second drain 203b are coupled to the same output terminal Vout. The first source 202a is coupled to the power supply voltage terminal Vdd, and the second source 203a is coupled to the ground voltage terminal Vss.

[0034] The inverter 200 has a stacked structure in which the first source 202a and the first drain 202b are stacked in a direction perpendicular to the substrate 201, and the second source 203a and the second drain 203b are stacked in a direction perpendicular to the substrate 201. That is, the first type carbon-based transistor 202 and the second type carbon-based transistor 203 each have a stacked structure.

[0035] In some embodiments, the inverter 200 may include a common gate 204 on a substrate 201. The first type carbon-based transistor 202 and the second type carbon-based transistor 203 share the common gate 204. The first source 202a and the first drain 202b of the first type carbon-based transistor 202 are stacked on a first sidewall 204a of the common gate 204 in a direction perpendicular to the substrate 201. The second source 203a and the second drain 203b of the second type carbon-based transistor 203 are stacked on a second sidewall 204b of the common gate 204 in a direction perpendicular to the substrate 201.

[0036] In this way, the first type carbon-based transistor 202 and the second type carbon-based transistor 203 , each having a stacked structure, can be combined together using the common gate 204 to form a compact stacked structure, thereby improving integration and reducing chip area.

[0037] In some embodiments, the first type carbon-based transistor 202 may include a first gate oxide layer 202c and a first channel layer 202d sequentially extending on a first sidewall 204a of the common gate 204. Similarly, the second type carbon-based transistor 203 may include a second gate oxide layer 203c and a second channel layer 203d sequentially extending on a second sidewall 204b of the common gate 204. The first channel layer 202d and the second channel layer 203d each include carbon nanotubes (CNTs).

[0038] In some embodiments, the first drain 202 b and the second drain 203 b may be coupled to the same output terminal Vout via a first connection member 205 crossing the common gate 204 over the common gate 204 .

[0039] Since the first type carbon-based transistor 202 and the second type carbon-based transistor 203 each have a stacked structure, and the two are located on both sides of the common gate 204 in a manner of sharing a common gate 204, the first drain 202b and the second drain 203b can be easily coupled together by using a first connecting component 205 crossing the common gate 204, which facilitates the implementation and application of the process.

[0040] In some embodiments, the first source 202 a and the second source 203 a may be flush in height, and the first drain 202 b and the second drain 203 b may be flush in height.

[0041] That is, the first source 202a and the second source 203a can be formed in the same layer, and the first drain 202b and the second drain 203b can be formed in the same layer. In this way, the implementation of the process can be simplified, and an inverter with a stacked structure can be formed in a simple manner.

[0042] In some embodiments, the layer where the first source 202 a and the second source 203 a are located and the layer where the first drain 202 b and the second drain 203 b are located may be in a step-like structure.

[0043] In an example, the size of the pattern for forming the first source 202a may be smaller than the size of the pattern for forming the first drain 202b, so that the first through hole 206a for connecting the first connection member 205 may be additionally formed in a portion where the pattern of the first drain 202b exceeds the pattern of the first source 202a. Similarly, the size of the pattern for forming the second source 203a may be smaller than the size of the pattern for forming the second drain 203b, so that the second through hole 206b for connecting the first connection member 205 may be additionally formed in a portion where the pattern of the second drain 203b exceeds the pattern of the second source 203a.

[0044] Therefore, it is possible to facilitate the process implementation, so that the first drain 202 b of the first type carbon-based transistor 202 and the second drain 203 b of the second type carbon-based transistor 203 can be coupled together by using a simple process.

[0045] In some embodiments, the first source 202a and the first drain 202b of the first type carbon-based transistor 202 may be isolated by a dielectric layer 207. Similarly, the second source 203a and the first drain 203b of the second type carbon-based transistor 203 may be isolated by a dielectric layer 208.

[0046] In addition, if Figure 2 As shown, the common gate 204 can be connected to the input terminal Vin through a via. The first source 202a of the first type carbon-based transistor 202 and the second source 203a of the second type carbon-based transistor 203 can be connected to the power supply voltage terminal Vdd and the ground voltage terminal Vss through respective vias.

[0047] Figure 3 A schematic perspective view of an inverter based on a carbon-based transistor according to another embodiment of the present disclosure is shown.

[0048] like Figure 3 The inverter 300 shown is compared to the Figure 2 The inverter 200 shown in the figure has a dielectric layer 310 covering the entire device structure, so that Figure 3The through holes outside the dielectric layer 310 are shown. Figure 3 Various aspects of the inverter 300 shown may be used in conjunction with Figure 2 The inverters 200 shown are identical.

[0049] Figure 4 A schematic perspective view of an inverter based on a carbon-based transistor according to yet another embodiment of the present disclosure is shown.

[0050] like Figure 4 As shown, the inverter 400 includes a substrate (not shown) and a first type carbon-based transistor 401 and a second type carbon-based transistor 402 on the substrate. The first type carbon-based transistor 401 includes a first source 401a and a first drain 401b. The second type carbon-based transistor 402 includes a second source 402a and a second drain 402b. The first drain 401b and the second drain 402b are coupled to the same output terminal Vout. The first source 401a is coupled to the power supply voltage terminal Vdd, and the second source 402a is coupled to the ground voltage terminal Vss.

[0051] The inverter 400 has a stacked structure, in which the first source 401a and the first drain 401b of the first type carbon-based transistor 401 are stacked together with the second source 402a and the second drain 402b of the second type carbon-based transistor 402 in a direction perpendicular to the substrate. That is, the first type carbon-based transistor 401 and the second type carbon-based transistor 402 are stacked together to form a stacked structure.

[0052] In some embodiments, the first type carbon-based transistor 401 may include a first gate 401c, and the second type carbon-based transistor 402 may include a second gate 402c. The first gate 401c and the second gate 402c share a common channel layer 403. The first source 401a and the first drain 401b of the first type carbon-based transistor 401 and the second source 402a and the second drain 402b of the second type carbon-based transistor 402 are stacked symmetrically in a direction perpendicular to the substrate relative to the common channel layer 403.

[0053] In this way, the first type carbon-based transistor 401 and the second type carbon-based transistor 402 stacked on each other can be combined together using the common channel layer 403 to form a compact stacking structure, thereby improving integration and reducing chip area.

[0054] In some embodiments, the first type carbon-based transistor 401 may include a first gate oxide layer 401d between the first gate 401c and the common channel layer 403 . The second type carbon-based transistor 402 may include a second gate oxide layer 402d between the second gate 402c and the common channel layer 403 .

[0055] In some embodiments, the first gate 401 c and the second gate 402 c may be coupled to the same input terminal Vin via a second connection member 404 extending in a direction perpendicular to the substrate.

[0056] In an example, a size of the pattern of the first gate 401c may be larger than a size of the pattern of the first gate oxide layer 401d, and a size of the pattern of the second gate 402c may be larger than a size of the pattern of the second gate oxide layer 402d, so that a portion of the pattern of the first gate 401c that extends beyond the pattern of the first gate oxide layer 401d and a portion of the pattern of the second gate 402c that extends beyond the pattern of the second gate oxide layer 402d may be coupled together via the second connecting component 404.

[0057] Therefore, it is possible to facilitate the process implementation, so that the first gate 401c and the second gate 402c can be coupled together by adopting a simple process.

[0058] In some embodiments, the first source 401 a and the first drain 401 b are flush in height, and the second source 402 a and the second drain 402 b are flush in height.

[0059] That is, the first source 401a and the first drain 401b can be formed in the same layer, and the second source 402a and the second drain 402b can be formed in the same layer. In this way, the process can be simplified, and an inverter with a stacked structure can be formed in a simple manner.

[0060] In some embodiments, the first source 401a of the first type carbon-based transistor 401 and the second source 402a of the second type carbon-based transistor 402 may be isolated by a dielectric layer. Similarly, the first drain 401b of the first type carbon-based transistor 401 and the second drain 402b of the second type carbon-based transistor 402 may be isolated by a dielectric layer.

[0061] In addition, if Figure 4 As shown, the first source 401a, the first drain 401b and the first gate 401c of the first type carbon-based transistor 401 and the second source 402a, the second drain 402b and the second gate 402c of the second type carbon-based transistor 402 can be connected to the corresponding input / output terminals or power supply / ground voltage terminals through their respective through holes.

[0062] The inverter based on the carbon-based transistor implemented according to the embodiment of the present disclosure has a simple structure, a simplified circuit, a small area and a high degree of integration.

[0063] According to another aspect of the embodiment of the present disclosure, a chip is further provided. The chip includes: Figures 2 to 4 An inverter based on a carbon-based transistor is shown.

[0064] The above description is only an illustration of the illustrative embodiments and application technical principles of the present disclosure. Those skilled in the art should understand that the scope of the present disclosure to which the embodiments of the present disclosure relate is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, and should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, the technical solutions formed by replacing the above-mentioned features with technical features (but not limited to) having similar functions to the technical features disclosed in the embodiments of the present disclosure also fall within the scope of protection of the present disclosure.

[0065] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered illustrative and schematic, not restrictive; the present disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure and the appended claims, those skilled in the art will be able to understand and implement variations to the disclosed embodiments when practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "plurality" means two or more, and the term "based on" should be interpreted as "based at least in part on". The mere fact that certain measures are recorded in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. An inverter based on a carbon-based transistor, comprising: substrate; A first type carbon-based transistor and a second type carbon-based transistor on a substrate, wherein the first type carbon-based transistor includes a first source and a first drain, and the second type carbon-based transistor includes a second source and a second drain, wherein the first source and the first drain and the second source and the second drain are individually stacked in a direction perpendicular to the substrate via a common gate on the substrate, wherein the first type of carbon-based transistor and the second type of carbon-based transistor share the common gate, the first source and the first drain of the first type of carbon-based transistor are stacked on a first side wall of the common gate in a direction perpendicular to the substrate, and the second source and the second drain of the second type of carbon-based transistor are stacked on a second side wall of the common gate in a direction perpendicular to the substrate, or The first source and the first drain are stacked together with the second source and the second drain via a common channel layer in a direction perpendicular to the substrate, wherein the first type carbon-based transistor includes a first gate, the second type carbon-based transistor includes a second gate, the first gate and the second gate share the common channel layer, and the first source and the first drain are stacked symmetrically with the second source and the second drain in a direction perpendicular to the substrate relative to the common channel layer; and The first drain and the second drain are coupled to the same output terminal, one of the first source and the second source is coupled to a power supply voltage terminal, and the other is coupled to a ground voltage terminal.

2. The inverter according to claim 1, wherein: When the first source and the first drain and the second source and the second drain are individually stacked in a direction perpendicular to the substrate via a common gate on a substrate, the first drain and the second drain are coupled to the same output terminal via a first connecting component crossing the common gate above the common gate.

3. The inverter according to claim 1, wherein: When the first source and the first drain and the second source and the second drain are individually stacked in a direction perpendicular to the substrate via a common gate on the substrate, the first source and the second source are flush in height, and the first drain and the second drain are flush in height.

4. The inverter according to claim 3, wherein: When the first source and the first drain and the second source and the second drain are individually stacked in a direction perpendicular to the substrate via a common gate on the substrate, the layer where the first source and the second source are located and the layer where the first drain and the second drain are located have a step-like structure.

5. The inverter according to claim 1, wherein: When the first source and the first drain are stacked together with the second source and the second drain via a common channel layer in a direction perpendicular to the substrate, the first gate and the second gate are coupled to the same input terminal via a second connection member extending in a direction perpendicular to the substrate.

6. The inverter according to claim 1, wherein: When the first source and the first drain are stacked together with the second source and the second drain via a common channel layer in a direction perpendicular to the substrate, the first source and the first drain are flush in height, and the second source and the second drain are flush in height.

7. The inverter according to any one of claims 1 to 6, wherein: The first type carbon-based transistor includes one of an NMOS transistor or a PMOS transistor, and the second type carbon-based transistor includes the other of an NMOS transistor or a PMOS transistor.

8. A chip, wherein: The chip includes the inverter according to any one of claims 1 to 7.

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