A software and hardware handshake method and device for switching chip working mode

Abstract

The present invention provides a method and device for switching the working mode of a chip by handshaking software and hardware, the method comprising: receiving configuration information set by firmware, the configuration information comprising the protocol flow of the chip physical layer IP; using digital logic to load and parse the configuration information, controlling the execution state of the state machine based on the configuration information, and switching the working mode of the chip by executing the protocol flow. The technical solution of the present invention reduces the duplication of digital-analog hybrid IP development and adapts to the digital development of different ASICs.

Description

Technical Field

[0001] The invention belongs to the field of chip design, and in particular relates to a software and hardware handshake method and device for switching chip working modes. Background Art

[0002] In chip design, intellectual property modules (IP) usually refer to reusable design modules or codes that can be used to build specific functions or components of a chip. For the physical layer (PHY), IP can implement the PHY layer protocol, combined with the implementation of part of the physical coding sublayer (PCS) or even the content of the media access control (MAC) layer protocol. In order to fully verify the MAC layer of different protocols, the digital logic design of the PHY IP design is increasingly complex when it is applied to the final application-specific integrated circuit (ASIC). IP delivery needs to verify these different application scenarios in advance to meet different protocols, such as the Multi-Source Agreement (MSA), the International Telecommunication Union (ITU), the Optical Interconnection Forum (OIF) and the Institute of Electrical and Electronics Engineers (IEEE) 802.3. Among them, MSA, as an inter-enterprise alliance, defines the structural packaging of optical modules (including external dimensions, electrical connectors, pin assignments, etc.), and also defines electrical interfaces and optical interfaces, thereby forming a complete optical module standard. ITU implements frame mapping. OIF can be specifically OIF-CEI-5.0, which is used to achieve different driving capabilities, such as ultra-long drive XLR / long drive LR / medium drive MR / short drive VSR / ultra-short drive XSR / multi-chip module MCM / co-packaged optical module CPO. IEEE 802.3 includes Backplane Channels, Cu Cable Channels, Chip-to-Module Channels and Chip to Chip Channels (10-20dB).

[0003] In the traditional solution, when IP is integrated into ASIC application chip, different driving capabilities (XSR, VSR, MR, LR, XLR) of IP are selected according to different requirements, and different upper layer protocols (MAC and above) are adapted. The digital logic implementation requirements of ASIC matching IP design are repeatedly implemented in IP and ASIC. In addition, in the new IP design, the analog IP design and development process, the digital design needs to design multiple branch backup solutions to debug performance.

[0004] For mixed-analog IP, during the performance tuning process, different test verification or protocol status requirements require the use of firmware to achieve conversion, and some timing and conversion time requirements cannot meet the standards. When IP is designed to cope with normalization in different scenarios, different versions of different digital logic designs are required, which increases the design cycle. Summary of the invention

[0005] The purpose of the present invention is to provide a software and hardware handshake method and device for switching chip working modes, aiming to reduce the duplication of digital-analog mixed IP development and adapt to the digital development of different ASICs.

[0006] According to a first aspect of the present invention, a software and hardware handshake method for switching a chip working mode is provided, comprising:

[0007] Receive configuration information set by the firmware, the configuration information including a protocol flow of a chip physical layer IP;

[0008] The configuration information is loaded and parsed by using digital logic, the execution state of the state machine is controlled based on the configuration information, and the chip working mode is switched by executing the protocol process.

[0009] Preferably, receiving configuration information set by the firmware, the configuration information including a protocol flow of a chip physical layer IP;

[0010] The configuration information is loaded and parsed by using digital logic, the execution state of the state machine is controlled based on the configuration information, and the chip working mode is switched by executing the protocol process.

[0011] Preferably, the protocol process includes power-on, power-off, calibration or adaptation processes, and the protocol process is fully implemented by the digital logic, or partially implemented by the digital logic and partially implemented by the firmware.

[0012] Preferably, before receiving the configuration information set by the firmware, the method further comprises:

[0013] The firmware sets corresponding configuration information according to different protocols and driving capability requirements.

[0014] Preferably, the firmware is SOC firmware.

[0015] Preferably, the firmware is the firmware of the IP.

[0016] According to a second aspect of the present invention, a software and hardware handshake device for switching a chip working mode is provided, comprising:

[0017] A firmware handshake interface unit, used to receive configuration information set by the firmware, wherein the configuration information includes a protocol flow of the chip physical layer IP;

[0018] A digital handshake control unit is used to load and parse the configuration information using digital logic, control the execution state of the state machine based on the configuration information, and switch the chip working mode by executing the protocol process.

[0019] Compared with the related art, the technical solution of the present invention has the following advantages:

[0020] Converting the actions executed by the original firmware into actions executed by the digital according to the firmware configuration can not only generalize and simplify the digital design in the digital-analog IP and speed up the running time, but also facilitate the firmware to configure the PHY IP execution process according to different protocols and driving capability requirements when integrating IP in ASIC. It only needs to issue different firmware configuration sequences in the CP / FT screening stage and different protocol product application ASICs, and the ASIC digital logic will be implemented according to the corresponding configuration, reducing the duplication of digital-analog mixed IP development and adapting to the digital development of different ASICs.

[0021] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures and processes indicated in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a flow chart of the software and hardware handshake method for switching the chip working mode according to the present invention.

[0024] Figure 2 Schematic diagram of the software and hardware handshake interface according to the present invention.

[0025] Figure 3 It is a flow chart of the interaction between the SOC firmware (FW) and the IP FW according to the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Based on the above analysis, the present invention proposes a software and hardware handshake method and device for switching the working mode of a chip, which adopts the handshake interaction in communication technology and the handshake mechanism in digital development and design, and is applied to the handshake interaction design when digital development and design, and firmware, i.e., IP, is integrated into ASIC.

[0028] See also Figure 1 The software and hardware handshake method for switching the chip working mode provided by the present invention includes:

[0029] Step 101: Receive configuration information set by firmware, where the configuration information includes a protocol flow of a chip physical layer IP.

[0030] like Figure 2 As shown, the order of digital execution is modified by IP firmware configuration to implement different protocol adaptation processes. When meeting different protocol requirements, the present invention not only uses firmware to control its power-on, power-off, calibration and adaptive design process, but also configures this design process according to the firmware. The digital logic (hardware) of the IP automatically loads the configuration, and the subsequent power-on, power-off, calibration and adaptive processes can be fully or partially implemented by digital logic (hardware register-level transmission circuit RTL). When part of it is implemented by digital logic, a certain process can be selectively skipped or replaced by firmware. The firmware configures the process executed by the PHY IP according to different protocols and driving capability requirements.

[0031] Take the design process of power-on as an example. If the rate needs to be changed in the sending stage, jump to the sending rate configuration step of the configuration information, change the setting to disable or power off, modify the corresponding rate configuration, and then power on and run.

[0032] Similarly, if the rate needs to be changed during the receiving phase, jump to the receiving rate configuration step of the configuration information. For different protocol timing requirements, you can jump to the calibration initialization step to adjust the corresponding calibration, such as quickly calibrating when time requirements are strict. In addition, you can use the blank spare steps to align the platforms for different firmware versions during the development process, such as minimizing the number of verification regression cases during verification.

[0033] Step 102: Use digital logic to load and parse the configuration information, control the execution state of the state machine based on the configuration information, and switch the chip working mode by executing the protocol process.

[0034] For different test verifications (such as loopback test), you can use the firmware as the corresponding chip return test case, or a combination of multiple test cases. After the test verification is completed, you can select the corresponding test case as the performance screen for the chip test CP / final test FT.

[0035] fw_CFG_done is the IP firmware configuration completion signal, which can be implemented with registers to notify the digital logic firmware that the register group of static configuration has been completed, and the digital logic enters the normal power-on startup process, and controls the corresponding analog module power-on startup and calibration accordingly. Different application specifications, protocol startup processes, and execution state machine configurations can be configured. reset is a soft reset for different modules, which is an asynchronous reset. The modules can include a send enable module, a send disable module, a receive enable module, a receive disable module, and a reference clock switching module. req is a request from different modules, notifying the digital logic firmware to issue a corresponding request. req-ctrl-st-r is a request control state machine. seq st-r is a sequential state machine control (the state machine that actually executes the sequential control). ack is a handshake signal for notification confirmation of the digital logic. seq_en_r is a pre-configured process enable request. seq_done_r is a completion mark after the digital logic execution module completes the corresponding execution state machine process (Sequence). ctrl_req is a specific control request. ctrl_ack is a confirmation of specific control and an execution notification after the digital logic receives the request req.

[0036] After the system is reset, in the handshake idle state, the execution process of the firmware configuration is read in. For example, the state machine jumps from the idle state to the State0 state, and the corresponding power-on process is executed at this time. The power-off state also configures the execution process of different states. In an optional application example, the rate of fast switching PHY can also be powered off to the State1 state at the corresponding configuration rate, and then executed to the State0 state; different rates are implemented through the lookup table (LUT) to implement the specific configuration of the corresponding parameter switching.

[0037] The present invention can provide the following functions for the system on chip SOC (i.e. the core in ASIC integration) under different configuration protocols: Figure 3 The interactive handshake is used to control the execution of the corresponding process action, which is specifically executed in the digital logic. The host (ASIC) sends a request REQ to request a certain operation or service; when the IP FW receives the request message, it confirms it ACK, and the ASIC determines that the IP has received the request and proceeds to the next step.

[0038] In an optional embodiment, other solutions implement handshake interaction between IP firmware (FW) and digital logic, and different firmware versions can be used to control the working sequence of corresponding different protocol products, and switch the controlled nodes at different steps. When implementing the interaction between SOC FW and IP FW, the optional solution can use the method of modifying IP FW or calling the interface (API) of IP FW to implement it.

[0039] It can be seen that the software and hardware handshake method for switching the chip working mode proposed in the present invention has the following advantages compared with the related art:

[0040] Converting the actions executed by the original firmware into actions executed by the digital according to the firmware configuration can not only generalize and simplify the digital design in the digital-analog IP and speed up the running time, but also facilitate the firmware to configure the PHY IP execution process according to different protocols and driving capability requirements when integrating IP in ASIC. It only needs to issue different firmware configuration sequences in the CP / FT screening stage and different protocol product application ASICs, and the ASIC digital logic will be implemented according to the corresponding configuration, reducing the duplication of digital-analog mixed IP development and adapting to the digital development of different ASICs.

[0041] Accordingly, the present invention provides a hardware and software handshake device for switching chip working modes in a second aspect, comprising:

[0042] A firmware handshake interface unit, used to receive configuration information set by the firmware, wherein the configuration information includes a protocol flow of the chip physical layer IP;

[0043] A digital handshake control unit is used to load and parse the configuration information using digital logic, control the execution state of the state machine based on the configuration information, and switch the chip working mode by executing the protocol process.

[0044] The above-mentioned device can be implemented by the software and hardware handshake method for switching the chip working mode provided in the embodiment of the first aspect above. The specific implementation method can be found in the description of the embodiment of the first aspect, which will not be repeated here.

[0045] It is understood that the structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present invention to the specific details of the above examples.

[0046] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A software and hardware handshake method for switching chip working mode, It is characterized in that include: Receive configuration information set by the firmware, the configuration information including a protocol flow of a chip physical layer IP; The protocol process includes power-on, power-off, calibration or adaptive process, and the protocol process is fully implemented by digital logic, or partially implemented by digital logic and partially implemented by the firmware; the digital logic is a hardware register-level transmission circuit RTL; Using digital logic to load and parse the configuration information, controlling the execution state of the state machine based on the configuration information, and switching the chip working mode by executing the protocol process; When the protocol process is a power-on process, switching the chip working mode by executing the protocol process further includes: If the rate needs to be changed during the sending phase, jump to the sending rate configuration step of the configuration information, change to disable or power off, modify the corresponding rate configuration information, and then power on and run.

2. The software and hardware handshake method for switching chip working modes according to claim 1, It is characterized in that Before receiving the configuration information set by the firmware, the method further includes: The firmware sets corresponding configuration information according to different protocols and driving capability requirements.

3. The software and hardware handshake method for switching chip working modes according to claim 2, It is characterized in that The firmware is the firmware of the SOC.

4. The software and hardware handshake method for switching chip working modes according to claim 2, It is characterized in that The firmware is the firmware of the IP.

5. A hardware and software handshake device for switching chip working mode, It is characterized in that include: A firmware handshake interface unit, used to receive configuration information set by the firmware, wherein the configuration information includes a protocol flow of the chip physical layer IP; The protocol process includes power-on, power-off, calibration or adaptive process, and the protocol process is fully implemented by digital logic, or partially implemented by digital logic and partially implemented by the firmware; the digital logic is a hardware register-level transmission circuit RTL; A digital handshake control unit, used to load and parse the configuration information using digital logic, control the execution state of the state machine based on the configuration information, and switch the chip working mode by executing the protocol process; When the protocol process is a power-on process, the digital handshake control unit is further used to: If the rate needs to be changed during the sending phase, jump to the sending rate configuration step of the configuration information, change to disable or power off, modify the corresponding rate configuration information, and then power on and run.

6. The software and hardware handshake device for switching chip working modes according to claim 5, It is characterized in that Before receiving the configuration information set by the firmware, the firmware handshake interface unit is further used to: Set corresponding configuration information according to different protocols and drive capability requirements.

7. The software and hardware handshake device for switching chip working modes according to claim 5 or 6, It is characterized in that The firmware is the firmware of the SOC.

8. The software and hardware handshake device for switching chip working modes according to claim 5 or 6, It is characterized in that The firmware is the firmware of the IP.

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