Computing power accelerator card, design method and computing power server

Abstract

The present application provides a computing power acceleration card, a design method and a computing power server, wherein the computing power acceleration card includes: a circuit board, P computing power chips arranged on the circuit board; the computing power chip includes a packaging substrate and N computing power core silicon wafers arranged on the packaging substrate, N is greater than or equal to 1 and less than or equal to the threshold value of the number of computing power core silicon wafers allowed to be accommodated by a single computing power chip; the computing power core silicon wafer includes a computing power core unit and M high-speed serial interfaces connected to the computing power core unit, P and M are both greater than or equal to 1; the computing power core silicon wafers located on the same computing power chip form package-level interconnections through corresponding high-speed serial interfaces, and the computing power core silicon wafers located on different computing power chips form circuit board-level interconnections through corresponding high-speed serial interfaces; the computing power core units corresponding to the P computing power chips constitute a core computing module. The present application can improve the computing power capability of the computing power chip, reduce the chip packaging cost, and build a high-specification computing power acceleration card.

Description

Technical Field

[0001] The present application relates to the field of circuit design technology, and in particular to a computing power acceleration card, a design method and a computing power server. Background Art

[0002] Artificial intelligence applications represented by ChatGPT (Chat Generative Pre-trained Transformer) require a lot of computing power support. The computing power accelerator card is a circuit module unit with an embedded computing power chip, which is used to specifically process artificial intelligence and other applications. Common forms include PCIE (Peripheral Component Interconnect Express) accelerator card, OAM module (OCP Accelerator Module, open acceleration module based on OCP standard), etc.

[0003] A typical multi-card computing server includes a CPU (Central Processing Unit), hard disk, memory, motherboard, and multiple PCIE computing acceleration cards. Since the number of PCIE card slots in the server is fixed (the number of pluggable acceleration cards is fixed), the higher the computing power of a single card, the more cost-effective it is to amortize fixed costs such as CPU / hard disk.

[0004] At present, large-scale model applications such as generative AI (Artificial Intelligence) are bringing about epoch-making changes, and the global demand for computing power is showing an explosive growth trend. However, it is also facing challenges such as the difficulty in further improving the computing density of computing power servers and high costs.

[0005] On the other hand, as Moore's Law gradually slows down, the practice of relying on transistor process scaling to increase transistor density, increase chip area and thus improve performance has encountered a bottleneck. Chip technology has come into being, which can integrate multiple chip silicon wafers together using packaging technology, effectively reducing costs while improving performance.

[0006] Figure 1A as well as Figure 1B It shows the current two typical forms of high-performance computing acceleration cards. Figure 1A As a PCIE accelerator card that uses a single silicon chip, its performance is limited by the chip manufacturing process and the number of transistors is difficult to further increase. Figure 1B It is a PCIE accelerator card based on a single chip composed of multi-chip silicon wafers. Due to the use of chip technology, it has achieved a breakthrough Figure 1A The limitation of the chip package allows the number of transistors to be further increased. Figure 1BIn the solution, when the number of core silicon wafers is large, the packaging substrate area is large, the packaging cost rises sharply, and the packaging yield also faces challenges (a packaging failure of a silicon wafer will cause the entire chip to be scrapped), and the chip cost is difficult to reduce.

[0007] Therefore, there is an urgent need to solve the problem that the computing power specifications of traditional high-performance computing acceleration cards are difficult to further improve and the computing power costs are high. Summary of the invention

[0008] In view of the above problems, the embodiments of the present application provide a computing power acceleration card, a design method and a computing power server that overcome the above problems or at least partially solve the above problems.

[0009] In a first aspect, an embodiment of the present application provides a computing power acceleration card, including:

[0010] A circuit board, and P computing chips arranged on the circuit board;

[0011] The computing power chip includes a packaging substrate and N computing power core silicon wafers arranged on the packaging substrate, where N is an integer greater than or equal to 1 and less than or equal to the threshold value of the number of computing power core silicon wafers allowed to be accommodated by a single computing power chip;

[0012] The computing power core silicon wafer includes a computing power core unit and M high-speed serial interfaces, the M high-speed serial interfaces are respectively connected to the computing power core units, and P and M are both integers greater than or equal to 1;

[0013] Among them, the computing power core silicon wafers located on the same computing power chip form package-level interconnections through corresponding high-speed serial interfaces, and the computing power core silicon wafers located on different computing power chips form circuit board-level interconnections through corresponding high-speed serial interfaces; the computing power core units corresponding to the P computing power chips constitute a core computing module.

[0014] In a second aspect, an embodiment of the present application provides a computing power server, comprising at least one computing power acceleration card according to the first aspect, wherein the computing power acceleration card is disposed in a card slot of the computing power server;

[0015] In the case where the computing power server includes multiple computing power acceleration cards, a board-level interconnection is formed between the multiple computing power acceleration cards, and at least one board-level interconnection structure is present between two connected computing power acceleration cards.

[0016] In a third aspect, an embodiment of the present application provides a computing power acceleration card design method, including:

[0017] Providing a computing power core silicon wafer, wherein the computing power core silicon wafer includes a computing power core unit and M high-speed serial interfaces connected to the computing power core unit;

[0018] Based on the design rule that each computing chip includes N computing core silicon wafers, the computing core silicon wafers are packaged to obtain P computing chips, where N is an integer greater than or equal to 1 and less than or equal to the threshold number of computing core silicon wafers allowed to be accommodated by a single computing chip, and P and M are both integers greater than or equal to 1;

[0019] Arrange the P computing chips on a circuit board, establish circuit board-level interconnection between the computing chips, and obtain a computing acceleration card including the P computing chips;

[0020] Among them, the computing power core silicon wafers located on the same computing power chip form package-level interconnection through corresponding high-speed serial interfaces, and the computing power core silicon wafers located on different computing power chips form circuit board-level interconnection through corresponding high-speed serial interfaces; the computing power core units corresponding to the P computing power chips constitute a core computing module; when designing multiple computing power acceleration cards, board-level interconnection is established between the multiple computing power acceleration cards.

[0021] The technical solution of the embodiment of the present application adopts the core particle technology to interconnect N computing power core particle silicon wafers and then package them to build a computing power chip, arranges P computing power chips on the circuit board and interconnects the computing power core particle silicon wafers on different computing power chips based on the chip interconnection technology, so that the computing power core particle silicon wafers can be interconnected at the packaging level and the circuit board level, so as to realize the construction of a high-specification computing power acceleration card based on the interconnection between the computing power core particle silicon wafers; and by packaging at least one computing power core particle silicon wafer to build a computing power chip, the computing power capacity of a single computing power chip can be guaranteed, and by limiting the number of computing power core particle silicon wafers allowed to be accommodated by a single computing power chip, the packaging cost of a single computing power chip can be reduced, the packaging yield can be improved, and the chip cost can be reduced, thereby achieving a reasonable balance between computing power capacity requirements and cost requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A Schematic diagram 1 showing a high-performance computing acceleration card in the prior art;

[0023] Figure 1B Schematic diagram of a high-performance computing acceleration card in the prior art Figure 2 ;

[0024] Figure 2 Schematic diagram 1 showing a computing power acceleration card provided in an embodiment of the present application;

[0025] Figure 3 Schematic diagram of a computing power acceleration card provided in an embodiment of the present application Figure 2 ;

[0026] Figure 4 A schematic diagram showing a computing power core silicon wafer provided in an embodiment of the present application;

[0027] Figure 5A schematic diagram showing the interconnection of computing power acceleration cards provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram showing a computing power acceleration card design method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. The multiple in the embodiments of the present application can include two and more than two.

[0031] The present application embodiment provides a computing power acceleration card, such as Figures 2 to 4 As shown, the computing power acceleration card includes:

[0032] A circuit board 10, and P computing chips 11 arranged on the circuit board 10;

[0033] The computing chip 11 includes a packaging substrate 111 and N computing core silicon wafers 112 arranged on the packaging substrate 111, where N is an integer greater than or equal to 1 and less than or equal to the threshold value of the number of computing core silicon wafers allowed to be accommodated by a single computing chip 11;

[0034] The computing power core silicon wafer 112 includes a computing power core unit 1121 and M high-speed serial interfaces 1122, the M high-speed serial interfaces 1122 are respectively connected to the computing power core unit 1121, and P and M are both integers greater than or equal to 1;

[0035] Among them, the computing power core silicon wafers 112 located on the same computing power chip 11 form package-level interconnections through corresponding high-speed serial interfaces 1122, and the computing power core silicon wafers 112 located on different computing power chips 11 form circuit board-level interconnections through corresponding high-speed serial interfaces 1122; the computing power core units 1121 corresponding to P computing power chips 11 constitute a core computing module.

[0036] The computing power acceleration card provided in the embodiment of the present application includes a circuit board 10 and P computing power chips 11 arranged on the circuit board 10, where the value of P is greater than or equal to 1. That is, the computing power acceleration card is formed by arranging at least one computing power chip 11 on the circuit board 10 and establishing interconnections between the computing power chips 11. The number of computing power chips 11 that can be arranged on the circuit board 10 is related to the area of ​​the circuit board 10 and the size of the computing power chip 11.

[0037] The computing chip 11 includes a packaging substrate 111 and N computing core silicon wafers 112 arranged on the packaging substrate 111, and the computing core silicon wafer 112 includes multiple transistors. The value of N is greater than or equal to 1. By arranging one or more computing core silicon wafers 112 on the packaging substrate 111, the number of transistors that can be accommodated in a single computing chip 11 can be guaranteed, thereby ensuring the computing power of a single computing chip 11; and the value of N is less than or equal to the threshold value of the number of computing core silicon wafers allowed to be accommodated by a single computing chip 11. By limiting the number of computing core silicon wafers 112 allowed to be accommodated by a single computing chip 11, the packaging cost of a single computing chip 11 can be reduced, the packaging yield can be improved, and the chip cost can be reduced.

[0038] It should be noted that the threshold value of the number of computing core silicon wafers allowed to be accommodated by a single computing power chip 11 is a threshold value determined by experiments. By setting the number of computing core silicon wafers 112 included in the computing power chip 11 based on the determined threshold value, the computing power capacity requirements and cost requirements can be reasonably balanced. For example, if the threshold value of the number of computing core silicon wafers 112 allowed to be accommodated by a single computing power chip 11 is 10, then the value of N is greater than or equal to 1 and less than or equal to 10. By limiting the value range of N, the packaging yield can be improved while ensuring the computing power of a single computing power chip 11, thereby achieving a reasonable balance between computing power capacity requirements and cost requirements.

[0039] When at least two computing chips 11 are arranged on the circuit board 10, the number of computing core silicon wafers 112 corresponding to different computing chips 11 may be different, or different computing chips 11 may deploy the same number of computing core silicon wafers 112 but have different layouts, or different computing chips 11 may deploy the same number of computing core silicon wafers 112 and have the same layout. Figure 3 As shown, four computing chips 11 are arranged on the circuit board 10, each computing chip 11 includes two computing core silicon wafers 112, and the layout of the computing core silicon wafers 112 on the computing chip 11 is the same. At this time, different computing chips 11 deploy the same number and the same layout of computing core silicon wafers 112.

[0040] like Figures 2 to 4As shown, for the computing power core silicon wafer 112, it includes a computing power core unit 1121 and M high-speed serial interfaces 1122, and the value of M is greater than or equal to 1, that is, each computing power core silicon wafer 112 corresponds to at least one high-speed serial interface 1122. The number of high-speed serial interfaces 1122 corresponding to different computing power core silicon wafers 112 belonging to the same computing power chip 11 can be exactly the same or different; the number of high-speed serial interfaces 1122 corresponding to computing power core silicon wafers 112 belonging to different computing power chips 11 can be different or exactly the same.

[0041] The M high-speed serial interfaces 1122 corresponding to the computing power chip silicon wafer 112 are all connected to the computing power core unit 1121, so that the computing power core unit 1121 in the current computing power chip silicon wafer is connected to the computing power core unit 1121 in other computing power chip silicon wafers through the high-speed serial interface 1122.

[0042] The high-speed serial interface 1122 in the embodiment of the present application is used to connect different computing power core silicon wafers 112, and different computing power core silicon wafers 112 deployed on the same computing power chip 11 can be connected through the high-speed serial interface 1122, and computing power core silicon wafers 112 deployed on different computing power chips 11 can also be connected through the high-speed serial interface 1122.

[0043] For different computing power core silicon wafers 112 located on the same computing power chip 11, they form package-level interconnections through corresponding high-speed serial interfaces 1122. For computing power core silicon wafers 112 located on different computing power chips 11, they form circuit board-level interconnections through corresponding high-speed serial interfaces 1122.

[0044] When one computing power chip 11 is arranged on the circuit board 10, since there is no connection between the computing power core silicon wafers 112 on different computing power chips 11, at this time, at least two computing power core silicon wafers 112 on the computing power chip 11 form a package-level interconnection through the corresponding high-speed serial interface 1122; when at least two computing power chips 11 are arranged on the circuit board 10, in addition to the different computing power core silicon wafers 112 located on the same computing power chip 11 forming a package-level interconnection through the corresponding high-speed serial interface 1122, the computing power core silicon wafers 112 can also be connected at the circuit board level between different computing power chips 11.

[0045] Since different computing power core silicon wafers 112 in the same computing power chip 11 can be interconnected, and the computing power core silicon wafers 112 located on different computing power chips 11 can be interconnected, the computing power core units 1121 corresponding to P computing power chips 11 can be combined into a core computing module through the interconnection between the computing power core silicon wafers 112 to construct the core components of a high-specification computing power acceleration card.

[0046] The above implementation scheme of the present application adopts the core particle technology to interconnect N computing power core particle silicon wafers and then package them to construct a computing power chip, arranges P computing power chips on the circuit board and interconnects the computing power core particle silicon wafers located on different computing power chips based on the chip interconnection technology, so that the computing power core particle silicon wafers can be interconnected at the packaging level and the circuit board level, so as to realize the construction of a high-specification computing power acceleration card based on the interconnection between the computing power core particle silicon wafers; and by packaging at least one computing power core particle silicon wafer to construct a computing power chip, the computing power capacity of a single computing power chip can be guaranteed, and by limiting the number of computing power core particle silicon wafers allowed to be accommodated by a single computing power chip, the packaging cost of a single computing power chip can be reduced, the packaging yield can be improved, and the chip cost can be reduced, thereby achieving a reasonable balance between computing power capacity requirements and cost requirements.

[0047] The high-speed serial interface provided in the embodiment of the present application is introduced below. Figure 3 and Figure 4 As shown, the M high-speed serial interfaces 1122 of the computing power core silicon wafer 112 correspond to the same interface structure, and the interface structures of the high-speed serial interfaces 1122 corresponding to different computing power core silicon wafers 112 are the same; and the high-speed serial interface 1122 is a unified interconnection interface that can be used as a package interconnection interface and a circuit board interconnection interface.

[0048] In the embodiment of the present application, the interface structures of the M high-speed serial interfaces 1122 corresponding to a single computing power core silicon wafer 112 are the same, that is, for any computing power core silicon wafer 112, when the number of the high-speed serial interfaces 1122 corresponding to it is greater than 1, the interface structures of the various high-speed serial interfaces 1122 are the same. For different computing power core silicon wafers 112, the high-speed serial interfaces 1122 corresponding to the same interface structure, that is, different computing power core silicon wafers 112 share the high-speed serial interfaces 1122 with the same interface structure.

[0049] The high-speed serial interface 1122 provided in the embodiment of the present application is a unified interconnection interface for interconnecting the computing power core silicon wafers 112, and the unified interconnection interface can be used as both a package interconnection interface and a circuit board interconnection interface. The package interconnection interface is an interface for connecting the computing power core silicon wafers 112 located on the same package substrate 111, and the circuit board interconnection interface is an interface for connecting the computing power core silicon wafers 112 located on different package substrates 111.

[0050] By adopting a unified computing core silicon wafer interconnection interface to expand the computing power of a single computing chip, there is no need to design two sets of interfaces for package-level interconnection and circuit board-level interconnection respectively, which reduces the complexity of interconnection and controls costs. At the same time, this design can adapt to computing chips of different forms.

[0051] Alternatively, if Figure 3As shown, a substrate connection 113 is arranged between two connected computing power core silicon wafers 112 located on the same computing power chip 11, and the corresponding high-speed serial interfaces 1122 of the two computing power core silicon wafers 112 are connected through the substrate connection 113; a circuit board connection 114 is arranged between two connected computing power core silicon wafers 112 located on different computing power chips 11, and the corresponding high-speed serial interfaces 1122 of the two computing power core silicon wafers 112 are connected through the circuit board connection 114.

[0052] A substrate connection line 113 is provided on the package substrate 111 of the computing power chip 11. The substrate connection line 113 is used to connect the computing power core silicon wafer 112 located on the same computing power chip 11, and the two ends of the substrate connection line 113 are respectively connected to the corresponding high-speed serial interfaces 1122 on the two computing power core silicon wafers 112. That is, the two computing power core silicon wafers 112 located on the same computing power chip 11 that can form a connection relationship are connected by the substrate connection line 113 arranged on the package substrate 111, thereby realizing the connection between the two computing power core silicon wafers 112. At this time, the high-speed serial interface 1122 is used as a package interconnection interface for connecting the two computing power core silicon wafers 112 on the same package substrate 111.

[0053] A circuit board connection 114 is provided on the circuit board 10. The circuit board connection 114 is used to connect the computing power core silicon wafers 112 located on different computing power chips 11, and the two ends of the circuit board connection 114 are respectively connected to the corresponding high-speed serial interfaces 1122 of the two computing power core silicon wafers 112 located on different packaging substrates 111. That is, the two computing power core silicon wafers 112 located on different computing power chips 11 that can form a connection relationship are connected by the circuit board connection 114 arranged on the circuit board 10, thereby realizing the connection between the two computing power core silicon wafers 112 located on different packaging substrates 111. At this time, the high-speed serial interface 1122 is used as a circuit board interconnection interface to connect the two computing power core silicon wafers 112 on different packaging substrates 111.

[0054] Since the high-speed serial interface 1122 is a unified interconnection interface for interconnecting the computing power core silicon wafers 112, the unified interconnection interface can be used as a packaging interconnection interface or as a circuit board interconnection interface. When connecting two computing power core silicon wafers 112 located on the same packaging substrate 111, the packaging interconnection function of the high-speed serial interface 1122 is used to realize the connection between different computing power core silicon wafers 112 on the same packaging substrate 111; when connecting two computing power core silicon wafers 112 located on different packaging substrates 111, the circuit board interconnection function of the high-speed serial interface 1122 is used to realize the connection between the computing power core silicon wafers 112 on different packaging substrates 111; and further, the packaging interconnection function and circuit board interconnection function of the high-speed serial interface 1122 can be used to reduce the complexity of interconnection and control costs.

[0055] Alternatively, if Figure 3 As shown, the high-speed serial interface 1122 supports adjusting the transmission rate; when the high-speed serial interface 1122 is connected to two computing core silicon wafers 112 located on the same computing power chip 11 through the substrate connection 113, the high-speed serial interface 1122 corresponds to the first transmission rate; when the high-speed serial interface 1122 is connected to two computing core silicon wafers 112 located on different computing power chips 11 through the circuit board connection 114, the high-speed serial interface 1122 corresponds to the second transmission rate;

[0056] The first transmission rate is the transmission rate corresponding to the substrate connection 113 , the second transmission rate is the transmission rate corresponding to the circuit board connection 114 , and the first transmission rate is greater than or equal to the second transmission rate.

[0057] Due to the different physical properties of the packaging substrate 111 and the circuit board 10, different transmission rates can be configured for the substrate connection 113 arranged on the packaging substrate 111 and the circuit board connection 114 arranged on the circuit board 10. The transmission rate here is the rate at which data is transmitted through the substrate connection 113 and the circuit board connection 114, which can also be referred to as the connection rate of the substrate connection 113 and the circuit board connection 114.

[0058] The transmission rate corresponding to the substrate connection 113 is the first transmission rate, and the transmission rate corresponding to the circuit board connection 114 is the second transmission rate. Since the circuit board connection 114 needs to cross different packaging substrates 111, the transmission rate corresponding to the circuit board connection 114 usually needs to be reduced, and the transmission rate corresponding to the substrate connection 113 arranged on the packaging substrate 111 is greater than or equal to the transmission rate corresponding to the circuit board connection 114, that is, the first transmission rate needs to be greater than or equal to the second transmission rate.

[0059] Since the high-speed serial interface 1122 is a unified interconnection interface, when the high-speed serial interface 1122 corresponds to the package interconnection function, the connection of the two high-speed serial interfaces 1122 is realized through the substrate connection 113, and when the high-speed serial interface 1122 corresponds to the circuit board interconnection function, the connection of the two high-speed serial interfaces 1122 is realized through the circuit board connection 114. Therefore, the high-speed serial interface 1122 supports the adjustment of the transmission rate. For the high-speed serial interface 1122 that connects the two computing core silicon wafers 112 located on the same computing power chip 11 through the substrate connection 113, it corresponds to the first transmission rate; for the high-speed serial interface 1122 that connects the two computing core silicon wafers 112 located on different computing power chips 11 through the circuit board connection 114, it corresponds to the second transmission rate.

[0060] From another perspective, a high-speed serial interface 1122 supports two working modes, one is the package interconnection mode, and the other is the circuit board interconnection mode. When the high-speed serial interface 1122 is in the package interconnection mode, it corresponds to the first transmission rate, and when the high-speed serial interface 1122 is in the circuit board interconnection mode, it corresponds to the second transmission rate. When the high-speed serial interface 1122 is used for package interconnection, the high-speed serial interface 1122 is connected to other high-speed serial interfaces 1122 through the substrate connection 113, and when the high-speed serial interface 1122 is used for circuit board interconnection, the high-speed serial interface 1122 is connected to other high-speed serial interfaces 1122 through the circuit board connection 114.

[0061] For any computing power core silicon wafer 112, it includes one or more high-speed serial interfaces 1122. If it only needs to be connected to other computing power core silicon wafers 112 located on the same packaging substrate 111, it can be connected to other one or more computing power core silicon wafers 112 located on the same packaging substrate 111 through one high-speed serial interface 1122, or it can be connected to other multiple computing power core silicon wafers 112 located on the same packaging substrate 111 through multiple high-speed serial interfaces 1122. At this time, when the high-speed serial interface 1122 is in the package interconnection mode, it corresponds to the first transmission rate.

[0062] If the computing power core silicon wafer 112 needs to be connected to other computing power core silicon wafers 112 located on the same packaging substrate 111, or needs to be connected to other computing power core silicon wafers 112 located on different packaging substrates 111, then the computing power core silicon wafer 112 needs to correspond to at least two high-speed serial interfaces 1122. The at least two high-speed serial interfaces 1122 are divided into two categories, one for use as a packaging interconnection interface, and the other for use as a circuit board interconnection interface. The packaging interconnection interface corresponds to a first transmission rate, and the circuit board interconnection interface corresponds to a second transmission rate.

[0063] The above introduces the scheme of connecting the computing power core silicon wafers with the high-speed serial interface in the embodiment of the present application. By providing a unified interconnection interface for interconnecting the computing power core silicon wafers, there is no need to design two sets of interfaces for package-level interconnection and circuit board-level interconnection respectively, thereby reducing the complexity of interconnection and controlling costs; and the high-speed serial interface supports adjustment of the transmission rate, which corresponds to the first transmission rate when connecting the computing power core silicon wafers on the same packaging substrate through substrate connections, and corresponds to the second transmission rate when connecting the computing power core silicon wafers on different packaging substrates through circuit board connections, thereby realizing data transmission between the computing power core silicon wafers at an adapted transmission rate while connecting the computing power core silicon wafers.

[0064] The following is an introduction to the connection between the computing power core silicon wafers in the computing power chip and the connection between computing power chips. Figure 3 As shown, in the computing power chip 11, the first computing power core silicon wafer is connected to at least one second computing power core silicon wafer; the first computing power core silicon wafer is any one of the N computing power core silicon wafers 112 included in the computing power chip 11, and the remaining (N-1) computing power core silicon wafers 112 are all second computing power core silicon wafers.

[0065] For any computing power chip 11, the first computing power core silicon wafer included therein is connected to at least one second computing power core silicon wafer, the first computing power core silicon wafer is any computing power core silicon wafer 112 among the N computing power core silicon wafers 112, and the other (N-1) computing power core silicon wafers 112 that are different from the first computing power core silicon wafer among the N computing power core silicon wafers 112 are all second computing power core silicon wafers. That is, the first computing power core silicon wafer is connected to at least one second computing power core silicon wafer, and can also be connected to multiple second computing power core silicon wafers, and there is no situation where any computing power core silicon wafer 112 in the computing power chip 11 is deployed in isolation and is not connected to other computing power core silicon wafers 112 on the same packaging substrate 111. If there is an isolated computing power core silicon wafer 112 on a packaging substrate 111, there is no need to package the computing power core silicon wafer 112 on the current packaging substrate 111. Therefore, there is no situation where any computing power core silicon wafer 112 in the computing power chip 11 is deployed in isolation.

[0066] As an example, when the value of N is 2, the computing power chip 11 includes a first computing power core silicon wafer and a second computing power core silicon wafer, and at this time, the first computing power core silicon wafer is connected to the second computing power core silicon wafer. When the value of N is 3, the computing power chip 11 includes computing power core silicon wafer A, computing power core silicon wafer B, and computing power core silicon wafer C. The computing power core silicon wafer A can be connected to at least one of the computing power core silicon wafer B and the computing power core silicon wafer C. For example, the computing power core silicon wafer A is connected to the computing power core silicon wafer B. Since the computing power core silicon wafer C is not allowed to be deployed in isolation, the computing power core silicon wafer C is connected to the computing power core silicon wafer B. At this time, the connection form of the computing power core silicon wafer A connecting the computing power core silicon wafer B and the computing power core silicon wafer C connecting the computing power core silicon wafer B is formed. Alternatively, the computing power core silicon wafer A is connected to the computing power core silicon wafer B and the computing power core silicon wafer C. In this case, the computing power core silicon wafer B may be connected to the computing power core silicon wafer C or may not be connected to the computing power core silicon wafer C. For the case where N is other values, they are not listed here one by one. Regardless of the value of N, it is necessary to ensure that there are no isolated computing power core silicon wafers deployed on the same packaging substrate 111.

[0067] like Figure 3 As shown, when at least two computing chips 11 are arranged on the circuit board 10, the first computing chip is connected to at least one second computing chip, and at least one circuit board connection line 114 is deployed between the connected first computing chip and the second computing chip; wherein, the first computing chip is any one of the at least two computing chips 11, and the other computing chips 11 different from the first computing chip are second computing chips.

[0068] The computing power acceleration card provided in the embodiment of the present application includes P computing power chips 11. When the value of P is greater than or equal to 2, at least two computing power chips 11 are arranged on the circuit board 10. A first computing power chip among the at least two computing power chips 11 is connected to at least one second computing power chip. The first computing power chip is any one of the at least two computing power chips 11. The other computing power chips 11 among the at least two computing power chips 11 that are different from the first computing power chip are second computing power chips.

[0069] One or more circuit board connections 114 are deployed between the connected first computing power chip and the second computing power chip. In the case where one circuit board connection 114 is deployed between the first computing power chip and the second computing power chip, a computing power core silicon wafer 112 in the first computing power chip is connected to a computing power core silicon wafer 112 in the second computing power chip; in the case where multiple circuit board connections 114 are deployed between the first computing power chip and the second computing power chip, at least one computing power core silicon wafer 112 in the first computing power chip is connected to multiple computing power core silicon wafers 112 in the second computing power chip, that is, one computing power core silicon wafer 112 in the first computing power chip can be connected to multiple computing power core silicon wafers 112 in the second computing power chip, or multiple computing power core silicon wafers 112 in the first computing power chip can be connected one-to-one with multiple computing power core silicon wafers 112 in the second computing power chip, or other connection situations can be used, which will not be elaborated here one by one. Figure 3 Schematic diagram of the case where one circuit board connection line 114 is arranged between two connected computing power chips 11 and two circuit board connections 114 are arranged between two connected computing power chips 11.

[0070] As an example, two computing chips 11 are arranged on the circuit board 10, namely, computing chip E and computing chip F, and a circuit board connection 114 is arranged between computing chip E and computing chip F, and computing chip E and computing chip F are connected through the circuit board connection 114. Alternatively, computing chip E and computing chip F respectively include two computing core silicon wafers 112, and the two computing core silicon wafers 112 in computing chip E correspond to the two computing core silicon wafers 112 in computing chip F one by one, and one computing core silicon wafer 112 in computing chip E is connected to one computing core silicon wafer 112 in computing chip F through the circuit board connection 114, and another computing core silicon wafer 112 in computing chip E is connected to another computing core silicon wafer 112 in computing chip F through the circuit board connection 114.

[0071] When other numbers of computing chips 11 are arranged on the circuit board 10, any computing chip 11 is connected to at least one other computing chip 11, and there is at least one circuit board connection line 114 between the two connected computing chips 11, and the details are not listed one by one.

[0072] It should be noted that Figure 3 The connection between the computing power core silicon wafers 112 in the same packaging substrate 111 and the connection between the computing power core silicon wafers 112 on different packaging substrates 111 form a two-dimensional grid topology structure. The connection between the computing power core silicon wafers 112 can also be other topological interconnection methods, such as star topology, fully connected topology, ring topology, etc.

[0073] The above introduces the connection conditions of the computing power core silicon wafers on the same packaging substrate and the connection conditions between different computing power chips in the embodiment of the present application. For the computing power core silicon wafers located on the same packaging substrate, by setting any computing power core silicon wafer to be connected to at least one other computing power core silicon wafer, it is possible to avoid the situation where the computing power core silicon wafer is isolated on the packaging substrate; for the connected computing power chips, by setting one or more circuit board connections, the interconnection between the computing power chips can be established based on at least one connection path.

[0074] The above is the overall implementation plan of the computing power acceleration card provided in the embodiment of the present application. By adopting the core particle technology to interconnect N computing power core particle silicon wafers and then package them to construct a computing power chip, P computing power chips are arranged on the circuit board and the computing power core particle silicon wafers located on different computing power chips are interconnected based on the chip interconnection technology. The computing power core particle silicon wafers can be interconnected at the packaging level and the circuit board level to realize the construction of a high-specification computing power acceleration card based on the interconnection between the computing power core particle silicon wafers; and by packaging at least one computing power core particle silicon wafer to construct a computing power chip, the computing power capacity of a single computing power chip can be guaranteed. By limiting the number of computing power core particle silicon wafers allowed to be accommodated by a single computing power chip, the packaging cost of a single computing power chip can be reduced, the packaging yield can be improved, and the chip cost can be reduced, thereby achieving a reasonable balance between computing power capacity requirements and cost requirements.

[0075] Furthermore, by providing a unified interconnection interface for interconnecting computing power core silicon wafers, there is no need to design two sets of interfaces for package-level interconnection and circuit board-level interconnection respectively, thereby reducing interconnection complexity and controlling costs; by setting a high-speed serial interface to support adjustment of the transmission rate, when connecting computing power core silicon wafers on the same packaging substrate through substrate connections, it corresponds to the first transmission rate, and when connecting computing power core silicon wafers on different packaging substrates through circuit board connections, it corresponds to the second transmission rate, thereby realizing data transmission between computing power core silicon wafers at an adapted transmission rate while connecting the computing power core silicon wafers.

[0076] For computing power core silicon wafers located on the same packaging substrate, by setting any computing power core silicon wafer to be connected to at least one other computing power core silicon wafer, it is possible to avoid the situation where the computing power core silicon wafer is isolated on the packaging substrate; for connected computing power chips, by setting one or more circuit board connections, interconnection between the computing power chips can be established based on at least one connection path.

[0077] An embodiment of the present application also provides a computing power server, comprising at least one computing power acceleration card in the above-mentioned embodiment, and the computing power acceleration card is arranged in a card slot of the computing power server; when the computing power server includes multiple computing power acceleration cards, a board-level interconnection is formed between the multiple computing power acceleration cards, and at least one board-level interconnection structure is present between two connected computing power acceleration cards.

[0078] The computing power server provided in the embodiment of the present application includes at least one card slot, and the card slot is used to accommodate the computing power acceleration card in the above embodiment. Since the computing power acceleration card includes P computing power chips, each computing power chip includes N computing power core silicon wafers, the computing power core silicon wafers on the same computing power chip can form package-level interconnections, and the computing power core silicon wafers on different computing power chips can form circuit board-level interconnections, which can ensure the computing power specifications of the computing power acceleration card. By setting one or more computing power acceleration cards in the corresponding card slots, when the computing power server includes multiple computing power acceleration cards, board-level interconnections of the computing power acceleration cards are formed, which can ensure the computing power performance of the computing power server.

[0079] In the case where the computing power server includes multiple computing power acceleration cards, a board-level interconnection is formed between any computing power acceleration card and at least one other computing power acceleration card. For two connected computing power acceleration cards, a board-level interconnection is formed between the two through a board-bridge, and a dedicated interconnection chip can also be used to form a board-level interconnection; and there is at least one board-level interconnection structure between the two connected computing power acceleration cards. Among them, the connection between the computing power acceleration cards is realized by the connection between the computing power core silicon wafers, specifically, by the connection between the high-speed serial interfaces on the computing power core silicon wafers. And for the two connected computing power acceleration cards, the connection between the two is realized by a pair of computing power core silicon wafers or a plurality of pairs of computing power core silicon wafers, where a pair of computing power core silicon wafers includes a computing power core silicon wafer located on one computing power acceleration card and a computing power core silicon wafer located on another computing power acceleration card. Each pair of computing power core silicon wafers corresponds to a board-level interconnection structure, so there is at least one board-level interconnection structure between the two connected computing power acceleration cards.

[0080] As an example, Figure 5 As shown, two computing power acceleration cards (computing power acceleration card A and computing power acceleration card B) each include 4 computing power chips, and 2 computing power core silicon wafers are deployed on each computing power chip. Four connection paths are formed between the two computing power acceleration cards, and each connection path corresponds to a board-level interconnection structure. Specifically, the computing power core silicon wafer a1 in the computing power chip A1 in the computing power acceleration card A is connected to the computing power core silicon wafer b1 in the computing power chip B1 in the computing power acceleration card B through a board bridge; the computing power core silicon wafer a1' in the computing power chip A1 in the computing power acceleration card A is connected to the computing power core silicon wafer b1' in the computing power chip B1 in the computing power acceleration card B through a board bridge; the computing power core silicon wafer a2 in the computing power chip A2 in the computing power acceleration card A is connected to the computing power core silicon wafer b2 in the computing power chip B2 in the computing power acceleration card B through a board bridge; the computing power core silicon wafer a2' in the computing power chip A2 in the computing power acceleration card A is connected to the computing power core silicon wafer b2' in the computing power chip B2 in the computing power acceleration card B through a board bridge.

[0081] The computing power server provided in the embodiment of the present application deploys one or more high-specification computing power acceleration cards provided in the above-mentioned embodiments. When the computing power server includes multiple computing power acceleration cards, board-level interconnection of the computing power acceleration cards is formed, which can ensure the computing power performance of the computing power server.

[0082] The present application also provides a method for designing a computing power acceleration card. Figure 6 As shown, the method includes:

[0083] Step 601: Provide a computing power core silicon wafer, which includes a computing power core unit and M high-speed serial interfaces connected to the computing power core unit, where M is an integer greater than or equal to 1.

[0084] When designing a computing power acceleration card, the embodiment of the present application first provides a computing power core silicon wafer, and the number of computing power core silicon wafers provided is multiple, and in special cases, it is 1. The computing power core silicon wafer includes a computing power core unit and at least one high-speed serial interface connected to the computing power core unit. The number of high-speed serial interfaces corresponding to different computing power core silicon wafers can be the same or different.

[0085] The interface structures of the M high-speed serial interfaces corresponding to a single computing power chip silicon wafer are the same. Different computing power chip silicon wafers correspond to high-speed serial interfaces with the same interface structure, that is, different computing power chip silicon wafers share high-speed serial interfaces with the same interface structure.

[0086] Step 602: Based on the design rule that each computing power chip includes N computing power core silicon wafers, the computing power core silicon wafers are packaged to obtain P computing power chips, where N is an integer greater than or equal to 1 and less than or equal to the threshold number of computing power core silicon wafers allowed to be accommodated by a single computing power chip, and P is an integer greater than or equal to 1.

[0087] After providing computing power core silicon wafers, based on the design rule that each computing power chip includes N computing power core silicon wafers, the computing power core silicon wafers are packaged using a packaging substrate to obtain P computing power chips. The value of P is greater than or equal to 1, that is, the computing power core silicon wafers are packaged according to the design rule to obtain at least one computing power chip.

[0088] The value of N is greater than or equal to 1. By designing a computing chip including at least one computing core silicon wafer, the number of transistors that a single computing chip can accommodate can be guaranteed, thereby ensuring the computing power of a single computing chip; and the value of N is less than or equal to the threshold number of computing core silicon wafers allowed to be accommodated by a single computing chip. By limiting the number of computing core silicon wafers allowed to be accommodated by a single computing chip, the packaging cost of a single computing chip can be reduced, the packaging yield can be improved, and the chip cost can be reduced.

[0089] Step 603: arrange P computing chips on a circuit board, establish circuit board-level interconnection between the computing chips, and obtain a computing acceleration card including the P computing chips; wherein, the computing core silicon wafers located on the same computing chip form package-level interconnection through corresponding high-speed serial interfaces, and the computing core silicon wafers located on different computing chips form circuit board-level interconnection through corresponding high-speed serial interfaces; the computing core units corresponding to the P computing chips constitute a core computing module; when designing multiple computing acceleration cards, establish board-level interconnection between the multiple computing acceleration cards.

[0090] After P computing chips are obtained through packaging, the P computing chips are arranged on a circuit board, and circuit board-level interconnections are established between the computing chips, thereby obtaining a computing acceleration card. The number of computing chips arranged on the circuit board is determined based on the number of computing core silicon wafers provided. When providing computing core silicon wafers, the area of ​​the circuit board and the design rules need to be considered, and an adapted number of computing core silicon wafers are provided.

[0091] The high-speed serial interface in the embodiment of the present application is used to connect different computing power core silicon wafers, and different computing power core silicon wafers deployed on the same computing power chip can be connected through the high-speed serial interface, and computing power core silicon wafers deployed on different computing power chips can also be connected through the high-speed serial interface, thereby realizing the connection of different computing power chips. For different computing power core silicon wafers located on the same computing power chip, they form package-level interconnection through corresponding high-speed serial interfaces, and for computing power core silicon wafers located on different computing power chips, they form circuit board-level interconnection through corresponding high-speed serial interfaces.

[0092] Since different computing power core silicon wafers in the same computing power chip can be interconnected, and computing power core silicon wafers located on different computing power chips can be interconnected, the computing power core units corresponding to P computing power chips can be combined into a core computing module through the interconnection between the computing power core silicon wafers to build the core components of a high-specification computing power acceleration card.

[0093] The above design process builds a computing chip based on N computing core silicon wafers, arranges P computing chips on the circuit board and interconnects different computing chips based on chip interconnection technology, so as to build a high-specification computing acceleration card; and by packaging at least one computing core silicon wafer to build a computing chip, the computing power capacity of a single computing chip can be guaranteed. By limiting the number of computing core silicon wafers allowed to be accommodated by a single computing chip, the packaging cost of a single computing chip can be reduced, the packaging yield can be improved, and the chip cost can be reduced, thereby achieving a reasonable balance between computing power capacity requirements and cost requirements.

[0094] It should be noted that, for the special case of providing a computing power core silicon wafer, the computing power acceleration card includes a computing power chip, and the computing power chip includes a computing power core silicon wafer. For the case of designing multiple computing power acceleration cards, a board-level interconnection can be established between multiple computing power acceleration cards. For any computing power acceleration card, a board-level interconnection is formed between it and at least one other computing power acceleration card. For two connected computing power acceleration cards, a board-level interconnection is formed between the two through a board bridge, or a dedicated interconnection chip can be used to form a board-level interconnection; and there is at least one board-level interconnection structure between the two connected computing power acceleration cards. For the specific situation of the interconnection between the computing power acceleration cards, please refer to the relevant introduction of the above-mentioned computing power server embodiment, which will not be repeated here.

[0095] As an optional embodiment, when each computing power chip includes N computing power core silicon wafers based on the design rule that the computing power core silicon wafers are packaged, and P computing power chips are obtained, the following steps are included:

[0096] Providing P packaging substrates;

[0097] Based on the layout strategy of arranging N computing power core silicon wafers on each packaging substrate, the first connection rule is used to establish the package-level interconnection between the N computing power core silicon wafers on the same packaging substrate, and the computing power core silicon wafers are packaged to obtain P computing power chips;

[0098] Among them, the first connection rule is the connection rule between the computing core silicon wafers deployed on the same computing power chip. The corresponding high-speed serial interfaces of two connected computing core silicon wafers on the same computing power chip form a package-level interconnection through substrate wiring, and the first transmission rate corresponding to the high-speed serial interface is the transmission rate corresponding to the substrate wiring.

[0099] In this embodiment, the computing power chip includes a packaging substrate and N computing power core silicon wafers. When P computing power chips are obtained by packaging the computing power core silicon wafers, P packaging substrates are provided. Based on the layout strategy of arranging the N computing power core silicon wafers on each packaging substrate, the N computing power core silicon wafers corresponding to each packaging substrate are determined. For each packaging substrate, the first connection rule is used to establish packaging-level interconnection between the N computing power core silicon wafers on the same packaging substrate, and the N computing power core silicon wafers are packaged, thereby obtaining P computing power chips.

[0100] The number of packaging substrates required is determined based on the number of computing power core silicon wafers provided and the number of computing power core silicon wafers corresponding to a single computing power chip. The first connection rule is the connection rule between computing power core silicon wafers deployed on the same computing power chip. In a computing power chip, any computing power core silicon wafer is connected to at least one other computing power core silicon wafer, that is, for any computing power core silicon wafer among the N computing power core silicon wafers included in the computing power chip, the computing power core silicon wafer is connected to at least one of the (N-1) computing power core silicon wafers.

[0101] The high-speed serial interface in the embodiment of the present application is a unified interconnection interface for interconnecting computing core silicon wafers. The unified interconnection interface can be used as a package interconnection interface, which is an interface for connecting computing core silicon wafers located on the same package substrate. For two connected computing core silicon wafers on the same computing chip, their corresponding high-speed serial interfaces (package interconnection interfaces) form package-level interconnections through substrate wiring.

[0102] The substrate connection is a connection arranged on the packaging substrate. The substrate connection is used to connect the computing core silicon wafers located on the same computing power chip, and the two ends of the substrate connection are respectively connected to the corresponding high-speed serial interfaces on the two computing core silicon wafers. That is, the two computing core silicon wafers located on the same computing power chip that can form a connection relationship, their corresponding high-speed serial interfaces are connected through the substrate connection arranged on the packaging substrate, thereby realizing the connection between the two computing core silicon wafers. Since the substrate connection is used to connect the packaging interconnection interface, the transmission rate corresponding to the substrate connection is the first transmission rate, so the packaging interconnection interface corresponds to the first transmission rate.

[0103] Optionally, when P computing chips are arranged on a circuit board, circuit board-level interconnection is established between the computing chips, and a computing acceleration card including the P computing chips is obtained, the following steps are included:

[0104] Providing a circuit board;

[0105] Arrange P computing chips on the circuit board, establish circuit board-level interconnection between the P computing chips based on the second connection rule, and obtain a computing acceleration card;

[0106] Among them, the second connection rule is the connection rule between computing power core silicon wafers deployed on different computing power chips. The corresponding high-speed serial interfaces of two connected computing power core silicon wafers located on different computing power chips form circuit board-level interconnection through circuit board connections, and the second transmission rate corresponding to the high-speed serial interface is the transmission rate corresponding to the circuit board connection.

[0107] After P computing chips are obtained through packaging, P computing chips are arranged on the provided circuit board, and the second connection rule is used to establish circuit board-level interconnection between the P computing chips on the same circuit board to obtain a computing power acceleration card. The second connection rule is the connection rule between computing core silicon wafers deployed on different computing chips. In a circuit board, any computing chip is connected to at least one other computing chip. That is, when the value of P is greater than or equal to 2, for any computing chip among the P computing chips arranged on the circuit board, the computing chip is connected to at least one of the (P-1) computing chips.

[0108] Among them, the unified interconnection interface can also be used as a circuit board interconnection interface, which is an interface for connecting computing core silicon wafers located on different packaging substrates. For two connected computing core silicon wafers on different computing chips, their corresponding high-speed serial interfaces (circuit board interconnection interfaces) form circuit board-level interconnections through circuit board wiring.

[0109] The circuit board connection is a connection arranged on the circuit board. The circuit board connection is used to connect the computing power core silicon wafers located on different computing power chips, and the two ends of the circuit board connection are respectively connected to the corresponding high-speed serial interfaces on the two computing power core silicon wafers. That is, the corresponding high-speed serial interfaces of the two computing power core silicon wafers located on different computing power chips that can form a connection relationship are connected through the circuit board connection arranged on the circuit board, thereby realizing the connection between the two computing power core silicon wafers.

[0110] Since the circuit board connection is used to connect the circuit board interconnection interface, the transmission rate corresponding to the circuit board connection is the second transmission rate, so the circuit board interconnection interface corresponds to the second transmission rate. And since the circuit board connection needs to cross different packaging substrates, the transmission rate corresponding to the circuit board connection usually needs to be reduced, and the transmission rate corresponding to the substrate connection arranged on the packaging substrate is greater than or equal to the transmission rate corresponding to the circuit board connection, that is, the first transmission rate is greater than or equal to the second transmission rate.

[0111] That is, the high-speed serial interface provided in the embodiment of the present application supports adjusting the transmission rate, and the high-speed serial interface supports two working modes, one is the package interconnection mode, and the other is the circuit board interconnection mode. When the high-speed serial interface is in the package interconnection mode, it corresponds to the first transmission rate, and when the high-speed serial interface is in the circuit board interconnection mode, it corresponds to the second transmission rate. For a high-speed serial interface that connects two computing power core silicon wafers located on the same computing power chip through substrate wiring, it corresponds to the first transmission rate; for a high-speed serial interface that connects two computing power core silicon wafers located on different computing power chips through circuit board wiring, it corresponds to the second transmission rate.

[0112] For detailed descriptions of high-speed serial interfaces, transmission rates, connections between computing power core silicon chips on the same package substrate, and connections between different computing power chips, please refer to the relevant descriptions in the computing power acceleration card embodiment, which will not be further described here. As for the design method embodiment, since it is similar to the computing power acceleration card embodiment, the relevant parts can be referred to the partial description of the computing power acceleration card embodiment.

[0113] The computing power acceleration card design method provided in the embodiment of the present application uses the core particle technology to interconnect N computing power core particle silicon wafers and then package them to construct a computing power chip, arranges P computing power chips on a circuit board and interconnects the computing power core particle silicon wafers located on different computing power chips based on the chip interconnection technology, so that the computing power core particle silicon wafers can be interconnected at the packaging level and the circuit board level, so as to realize the construction of a high-specification computing power acceleration card based on the interconnection between the computing power core particle silicon wafers; and by packaging at least one computing power core particle silicon wafer to construct a computing power chip, the computing power capacity of a single computing power chip can be guaranteed, and by limiting the number of computing power core particle silicon wafers allowed to be accommodated by a single computing power chip, the packaging cost of a single computing power chip can be reduced, the packaging yield can be improved, and the chip cost can be reduced, thereby achieving a reasonable balance between computing power capacity requirements and cost requirements.

[0114] By providing a unified interconnection interface for interconnecting computing core silicon wafers, there is no need to design two sets of interfaces for package-level interconnection and circuit board-level interconnection respectively, thus reducing interconnection complexity and controlling costs.

[0115] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A computing power acceleration card, characterized in that: include: A circuit board, and P computing chips arranged on the circuit board; The computing power chip includes a packaging substrate and N computing power core silicon wafers arranged on the packaging substrate, where N is an integer greater than or equal to 1 and less than or equal to the threshold value of the number of computing power core silicon wafers allowed to be accommodated by a single computing power chip; The computing power core silicon wafer includes a computing power core unit and M high-speed serial interfaces, the M high-speed serial interfaces are respectively connected to the computing power core units, and P and M are both integers greater than or equal to 1; Among them, the computing power core silicon wafers located on the same computing power chip form package-level interconnection through corresponding high-speed serial interfaces, and the computing power core silicon wafers located on different computing power chips form circuit board-level interconnection through corresponding high-speed serial interfaces; the computing power core units corresponding to the P computing power chips constitute a core computing module; In the computing power chip, a first computing power core silicon wafer is connected to at least one second computing power core silicon wafer; The first computing power core silicon wafer is any one of the N computing power core silicon wafers included in the computing power chip, and the remaining N-1 computing power core silicon wafers are all the second computing power core silicon wafers; A substrate connection is arranged between two connected computing power core silicon wafers on the same computing power chip, and the corresponding high-speed serial interfaces of the two computing power core silicon wafers are connected through the substrate connection; a circuit board connection is arranged between two connected computing power core silicon wafers on different computing power chips, and the corresponding high-speed serial interfaces of the two computing power core silicon wafers are connected through the circuit board connection; The high-speed serial interface supports adjusting the transmission rate; when the high-speed serial interface connects two computing core silicon wafers located on the same computing power chip through the substrate wiring, the high-speed serial interface corresponds to a first transmission rate; when the high-speed serial interface connects two computing core silicon wafers located on different computing power chips through the circuit board wiring, the high-speed serial interface corresponds to a second transmission rate; The first transmission rate is the transmission rate corresponding to the substrate connection, the second transmission rate is the transmission rate corresponding to the circuit board connection, and the first transmission rate is greater than or equal to the second transmission rate.

2. The computing power acceleration card according to claim 1, characterized in that: The M high-speed serial interfaces of the computing power core silicon wafer correspond to the same interface structure, and the interface structures of the high-speed serial interfaces corresponding to different computing power core silicon wafers are the same; and the high-speed serial interface is a unified interconnection interface that can be used as a packaging interconnection interface and a circuit board interconnection interface.

3. The computing power acceleration card according to any one of claims 1 to 2, characterized in that: In the case where at least two computing chips are arranged on the circuit board, a first computing chip is connected to at least one second computing chip, and at least one circuit board connection line is arranged between the connected first computing chip and the second computing chip; The first computing power chip is any one of the at least two computing power chips, and the other computing power chip different from the first computing power chip is the second computing power chip.

4. A computing power server, characterized in that: comprising at least one computing power acceleration card according to any one of claims 1 to 3, wherein the computing power acceleration card is arranged in a card slot of the computing power server; In the case where the computing power server includes multiple computing power acceleration cards, a board-level interconnection is formed between the multiple computing power acceleration cards, and at least one board-level interconnection structure is present between two connected computing power acceleration cards.

5. A method for designing a computing power acceleration card, characterized in that: include: Providing a computing power core silicon wafer, wherein the computing power core silicon wafer includes a computing power core unit and M high-speed serial interfaces connected to the computing power core unit; Based on the design rule that each computing chip includes N computing core silicon wafers, the computing core silicon wafers are packaged to obtain P computing chips, where N is an integer greater than or equal to 1 and less than or equal to the threshold number of computing core silicon wafers allowed to be accommodated by a single computing chip, and P and M are both integers greater than or equal to 1; Arrange the P computing chips on a circuit board, establish circuit board-level interconnection between the computing chips, and obtain a computing acceleration card including the P computing chips; Among them, the computing power core silicon wafers located on the same computing power chip form package-level interconnection through corresponding high-speed serial interfaces, and the computing power core silicon wafers located on different computing power chips form circuit board-level interconnection through corresponding high-speed serial interfaces; the computing power core units corresponding to the P computing power chips constitute a core computing module; when designing multiple computing power acceleration cards, board-level interconnection between multiple computing power acceleration cards is established; substrate wiring is arranged between two connected computing power core silicon wafers located on the same computing power chip, and the corresponding high-speed serial interfaces of the two computing power core silicon wafers are connected through the substrate wiring; A circuit board connection is arranged between two connected computing power core silicon wafers on different computing power chips, and the corresponding high-speed serial interfaces of the two computing power core silicon wafers are connected through the circuit board connection; the high-speed serial interface supports adjusting the transmission rate; when the high-speed serial interface connects the two computing power core silicon wafers located on the same computing power chip through the substrate connection, the high-speed serial interface corresponds to the first transmission rate; when the high-speed serial interface connects the two computing power core silicon wafers located on different computing power chips through the circuit board connection, the high-speed serial interface corresponds to the second transmission rate; Wherein, the first transmission rate is the transmission rate corresponding to the substrate connection, the second transmission rate is the transmission rate corresponding to the circuit board connection, and the first transmission rate is greater than or equal to the second transmission rate; For any one of the N computing power core silicon wafers included in the computing power chip, the computing power core silicon wafer is connected to at least one of the N-1 computing power core silicon wafers.

6. The computing power acceleration card design method according to claim 5, characterized in that: The method of packaging the computing power core silicon wafers based on the design rule that each computing power chip includes N computing power core silicon wafers to obtain P computing power chips includes: Providing P packaging substrates; Based on the layout strategy of arranging N computing power core silicon wafers on each packaging substrate, a first connection rule is used to establish packaging-level interconnection between the N computing power core silicon wafers on the same packaging substrate, and the computing power core silicon wafers are packaged to obtain the P computing power chips; Among them, the first connection rule is the connection rule between the computing core silicon wafers deployed on the same computing power chip, and the corresponding high-speed serial interfaces of the two connected computing core silicon wafers on the same computing power chip form a package-level interconnection through a substrate connection, and the first transmission rate corresponding to the high-speed serial interface is the transmission rate corresponding to the substrate connection.

7. The computing power acceleration card design method according to claim 5, characterized in that: The P computing chips are arranged on a circuit board, and circuit board-level interconnections are established between the computing chips to obtain a computing acceleration card including the P computing chips, including: Providing a circuit board; Arrange P computing chips on the circuit board, establish circuit board-level interconnection between the P computing chips based on a second connection rule, and obtain the computing acceleration card; Among them, the second connection rule is the connection rule between the computing power core silicon wafers deployed on different computing power chips, and the corresponding high-speed serial interfaces of two connected computing power core silicon wafers located on different computing power chips form circuit board level interconnection through circuit board connections, and the second transmission rate corresponding to the high-speed serial interface is the transmission rate corresponding to the circuit board connection.

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