A write verification method, circuit and memory for dynamically adjusting read reference based on memristor

Abstract

The present invention provides a write verification method, circuit and memory for dynamically adjusting a read reference based on a memristor, comprising: a read circuit, used to perform a verification operation on a memristor unit that has undergone a write operation, so as to verify whether the write operation is successful; a read-write logic control unit, used to control the verification operation performed by the read circuit; a read reference comparison output circuit, used to compare a verification signal output by the memristor unit when performing a verification operation with a read reference signal, and output a signal indicating whether the write operation is successful according to a comparison result; and a read reference signal generating circuit, used to generate a read reference signal. In the case where the write operation verification fails, the read-write logic control unit controls the read reference signal generating circuit to adjust the size of the read reference signal, and controls the read reference comparison output circuit to compare the verification signal with the adjusted read reference signal, until the read reference comparison output circuit outputs a signal indicating that the write operation is successful.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a write verification method, circuit and memory for dynamically adjusting a read reference based on a memristor. Background Art

[0002] A memristor is a resistive switch with a memory effect. Its resistance can be stably maintained after power is removed, so it has a natural non-volatile property. Since memristors have the characteristics of small size, high integration, low power consumption, and non-volatility, it is easier to package more memristors on a chip. Memristors may replace transistors and continue Moore's Law, so memristors will become an ideal new storage material. In addition to the non-volatile property, the resistive random access memory (RRAM) with memristors as the core device also has the characteristics of simple structure, compatibility with complementary metal oxide semiconductor technology (CMOS technology), fast resistive switching speed, small size, and high integration density, making it suitable for realizing in-memory computing and having incomparable advantages over other emerging non-volatile memories.

[0003] Memristors can be divided into binary memristors and multi-value memristors according to their resistance distribution. For binary memristors, they can be switched between high-resistance and low-resistance states by applying appropriate voltages, where the low-resistance state is a state where a conductive path is formed and has a low resistance value, while the high-resistance state is a state where a conductive path is disconnected and has a high resistance value. Therefore, data can be stored through high and low resistance. For multi-value memristors, there are multiple resistance states, so multiple values ​​can be stored.

[0004] The most basic operations in the read and write operations of a memristor are Set (write "1"), Reset (write "0"), and read operations. For example, for a binary memristor, by applying a forward bias voltage or current across its two ends, the memristor is placed in a low-resistance state, i.e., the Set (write "1") operation, and by applying a reverse bias voltage or current across its two ends, the memristor is placed in a high-resistance state, i.e., the Reset (write "0") operation. The Read (read) operation determines the state of the memristor by applying a voltage or current of a certain amplitude across the memristor and detecting the amplitude of its output voltage or current, i.e., reading the data stored in the memristor to determine whether it is data "0" (Set) or data "1" (Reset), etc. The threshold amplitude used to distinguish the state of the memristor is usually referred to as a read reference voltage or current (hereinafter collectively referred to as a read reference signal).

[0005] When programming the memristor array, the data of a certain address is generally programmed uniformly. Figure 1Taking the memristor array with a bit width of 8 as an example, that is, there are 8 memristor units as storage units of the address, the process of programming the selected 8 memristor units is generally as follows:

[0006] Set / Reset operation: by applying forward / reverse bias voltage or current, the memristor unit at the address is placed in a low resistance state or a high resistance state, which is equivalent to writing data "1" or data "0";

[0007] Verify operation: By applying a verification voltage or current, it is determined whether the above operation is written successfully. This verification operation is similar to the read operation. By detecting the voltage or current output by the memristor unit and comparing it with the read reference signal, the current resistance state of the unit is determined, that is, whether the data stored therein is "0" or "1", thereby verifying whether the previous write is successful.

[0008] If the write fails, you need to perform the Set / Reset + Verify process again until the write succeeds. Due to the write time requirement, it is sometimes impossible to perform the Set / Reset + Verify process many times, or even only one Set / Reset + Verify process, which is very likely to cause write failure.

[0009] One of the reasons for write failure is the reliability of the memristor. Since the resistance parameter distribution of each memristor unit is discrete and each unit has inconsistency in durability and retention performance, this instability causes the reliability of the memristor array composed of multiple memristor units to be limited by the unit with the worst performance in the array. The tailing effect of the array seriously restricts the performance and size of the array, and is also the main source of the bit error rate of the memristor array.

[0010] Figure 1 The figure shows the resistance distribution of the memristor cells in the memristor array. Take the memristor array with a bit width of 8 as an example. Usually, the read reference signals of all memristor cells in the memristor array have a constant or the same amplitude. Figure 1 Ref1 in the figure represents a read reference signal for determining a high resistance state, that is, when the voltage or current output by the memristor unit is higher than Ref1, it indicates that the unit is in a high resistance state. Ref2 represents a read reference signal for determining a low resistance state, that is, when the voltage or current output by the memristor unit is lower than Ref1, it indicates that the unit is in a low resistance state. Figure 1The distribution of memristor resistance values ​​shown in the figure shows that in some read / write processes, the read reference signal cannot correctly distinguish data "0" from data "1". For example, for the read reference signal Ref1, the 6th memristor unit at this address (the 6th from the left in the figure) may be misjudged as low resistance in a certain read / write process. Similarly, for the read reference signal Ref2, the 3rd memristor unit at this address (the 3rd from the left in the figure) may be misjudged as high resistance in a certain read / write process.

[0011] In addition, in the process of frequently reading and writing data to the memristor, there may be a unit that is over-operated once, resulting in insufficient writing of the opposite data the next time, and thus the write failure will be judged based on the current read reference signal, which will affect the uniformity of the characteristics of the memristor unit and is not conducive to the promotion and use of memristors.

[0012] Therefore, how to make the memristor write successfully in a limited number of Set / Reset+verify processes is a problem that memristors and their storage devices currently face. Summary of the invention

[0013] In order to solve the above problems, the present invention proposes a write verification method for dynamically adjusting a read reference signal based on a memristor. By dynamically adjusting the read reference signal during the verification operation, discretely distributed resistive parameters are gathered within a certain adjustable range. At the same time, the dynamically adjusted read reference signal is mapped and bit-stored to solve the problem of write failure and improve the reliability of the resistive memory.

[0014] According to some exemplary embodiments of the present disclosure, there is provided a write verification circuit for dynamically adjusting a read reference based on a memristor, which performs a write verification operation on a memristor array composed of a plurality of memristor units, and is characterized in that it comprises: a read circuit for performing a verification operation on the memristor unit that has undergone a write operation to verify whether the write operation is successful; a read-write logic control unit for controlling the verification operation performed by the read circuit; a read reference comparison output circuit for comparing a verification signal output by the memristor unit when performing the verification operation with a read reference signal, and outputting a signal indicating whether the write operation is successful based on a comparison result; and a read reference signal generating circuit for generating the read reference signal, wherein, in the event that the write operation verification fails, the read-write logic control unit controls the read reference signal generating circuit to adjust the size of the read reference signal, and controls the read reference comparison output circuit to compare the verification signal with the adjusted read reference signal until the read reference comparison output circuit outputs a signal indicating that the write operation is successful.

[0015] In some embodiments, when the write operation verification is successful, the read-write logic control unit stores the read reference signal that makes the write operation verification successful.

[0016] In some embodiments, the read reference signal is stored in a check bit storage area inside the memristor array in the form of a check bit storage value corresponding to the memristor unit.

[0017] In some embodiments, the read reference signal is stored in a check bit storage area of ​​an external storage medium in the form of a check bit storage value corresponding to the memristor unit.

[0018] In some embodiments, the read reference signal is mapped to the check bit storage value to generate a check bit storage mapping relationship table.

[0019] In some embodiments, the read / write logic control unit adjusts the size of the read reference signal by reading the read reference signal corresponding to different check bit storage values ​​from the check bit storage mapping relationship table.

[0020] In some embodiments, when the read circuit performs a read operation on the memristor unit, it reads the check bit storage value corresponding to the memristor unit from the check bit storage area, and refers to the check bit storage mapping relationship table, and the reference signal generating circuit generates the read reference signal corresponding to the check bit storage value, and the read-write logic control unit uses the read reference signal to read the data stored in the memristor unit.

[0021] According to some exemplary embodiments of the present disclosure, there is also provided a write verification method for dynamically adjusting a read reference based on a memristor, and performing a write verification operation on a memristor array composed of a plurality of memristor units, including: performing a verification operation on the memristor unit that has undergone a write operation to verify whether the write operation is successful; comparing a verification signal output by the memristor unit when performing the verification operation with a read reference signal, and outputting a signal indicating whether the write operation is successful based on the comparison result; in the event that the write operation verification fails, adjusting the size of the read reference signal, and comparing the verification signal with the adjusted read reference signal until a signal indicating that the write operation is successful is output.

[0022] According to some exemplary embodiments of the present disclosure, a memory is further provided, comprising a memristor array composed of a plurality of memristor units, and having the above-mentioned write verification circuit for dynamically adjusting a read reference based on a memristor.

[0023] The present disclosure is characterized in that a write verification operation is performed by dynamically adjusting a read reference signal. After a write operation (set / reset operation) is performed, multiple verifications are performed, and the read reference signal is adjusted (increased or decreased) during each verification until the write is successful. Therefore, compared with the previous process of rewriting and re-verifying after verification failure, the write verification can be efficiently guaranteed to be successful within a limited time, and the verification time can be shortened. In addition, by dynamically adjusting the read reference signal, the discretely distributed resistive parameters of each memristor unit can be gathered within a certain adjustable range, which can solve the problem of discrete distribution of resistive parameters to a certain extent and improve the reliability of resistive memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0025] Figure 1 shows a resistance distribution diagram of a memristor unit in a memristor array;

[0026] Figure 2 An example block diagram of a memory 100 having a write verification circuit 110 according to this embodiment is shown;

[0027] Figure 3 Shows Figure 2 A schematic diagram of a memristor cell MC1 included in the memristor array 101 shown;

[0028] Figure 4 The structure block diagram of the write verification circuit 110 for dynamically adjusting the read reference based on a memristor of the present embodiment is shown;

[0029] Figure 5 A flowchart of a write operation using the write verification circuit 110 of this embodiment is shown;

[0030] Figure 6 FIG. 1 is a flow chart showing a read operation performed by the write verification circuit 110 of this embodiment. DETAILED DESCRIPTION

[0031] The specific implementation methods of the present disclosure will be described below. It should be noted that in the specific description of these implementation methods, in order to provide a concise description, it is impossible for this specification to provide a detailed description of all the features of the actual implementation methods. It should be understood that in the actual implementation of any implementation method, just as in the process of any engineering project or design project, in order to achieve the specific goals of the developer and to meet system-related or business-related restrictions, various specific decisions are often made, and this will also change from one implementation method to another. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for ordinary technicians in the field related to the content disclosed by the present disclosure, some changes in design, manufacturing or production based on the technical content disclosed in the present disclosure are just conventional technical means, and should not be understood as insufficient content of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the claims and the specification shall have the usual meanings understood by persons with ordinary skills in the technical field to which the present disclosure belongs. The words "first", "second" and similar words used in the patent application specification and the claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one" or "one" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalent elements, and do not exclude other elements or objects. Words such as "connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0033] In the present disclosure, unless otherwise specified, all embodiments and preferred embodiments mentioned herein can be combined with each other to form a new technical solution. In the present disclosure, unless otherwise specified, all technical features and preferred features mentioned herein can be combined with each other to form a new technical solution.

[0034] In the description of the embodiments of the present disclosure, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0035] A write verification circuit and method for dynamically adjusting a read reference based on a memristor according to an embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0036] Figure 2 1 is a block diagram of an example of a memory 100 having a write verification circuit 110 according to the present embodiment. Figure 2 , the memory 100 includes a memristor array 101, an address decoder 102, a data input / output (I / O) circuit 103 and a control logic 104. According to an embodiment of the inventive concept, the control logic 104 may include a write verification circuit 110 for dynamically adjusting a read reference based on a memristor provided by the present invention.

[0037] The memristor array 101 may have a plurality of memristor cells MC1. In the present embodiment, the memristor array 101 with a bit width of 8 is taken as an example, that is, there are 8 memristor cells MC1 corresponding to each row. Of course, the bit width of the memristor array 101 is not limited to 8, and may also be 16, 32, or other cases. Each memristor cell MC1 stores one or more data bits. The memory cell MC1 may be connected to a plurality of word lines WL (word line), a plurality of source lines SL (source line) and a plurality of bit lines BL (bit line).

[0038] The address decoder 102 may be connected to the memristor array 101 via word lines WL and source lines SL. The address decoder 102 may operate in response to the control of the control logic 104. The address decoder 102 may decode an input address to select the word lines WL and the source lines SL, and may receive a voltage or current from the control logic 104 to provide it to a selected or unselected word line WL.

[0039] The data input / output circuit 103 may be connected to the memristor array 101 via the bit line BL. The data input / output circuit 103 may operate in response to the control of the control logic 104. The data input / output circuit 103 may select the bit line BL in response to a selection signal (not shown) from the address decoder 102, and may receive a voltage or current from the control logic 104 which is provided to the selected bit line BL.

[0040] The control logic 104 may be configured to control the overall operation of the memory 100. The control logic 104 may be provided with an external power supply and / or a control signal, may use the external power supply to generate a voltage or current required for internal operation, and may control read, write, verify, and / or erase operations in response to the control signal. According to an embodiment of the inventive concept, the control logic 104 may include a write verify circuit 110 that dynamically adjusts a read reference based on a memristor.

[0041] Figure 3 yes Figure 2Schematic diagram of a memristor cell MC1 included in a memristor array 101 shown. The memristor cell MC1 includes a memristor element 10 and a transistor 20. The memristor element 10 is a basic element for forming a resistive memory such as RRAM, and is composed of an upper electrode 11 and a lower electrode 13, and a functional layer 12 with memristive characteristics arranged between the two electrodes 11 and 13. For example, in the case of a binary memristor, the memristor element 10 has two resistance states, a high resistance state and a low resistance state, and its resistance state changes according to the polarity or magnitude of the voltage or current applied to both ends. In the following description, a forward bias voltage is applied to both ends of the memristor element 10, that is, the current direction in the memristor element 10 is from the upper electrode 11 to the lower electrode 13 (i.e., in the downward direction), the memristor element 10 presents a low resistance state, and the memristor cell MC1 is defined as being in a logic "1" state, which is equivalent to Set (writing "1"). On the contrary, when a reverse bias voltage is applied to both ends of the memristor element 10, that is, the direction of the current in the memristor element 10 flows from the lower electrode 13 to the upper electrode 11 (i.e., upward direction), the memristor element 10 presents a high resistance state, and the memristor unit MC1 is defined as being in a logical "0" state, which is equivalent to Reset (writing "0"). It should be understood that in other embodiments, the above direction can be defined in reverse, that is, the directions of the voltages or currents corresponding to Set and Reset can be opposite to each other.

[0042] The transistor 20 is generally a MOS transistor. The gate of the transistor 20 is connected to the word line WL, the drain is connected to the lower electrode 13 of the memristor element 10, and the source is connected to the source line SL. The upper electrode 11 of the memristor element 10 is connected to the bit line BL. Figure 2 The address decoder 102 and the control logic 104 in the embodiment select the word line WL, the source line SL and the bit line BT, and then select the corresponding memristor unit 1.

[0043] Next, the Set operation (write “1” operation), the Reset operation (write “0” operation), the Read operation, and the Verify operation performed by the memristor unit 1 are described.

[0044] Set operation (write "1" operation): V_Set voltage is applied to the upper electrode 11 of the selected memristor cell MC1 through the bit line BL, Vw_Set voltage is applied through the word line WL, and the source line is grounded, thereby applying a forward bias voltage ΔV_Set across the two ends of the memristor cell MC1.

[0045] Reset operation (write "0" operation): the upper electrode 11 of the selected memristor unit MC1 is grounded, that is, a voltage of, for example, 0V is applied through the bit line BL, a voltage of Vw_Reset is applied to the word line WL, and a voltage of V_Reset is applied to the source line, thereby applying a reverse bias voltage ΔV_Reset to both ends of the memristor unit MC1.

[0046] Read operation: V_Read voltage is applied to the upper electrode 11 of the selected memristor cell MC1, Vw_Read voltage is applied to the word line WL, and the source line is grounded, so that a forward bias voltage ΔV_Read is applied to both ends of the memristor cell MC1. Whether "0" or "1" is stored in the memristor cell MC1 is output by detecting the current of the memristor cell MC1, i.e., the read operation current I_Read, and comparing it with the preset read reference current I_Ref.

[0047] Verify operation: Verify whether the write operation of Set and Reset is successful. The specific operation is similar to the Read operation. By applying a forward bias voltage ΔV_Verify to both ends of the memristor unit MC1, the current of the memristor unit MC1, i.e., the verification current I_Verify, is detected and compared with a preset read reference signal, such as the current I_Ref, to confirm whether the data written in the memristor unit MC1 is consistent with the previous write operation.

[0048] As mentioned above, due to the inconsistency / non-uniformity of the characteristics of the memristor units in the memristor array, it may not be possible to successfully write the memristor within a limited number of Set / Reset+verify cycles or within a limited time, resulting in reduced reliability of the memristor. The write verification method and circuit based on the dynamic adjustment of the read reference of the memristor in this embodiment can solve this problem.

[0049] Figure 4 4 is a structural block diagram of a write verification circuit 110 for dynamically adjusting a read reference based on a memristor according to the present embodiment.

[0050] The write verification circuit 110 is a circuit for verifying whether the memristor cell MC1 at the selected address in the memristor array 101 is successfully written. Figure 4 In the figure, the structure of a single memristor unit MC1 is used as a representative to illustrate multiple memristor units at the selected address in the memristor array 101. For example, in this embodiment, the selected address corresponds to a memristor array with a bit width of 8, that is, Figure 1 , Figure 2 A row of addresses is formed by a total of 8 memristor units MC1. Of course, the number of memristor units MC1 is not limited to 8, but may also be 16, 32, etc.

[0051] The write verification circuit 110 includes a write circuit 2 , a read circuit 3 , a read / write logic control unit 4 , a read reference comparison output circuit 5 , a read reference signal generating circuit 6 , a check bit storage mapping relationship table 7 and a check bit storage value 8 .

[0052] like Figure 4 As shown, when writing data, the read / write logic control unit 4 controls the write circuit 2 to perform a Set operation (write "1" operation) / Reset operation (write "0" operation) on the memristor unit MC1 at the selected address in the memristor array 101, and performs a Verify operation (verification operation) through the read circuit 3. For example, the read circuit 3 applies a forward bias voltage ΔV_Verify to both ends of the memristor unit MC1, detects the current output by the memristor unit MC1, that is, the verification current I_Verify, and inputs the verification current I_Verify to an input end of the read reference comparison output circuit 5, and compares it with the preset read reference signal Ref1 to confirm whether the data written in the memristor unit MC1 is consistent with the previous write operation. If the comparison result is that the two are consistent, the read reference comparison output circuit 5 outputs a signal indicating that the verification is successful, that is, the writing is successful, to the read circuit 3. If the comparison result is that the two are inconsistent, the read reference comparison output circuit 5 outputs a signal indicating that the verification fails, that is, the writing fails, to the read circuit 3.

[0053] When the read circuit 3 receives a signal indicating verification failure from the read reference comparison output circuit 5, the read reference signal generating circuit 6 is controlled by the read / write logic control unit 4 to adjust the size of the read reference signal. For example, in this embodiment, the adjusted read reference signal is recorded as Ref2. The read reference signal here can be a read reference current or a read reference voltage, and there is no special limitation. The adjusted read reference signal Ref2 is provided to the other input end of the read reference comparison output circuit 5, and is compared again with the verification current I_Verify output by the memristor unit MC1. The read reference comparison output circuit 5 outputs a signal indicating verification success or failure to the read circuit 3 again. If the verification still fails, the read reference signal generating circuit 6 adjusts the size of the read reference signal again, for example, generating a read reference signal Ref3 that is adjusted again. This cycle is repeated until the determination result of the read reference signal generating circuit 6 is that the current write is successful.

[0054] When the read reference comparison output circuit 5 outputs a signal indicating successful verification, i.e., successful writing, the corresponding read reference signal is bit-mapped for storage, for example, in the form of a check bit storage mapping relationship table 7, and the mapped check bit storage value is stored in the check bit storage area of ​​the storage medium inside or outside the memristor array 101.

[0055] Table 1 is an example of a mapping relationship table between a read reference signal and a check bit storage value in this embodiment.

[0056]

Table 1

[0057] Bit storage value Read reference signal 00 Ref1 01 Ref2 10 Ref3 11 Ref4 ... ...

[0058] Table 1 shows the four read reference signals Ref1, Ref2, Ref3, and Ref4. Since the read reference signal can be a current signal or a voltage signal, Table 1 does not distinguish between voltage and current, but is uniformly recorded as the read reference signal Ref.

[0059] As shown in Table 1, the four read reference signals occupy a 2-bit check bit storage space. For example, the bit storage value 00 corresponds to the read reference signal Ref1, the bit storage value 01 corresponds to the read reference signal Ref2, the bit storage value 10 corresponds to the read reference signal Ref2, and the bit storage value 11 corresponds to the read reference signal Ref4. Of course, the present invention has no particular limitation on the number of read reference signals, and can be Figure 1 The 2 shown may also be 3 or 4 or more.

[0060] When performing a data reading operation, the read circuit 3 reads the check bit storage value 8 from the corresponding address of the check bit storage area through the read-write logic control unit 4, obtains the corresponding read reference signal value Ref through the check bit storage mapping relationship table 7, and the read reference signal generating circuit 6 generates a corresponding signal quantity, such as current I_Ref, according to the read reference signal value Ref, and inputs it to the input end of the read reference comparison output circuit 5, and compares it with the read operation detection current (not shown) input to the other end of the read reference comparison output circuit 6 to generate corresponding 0 / 1 data, and then the read-write logic control unit 4 controls the read circuit 3 to read the data, thereby completing the data reading operation.

[0061] Next, the specific process of performing data reading and writing operations using the write verification circuit 110 of this embodiment is described. Figure 5 1 is a flow chart of a write operation performed using the write verification circuit 110 of this embodiment. Figure 6 1 is a flow chart of a read operation performed by the write verification circuit 110 of this embodiment.

[0062] When writing data, Figure 5 As shown, in step S11, the read / write logic control unit 4 selects a certain address in the memristor array 101, and performs a Set operation or a Reset operation on the memristor cell MC1 at the address, that is, writes "1" or writes "0".

[0063] In step S12, the read / write logic control unit 4 performs a verification operation on the memristor unit MC1 at the address, and compares the verification current output by the memristor unit MC1 with a preset read reference signal, thereby verifying whether the data written into the corresponding memristor unit MC1 is successful.

[0064] In step S13, the read reference comparison output circuit 5 outputs a signal indicating whether verification is successful.

[0065] If the result in step S13 is that the verification is successful ("yes"), the read reference signal Ref of the address is mapped to a verification bit storage value (step S14), and the verification bit storage value is stored in the verification storage area of ​​the internal or external storage medium of the memristor array 101 (step S15).

[0066] If the result in step S13 is that the verification fails ("No"), the process proceeds to step S16, where the read reference signal generating circuit 6 is controlled by the read / write logic control unit 4 to adjust the magnitude of the read reference signal. The process then returns to step S12, where the verification operation is performed again using the adjusted read reference signal until the verification succeeds, and then the process proceeds to steps S14 and S15.

[0067] At this point, the process of performing data write operation using the write verification circuit 110 of this embodiment is completed.

[0068] When reading data, Figure 6 As shown, in step S21, the read / write logic control unit 4 selects a certain address in the memristor array 101 and performs a read operation on the memristor cell MC1 at the address.

[0069] In step S22, the read / write logic control unit 4 reads the check bit storage value corresponding to the address, such as the bit storage value 00 in Table 1.

[0070] Then in step S23, the read reference signal value corresponding to the check bit storage value 00 is searched in the check storage mapping relationship table in Table 1, for example, Ref1 in this embodiment.

[0071] In step S24 , the read reference signal generating circuit 6 generates a corresponding reference voltage or reference current signal according to the read reference signal value Ref1 .

[0072] Next, in step S25 , the read reference comparison output circuit 5 compares the voltage or current output by the memristor cell MC1 in the read operation with the reference voltage or current generated in step S24 , thereby outputting a signal representing the data stored in the address.

[0073] At this point, the process of performing a data read operation using the write verification circuit 110 of this embodiment is completed.

[0074] According to the memristor write verification method for dynamically adjusting the read reference signal of the present embodiment, after a write operation (set / reset operation) is performed, multiple verifications are performed, and the read reference signal is adjusted (increased or decreased) during each verification until the write is successful. Therefore, compared with the previous process of rewriting and re-verifying after verification failure, the write verification can be efficiently guaranteed to be successful within a limited time, and the verification time can be shortened. In addition, by dynamically adjusting the read reference signal, the discretely distributed resistive parameters of each memristor unit can be gathered within a certain adjustable range, which can solve the problem of discrete distribution of resistive parameters to a certain extent and improve the reliability of resistive memory.

[0075] In some embodiments, if multiple checks fail (reaching a certain number of times) after a write operation (set / reset operation), the write operation (set / reset operation) can be performed again, and then the read reference voltage can be dynamically adjusted to perform the check until the write is successful. As long as the check can be guaranteed to be successful within the allowed time, the number of checks and the need for re-writing operations can be set according to actual needs.

[0076] In some embodiments, a threshold value for the number of verification failures can be set. If the number of verification failures for a write operation reaches the threshold, it indicates that one or some of the memristor units at the selected address may be faulty and normal read and write operations cannot be performed. Therefore, the write verification operation is exited and operations such as fault detection can be performed.

[0077] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present disclosure, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present disclosure. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present disclosure, the various embodiments are not meant to be restrictive, but exemplary embodiments. In reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. A write verification circuit for dynamically adjusting a read reference based on a memristor, performing a write verification operation on a memristor array composed of a plurality of memristor units, characterized in that: include: A read circuit, used for performing a verification operation on the memristor unit that has been written to, so as to verify whether the writing operation is successful; A read / write logic control unit, used to control the verification operation performed by the read circuit; a read reference comparison output circuit, used for comparing the verification signal output by the memristor unit when performing the verification operation with the read reference signal, and outputting a signal indicating whether the write operation is successful according to the comparison result; as well as a read reference signal generating circuit, used to generate the read reference signal, In the case where the write operation verification fails, the read-write logic control unit controls the read reference signal generating circuit to adjust the magnitude of the read reference signal, and controls the read reference comparison output circuit to compare the verification signal with the adjusted read reference signal until the read reference comparison output circuit outputs a signal indicating that the write operation is successful. The read reference signal when the write operation is successfully verified is subjected to check bit storage mapping, and the mapped check bit storage value is written into a check bit storage area corresponding to the memristor unit.

2. The write verification circuit according to claim 1, characterized in that: The check bit storage area is arranged inside the memristor array.

3. The write verification circuit according to claim 1, wherein: The check bit storage area is set in an external storage medium.

4. The write verification circuit according to claim 1 or 2, characterized in that: The read reference signal is mapped to the check bit storage value to generate a check bit storage mapping relationship table.

5. The write verification circuit according to claim 4, characterized in that: The read / write logic control unit adjusts the size of the read reference signal by reading the read reference signal corresponding to different check bit storage values ​​from the check bit storage mapping relationship table.

6. The write verification circuit according to claim 4, characterized in that: When the read circuit performs a read operation on the memristor unit, the check bit storage value corresponding to the memristor unit is read from the check bit storage area, and with reference to the check bit storage mapping relationship table, the reference signal generating circuit generates the read reference signal corresponding to the check bit storage value, and the read-write logic control unit uses the read reference signal to read the data stored in the memristor unit.

7. A write verification method based on a memristor for dynamically adjusting a read reference, performing a write verification operation on a memristor array composed of a plurality of memristor units, characterized in that: include: Performing a verification operation on the memristor unit that has been written to verify whether the writing operation is successful; comparing a verification signal output by the memristor unit when performing the verification operation with a read reference signal, and outputting a signal indicating whether the write operation is successful according to the comparison result; In the case where the write operation verification fails, adjusting the magnitude of the read reference signal, and comparing the verification signal with the adjusted read reference signal until a signal indicating that the write operation is successful is output; The read reference signal when the write operation is successfully verified is subjected to check bit storage mapping, and the mapped check bit storage value is written into a check bit storage area corresponding to the memristor unit.

8. The write verification method according to claim 7, characterized in that: The check bit storage area is arranged inside the memristor array.

9. The write verification method according to claim 7, characterized in that: The check bit storage area is set in an external storage medium.

10. The write verification method according to claim 7, characterized in that: The read reference signal is mapped to the check bit storage value to generate a check bit storage mapping relationship table.

11. The write verification method according to claim 10, characterized in that: The size of the read reference signal is adjusted by reading the read reference signal corresponding to different check bit storage values ​​from the check bit storage mapping relationship table.

12. The write verification method according to claim 10, characterized in that: When performing a read operation on the memristor unit, the check bit storage value corresponding to the memristor unit is read from the check bit storage area, and the read reference signal corresponding to the check bit storage value is generated with reference to the check bit storage mapping relationship table, and the data stored in the memristor unit is read using the read reference signal.

13. A memory comprising a memristor array composed of a plurality of memristor units, characterized in that: A write verification circuit for dynamically adjusting a read reference based on a memristor as claimed in any one of claims 1 to 6.

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