A silicon-based gallium nitride epitaxial wafer and a method for preparing the same

Abstract

The present application provides a silicon-based gallium nitride epitaxial wafer and a preparation method thereof, the preparation method comprising the following steps: providing a base, placed in an epitaxial reaction chamber, the base comprising a groove, the bottom wall of the groove protruding along a first direction; providing a substrate, placing the substrate in the groove of the base; introducing a carrier gas, an aluminum source and a nitrogen source, preparing a nucleation layer on the surface of the substrate; and completing epitaxial growth on the surface of the nucleation layer. By using a groove with a central micro-convex structure as a base for silicon-based gallium nitride epitaxial growth, temperature compensation can be performed on the processed device during the epitaxial growth process, effectively improving the crystal quality, thickness uniformity and component uniformity of each layer of the silicon-based gallium nitride epitaxial wafer, while reducing the temperature difference between the inner and outer circles of the base groove, thereby improving the yield and utilization rate of large-size silicon-based gallium nitride epitaxial wafers.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor manufacturing technology, and specifically relates to a silicon-based gallium nitride epitaxial wafer and a preparation method thereof. Background Art

[0002] As one of the representatives of the third generation of semiconductor materials, gallium nitride (GaN) has unique material properties such as wide bandgap, high temperature resistance, and high thermal conductivity, and has excellent performance in the field of electronic power devices. In particular, the birth of the two-dimensional electron gas (2DEG) at the AlGaN / GaN heterojunction interface has further enhanced the prospects of gallium nitride in the field of power devices.

[0003] At present, the commonly used substrates for GaN epitaxy are mainly sapphire (Sapphire or Al2O3) and single crystal silicon (Si). Since silicon substrates have the characteristics of high thermal conductivity, high electrical conductivity, easy grinding and processing, large wafer size, and low cost, silicon-based GaN has become one of the mainstream growth methods for GaN-based high electron mobility transistors (HEMT). However, the mismatch in lattice constants and thermal expansion coefficients between GaN and Si substrates will cause poor quality and warping problems in the GaN epitaxial layer. Taking 6-inch silicon-based gallium nitride epitaxy as an example, affected by factors such as vertical temperature gradient, thermal expansion coefficient mismatch and lattice constant mismatch, the wafer will change from flat to concave, then to convex, and finally cool down and become flat again during the epitaxial growth process. Generally, when growing aluminum nitride, the wafer is in the most concave state, and the warp can reach 90-130μm; when growing AlGaN / GaN heterojunction, the wafer is often in the most convex state, and the warp can reach 150-600μm, resulting in a temperature difference of 10-20℃ between the center and edge of the wafer, resulting in poor quality and uniformity of the grown AlGaN / GaN. Summary of the invention

[0004] The present application provides a silicon-based gallium nitride epitaxial wafer and a preparation method thereof, aiming to solve the problems of high warping and unsatisfactory uniformity of finished products caused by uneven heating of the substrate and other problems in the existing gallium nitride epitaxial process.

[0005] On the one hand, an embodiment of the present application provides a method for preparing a silicon-based gallium nitride epitaxial wafer, comprising the following steps:

[0006] Providing a base, placed in the epitaxial reaction chamber, the base comprising a groove, the bottom wall of the groove protruding along a first direction;

[0007] Providing a substrate, and placing the substrate in the groove of the base;

[0008] introducing a carrier gas, an aluminum source and a nitrogen source to prepare a nucleation layer on the surface of the substrate;

[0009] Epitaxial growth is completed on the surface of the nucleation layer.

[0010] In some embodiments, the bottom wall is a convex spherical surface, and a chord height of the convex spherical surface is 30-1000 μm.

[0011] In some embodiments, the groove has a side wall, and the side wall is connected to the bottom wall to form an angle α that satisfies: 5°≤α≤30°.

[0012] In some embodiments, the base is made of graphite.

[0013] In some embodiments, the surface of the groove has a silicon carbide coating.

[0014] In some embodiments, the flow rate of the nitrogen source is 1500-12000 sccm.

[0015] Based on the above embodiment, the step of introducing a carrier gas, an aluminum source and a nitrogen source to prepare a nucleation layer on the surface of the silicon-based substrate satisfies at least one of the following characteristics:

[0016] a) the flow rate of the carrier gas is 70 to 161.5 slm, the flow rate of the aluminum source is 200 to 400 sccm, and the time for preparing the nucleation layer is 20.4 to 72 min;

[0017] b) The flow rate of the carrier gas is 70 to 161.5 slm, the flow rate of the aluminum source is 204 to 480 sccm, and the time for preparing the nucleation layer is 20 to 60 minutes.

[0018] In some embodiments, the epitaxial reaction chamber includes at least two groups of gas delivery pipes; the gas delivery pipes include a first delivery pipe and a second delivery pipe, the first delivery pipe is arranged at the top of the epitaxial reaction chamber, and the second delivery pipe is arranged at the bottom of the epitaxial reaction chamber.

[0019] Based on the above embodiment, the step of introducing a carrier gas, an aluminum source and a nitrogen source to prepare a nucleation layer on the surface of the substrate satisfies at least one of the following characteristics:

[0020] c) the total flow rate of the carrier gas is 100-170 slm, the total flow rate of the aluminum source is 200-400 sccm; the ammonia gas in the first delivery pipe has a first flow rate Q1, and the carrier gas has a second flow rate Q2; the ammonia gas in the second delivery pipe has a third flow rate Q3, and the carrier gas has a fourth flow rate Q4;

[0021] Satisfy: Q1:Q3=2.1~26:1, and Q2:Q4=1:1.1~2;

[0022] d) the total flow rate of the carrier gas is 100-170 slm, the total flow rate of the aluminum source is 200-400 sccm, the ammonia gas in the first delivery pipe has a fifth flow rate Q5, and the carrier gas has a sixth flow rate Q6; the ammonia gas in the second delivery pipe has a seventh flow rate Q7, and the carrier gas has an eighth flow rate Q8;

[0023] Satisfies: Q5:Q7=2~20:1, and Q6:Q8=1:1.1~2.

[0024] In some embodiments, the carrier gas includes hydrogen.

[0025] In some embodiments, the aluminum source includes trimethylaluminum.

[0026] In some embodiments, the nitrogen source includes ammonia gas.

[0027] In some embodiments, the substrate is single crystal silicon.

[0028] In some embodiments, the step of completing epitaxial preparation on the surface of the nucleation layer further comprises:

[0029] preparing a buffer layer on the nucleation layer;

[0030] preparing a channel layer on the buffer layer;

[0031] preparing a barrier layer on the channel layer;

[0032] A surface layer is prepared on the barrier layer.

[0033] In some embodiments, before the step of preparing a barrier layer on the channel layer, the method further includes:

[0034] An insertion layer is formed on the channel layer.

[0035] On the other hand, an embodiment of the present application provides a silicon-based gallium nitride epitaxial wafer, which is prepared using the method for preparing an epitaxial wafer in any of the above embodiments.

[0036] In some embodiments, the silicon-based gallium nitride epitaxial wafer comprises:

[0037] substrate layer;

[0038] a nucleation layer, the nucleation layer being located on one side of the substrate layer;

[0039] a buffer layer, the buffer layer being located on a side of the nucleation layer away from the substrate layer;

[0040] A channel layer, the channel layer being located on a side of the buffer layer away from the nucleation layer;

[0041] A barrier layer, wherein the barrier layer is located on a side of the channel layer away from the buffer layer;

[0042] A surface layer is located on a side of the barrier layer away from the channel layer.

[0043] In some embodiments, the thickness of the nucleation layer is 150-300 nm.

[0044] In some embodiments, the buffer layer includes at least one of aluminum gallium nitride, gallium nitride, and a superlattice structure;

[0045] The superlattice structure includes AlN / GaN, AlN / AlGaN, AlGaN / GaN, Al x Ga 1-x N / A y Ga 1-y At least one of N, where 0≤y <x≤1。

[0046] In some embodiments, the channel layer is undoped gallium nitride, and the thickness of the channel layer is 80-400 nm.

[0047] In some embodiments, the barrier layer is aluminum gallium nitride, and the thickness of the barrier layer is 12-30 nm.

[0048] In some embodiments, the surface layer includes one of nGaN, SiN, or pGaN.

[0049] In some embodiments, an insertion layer is further disposed between the channel layer and the barrier layer.

[0050] In some embodiments, the insertion layer is aluminum nitride, and the thickness of the insertion layer is 1-5 nm.

[0051] The preparation method of silicon-based gallium nitride epitaxial wafer provided in the present application includes the following steps: providing a base, placed in an epitaxial reaction chamber, the base including a groove, the bottom wall of the groove protruding along a first direction; providing a substrate, placing the substrate in the groove of the base; introducing a carrier gas, an aluminum source and a nitrogen source, preparing a nucleation layer on the surface of the substrate; and completing epitaxial growth on the surface of the nucleation layer. By using a groove with a central micro-convex structure as a base for silicon-based gallium nitride epitaxial growth, temperature compensation can be performed on the processed device during the epitaxial growth process, effectively improving the crystal quality, thickness uniformity and component uniformity of each layer of the silicon-based gallium nitride epitaxial wafer, while reducing the temperature difference between the inner and outer circles of the base groove, thereby improving the yield and utilization rate of large-size silicon-based gallium nitride epitaxial wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0053] Figure 1A schematic diagram of a base structure in a method for preparing a silicon-based gallium nitride epitaxial wafer provided in an embodiment of the present application;

[0054] Figure 2 A schematic diagram of the structure of a silicon-based gallium nitride epitaxial wafer provided in an embodiment of the present application;

[0055] Figure 3 A schematic diagram of the structure of a silicon-based gallium nitride epitaxial wafer provided in Example 1 of the present application;

[0056] Figure 4 This is a graph showing the characterization results of the barrier layer aluminum distribution of the silicon-based gallium nitride epitaxial wafer provided in Example 1, Comparative Example 1 and Comparative Example 2 of the present application.

[0057] Figure numerals: 10 - groove, 11 - bottom wall, 12 - side wall, 100 - substrate layer, 200 - nucleation layer, 300 - buffer layer, 301 - first buffer layer, 302 - second buffer layer, 303 - third buffer layer, 304 - fourth buffer layer, 305 - fifth buffer layer, 400 - channel layer, 500 - insertion layer, 600 - barrier layer, 700 - surface layer. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0059] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features.

[0060] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application.

[0061] The first embodiment of the present application provides a method for preparing a silicon-based gallium nitride epitaxial wafer, comprising the following steps:

[0062] A base is provided, and is placed in the epitaxial reaction chamber. The base includes a groove 10, and a bottom wall 11 of the groove 10 is raised along a first direction X;

[0063] Providing a substrate, and placing the substrate in the groove 10 of the base;

[0064] A carrier gas, an aluminum source and a nitrogen source are introduced to prepare a nucleation layer 200 on the surface of the substrate;

[0065] Epitaxial growth is completed on the surface of the nucleation layer 200 .

[0066] By using the groove 10 with a central micro-convex structure as the base for the epitaxial growth of silicon-based gallium nitride, temperature compensation can be performed on the processed device during the epitaxial growth process. On the one hand, it can alleviate the aggravation of warping caused by the different growth rates of the epitaxial layer due to temperature differences; on the other hand, it can improve the temperature uniformity of the inner and outer circles during the growth process of the AlGaN / GaN heterojunction, and obtain a gallium nitride channel layer with high crystal quality and uniformity, and an aluminum gallium nitride barrier layer with high Al% and thickness uniformity.

[0067] See also Figure 1 In some embodiments, the bottom wall 11 of the base is a convex spherical surface, and the chord height of the convex spherical surface is 30 to 1000 μm. It can be understood that the value of the chord height (unit: μm) can be any value of 30, 50, 100, 200, 500, 700, 900, 1000 or a range between any two values. When the chord height of the convex spherical surface meets the above value range, the base groove has a relatively ideal temperature compensation effect during the epitaxial layer growth process.

[0068] In some embodiments, the groove 10 has a side wall 12, the side wall 12 is connected to the bottom wall 11, and has an angle α, which satisfies: 5°≤α≤30°. It can be understood that the value of the angle α (unit: °) can be any value of 5, 10, 15, 20, 25, 30 or a range between any two values. When the value of the angle α satisfies the above range of values, the groove 10 can maximize the warping formed during the epitaxial growth of silicon-based gallium nitride, thereby making the center temperature of the wafer the same as the edge temperature, and making the inner and outer ring temperatures of the subsequent AlGaN / GaN heterojunction growth process more uniform.

[0069] In some embodiments, the base is made of graphite, which has good thermal conductivity and can maintain good mechanical stability in high temperature environments, and can maintain a stable response to changes in the external environment during epitaxial growth.

[0070] In some embodiments, the surface of the groove 10 has a silicon carbide coating. The silicon carbide coating has high thermal stability and corrosion resistance under high temperature conditions, as well as good chemical corrosion resistance. By coating the surface of the groove 10 with the silicon carbide coating, the durability and stability of the graphite base in a high temperature environment can be improved, and the graphite base can be protected from pollution and corrosion. At the same time, the silicon carbide material has better lattice matching with gallium nitride, which can reduce the lattice difference between the epitaxial layer and the base, reduce stress and improve the quality of the epitaxial layer.

[0071] In some embodiments, the flow rate of the nitrogen source is 1500 to 12000 sccm. It is understood that the flow rate value of the nitrogen source (unit: sccm) can be any value of 1500, 2000, 5000, 10000, 12000 or a range between any two values. When the flow rate of the nitrogen source meets the above value range, the epitaxial layer can be grown at a relatively ideal rate, so that the growth of the epitaxial layer is uniform and has fewer defects.

[0072] Based on the above embodiment, further, the step of introducing a carrier gas, an aluminum source and a nitrogen source to prepare a nucleation layer 200 on the surface of a silicon-based substrate satisfies at least one of the following characteristics:

[0073] a) the flow rate of the carrier gas is 70 to 161.5 slm, the flow rate of the aluminum source is 200 to 400 sccm, and the time for preparing the nucleation layer 200 is 20.4 to 72 min;

[0074] b) The flow rate of the carrier gas is 70 to 161.5 slm, the flow rate of the aluminum source is 204 to 480 sccm, and the time for preparing the nucleation layer 200 is 20 to 60 minutes.

[0075] By adopting one of the parameters a) or b), the temperature field change caused by the change of the graphite disk can be neutralized, ensuring the growth of a high-quality and high-uniformity nucleation layer.

[0076] In some embodiments, the epitaxial reaction chamber includes at least two groups of gas delivery pipes; the gas delivery pipes include a first delivery pipe and a second delivery pipe, the first delivery pipe is arranged at the top of the epitaxial reaction chamber, and the second delivery pipe is arranged at the bottom of the epitaxial reaction chamber. By adopting the form of dual gas delivery pipes, the uniformity of epitaxial growth can be controlled by the total gas flow ratio of the upper and lower pipes and the special gas flow ratio, and high-quality and high-uniform epitaxy can be grown by controlling the flow field change and the temperature field change.

[0077] Based on the above embodiment, the step of introducing a carrier gas, an aluminum source and a nitrogen source to prepare a nucleation layer 200 on the substrate surface satisfies at least one of the following characteristics:

[0078] c) the total flow rate of the carrier gas is 100-170 slm, and the total flow rate of the aluminum source is 200-400 sccm; the ammonia gas in the first delivery pipe has a first flow rate Q1, and the carrier gas has a second flow rate Q2; the ammonia gas in the second delivery pipe has a third flow rate Q3, and the carrier gas has a fourth flow rate Q4;

[0079] Satisfy: Q1:Q3=2.1~26:1, and Q2:Q4=1:1.1~2;

[0080] d) the total flow rate of the carrier gas is 100-170 slm, the total flow rate of the aluminum source is 200-400 sccm, the ammonia gas in the first delivery pipe has a fifth flow rate Q5, and the carrier gas has a sixth flow rate Q6; the ammonia gas in the second delivery pipe has a seventh flow rate Q7, and the carrier gas has an eighth flow rate Q8;

[0081] Satisfies: Q5:Q7=2~20:1, and Q6:Q8=1:1.1~2.

[0082] When the flow rates of ammonia and carrier gas in the first delivery pipe and the second delivery pipe satisfy one of the parameters c) or d), the nucleation layer 200, ie, the growth of aluminum nitride, can be further optimized so that the generated aluminum nitride has uniform quality and fewer defects.

[0083] In some embodiments, the carrier gas includes hydrogen.

[0084] In some embodiments, the aluminum source includes trimethylaluminum.

[0085] In some embodiments, the nitrogen source includes ammonia gas.

[0086] The substrate is single crystal silicon.

[0087] In some embodiments, the step of completing epitaxial preparation on the surface of the nucleation layer 200 further includes:

[0088] A buffer layer 300 is prepared on the nucleation layer 200;

[0089] Forming a channel layer 400 on the buffer layer 300;

[0090] forming a barrier layer 600 on the channel layer 400;

[0091] A surface layer 700 is prepared on the barrier layer 600 .

[0092] In some embodiments, before the step of preparing the barrier layer 600 on the channel layer 400, the method further includes:

[0093] An insertion layer 500 is formed on the gallium nitride channel layer 400 .

[0094] A second embodiment of the present application provides a silicon-based gallium nitride epitaxial wafer, which is prepared by using the method for preparing an epitaxial wafer in any of the above embodiments.

[0095] See also Figure 2 In some embodiments, the GaN-on-Si epitaxial wafer comprises:

[0096] Substrate layer 100;

[0097] A nucleation layer 200 , wherein the nucleation layer 200 is located on one side of the substrate layer 100 ;

[0098] A buffer layer 300 , wherein the buffer layer 300 is located on a side of the nucleation layer 200 away from the substrate layer 100 ;

[0099] A channel layer 400 , where the channel layer 400 is located on a side of the buffer layer 300 away from the nucleation layer 200 ;

[0100] A barrier layer 600 , where the barrier layer 600 is located on a side of the channel layer 400 away from the buffer layer 300 ;

[0101] The surface layer 700 is located on a side of the barrier layer 600 away from the channel layer 400 .

[0102] In some embodiments, the thickness of the nucleation layer 200 is 150-300 nm. It is understood that the thickness (in nm) of the nucleation layer 200 can be any value among 150, 200, 250, 300 or a range between any two values.

[0103] In some embodiments, the buffer layer 300 includes at least one of aluminum gallium nitride, gallium nitride, and a superlattice structure;

[0104] Superlattice structures include AlN / GaN, AlN / AlGaN, AlGaN / GaN, Al x Ga 1-x N / A y Ga 1-y At least one of N, where 0≤y <x≤1。

[0105] In some embodiments, the channel layer 400 is undoped gallium nitride, and the thickness of the channel layer 400 is 80-400 nm. It is understood that the thickness of the channel layer 400 (unit: nm) can be any value among 80, 100, 200, 300, 400 or a range between any two values.

[0106] In some embodiments, the barrier layer 600 is aluminum gallium nitride, and the thickness of the barrier layer 600 is 12-30 nm. It is understood that the thickness of the barrier layer 600 (unit: nm) can be any value among 12, 16, 20, 24, 30 or a range between any two values.

[0107] In some embodiments, the surface layer 700 includes one of nGaN, SiN, or pGaN.

[0108] In some embodiments, an insertion layer 500 is further disposed between the channel layer 400 and the barrier layer 600;

[0109] The insertion layer 500 is aluminum nitride, and the thickness of the insertion layer 500 is 1-5 nm. It is understood that the thickness of the insertion layer 500 (unit: nm) can be any value of 1, 2, 3, 4, 5 or a range between any two values.

[0110] A silicon-based gallium nitride epitaxial wafer and a method for preparing the same are described below through specific embodiments.

[0111] Example 1

[0112] This embodiment provides a silicon-based gallium nitride epitaxial wafer, which is prepared by the following steps:

[0113] S1. Provide a graphite base for 6-inch silicon wafers and place it in the epitaxial reaction chamber. The base includes a groove 10. The bottom wall 11 of the groove 10 is raised along the first direction X to form a convex spherical surface. The chord height of the convex spherical surface is 300 μm, and a SiC coating with a uniform thickness of 100 μm is coated on the surface.

[0114] S2, providing a silicon-based substrate, and placing the substrate in the groove 10 of the base as a substrate layer 100;

[0115] S3, introducing hydrogen, trimethylaluminum and ammonia into the epitaxial reaction chamber, and using metal organic compound vapor phase epitaxy to prepare an aluminum nitride nucleation layer 200 on the substrate surface, wherein the hydrogen flow rate is 100 slm, the trimethylaluminum flow rate is 350 sccm, the ammonia flow rate is 10 slm, the reaction time is 40 min, and the thickness of the nucleation layer 200 is 200 nm;

[0116] S4, preparing a buffer layer 300 on the nucleation layer 200, wherein the buffer layer 300 includes:

[0117] The first buffer layer 301 is made of aluminum gallium nitride, with an aluminum mass fraction of 80% and a thickness of 200 nm;

[0118] The second buffer layer 302 is made of aluminum gallium nitride, with an aluminum mass fraction of 60% and a thickness of 300 nm;

[0119] The third buffer layer 303 is made of aluminum gallium nitride, with an aluminum mass fraction of 40% and a thickness of 400 nm;

[0120] The fourth buffer layer 304 is made of aluminum gallium nitride, with an aluminum mass fraction of 20% and a thickness of 500 nm;

[0121] The fifth buffer layer 305 is made of carbon-doped gallium nitride, the doping source is ethylene, and the carbon doping concentration is 5e19cm 3 ;

[0122] S5, preparing a gallium nitride electron channel layer 400 on the buffer layer 300, with a thickness of 250 nm;

[0123] S6, preparing an aluminum nitride insertion layer 500 on the gallium nitride electronic channel layer 400, with a thickness of 1.5 nm,

[0124] S7, preparing an aluminum gallium nitride barrier layer 600 on the aluminum nitride insertion layer 500, wherein the aluminum mass component of the barrier layer 600 is 23% and the thickness is 25 nm;

[0125] S8. Prepare an nGaN surface layer 700 on the aluminum gallium nitride barrier layer 600. The doping source is silane, the doping flow rate is 500 sccm, and the thickness of the surface layer 700 is 2 nm.

[0126] The structure of the silicon-based gallium nitride epitaxial wafer prepared in this embodiment is as follows Figure 3 shown.

[0127] Embodiments 2 to 6

[0128] The preparation steps of the silicon-based gallium nitride epitaxial wafers of Examples 2 to 6 are consistent with those of Example 1, with only some process parameters being adjusted.

[0129] Comparative Examples 1-2

[0130] The preparation steps of the silicon-based gallium nitride epitaxial wafers of Comparative Examples 1-2 are consistent with those of Example 1, and only some process parameters are adjusted.

[0131] Comparative Examples 3-4

[0132] The preparation steps of the silicon-based gallium nitride epitaxial wafers of Comparative Examples 3 to 4 are respectively consistent with those of Example 1 and Comparative Example 1, with the only difference being that a base having a flat bottom wall 11 of the groove 10 is used.

[0133] The process parameters in Examples 1 to 6 and Comparative Examples 1 to 4 are shown in Table 1.

[0134] Table 1

[0135]

[0136] The temperature, warpage, crystal quality, barrier layer thickness and aluminum composition of the epitaxial wafers grown in the above-mentioned Examples 1 to 6 and Comparative Examples 1 to 3 were monitored, and the test method was as follows:

[0137] 1) Real-time temperature, warpage and curvature testing

[0138] Use the Laytec Epi TT Curve monitoring system to monitor the temperature distribution and changes, and warpage changes during epitaxial growth in real time.

[0139] 2) Crystal quality test

[0140] A high-resolution X-ray diffractometer was used to detect the crystal quality of the AlN nucleation layer (AlN(002) FWHM) and the crystal quality of the GaN channel layer (GaN(002) FWHM, GaN(102) FWHM) of the epitaxial wafer.

[0141] 3) Barrier layer thickness test

[0142] The thickness and thickness uniformity of the barrier layer were detected using an X-ray reflection system.

[0143] 4) Barrier layer component test

[0144] The aluminum composition and uniformity of the barrier layer were detected using a photoluminescence spectrometer.

[0145] The test results are shown in Table 2.

[0146] Table 2

[0147]

[0148] It can be seen from Table 2 that:

[0149] The AlN(002) of Comparative Example 1 is significantly lower than that of Example 1, indicating that only replacing the graphite disk structure without using the aluminum nitride buffer layer optimization process will affect the quality of the aluminum nitride buffer layer, and the subsequent gallium nitride crystal quality will also be affected accordingly;

[0150] Compared with Comparative Examples 1 and 3, AlN(002) in Example 1 is only slightly lower than that in Comparative Example 3, indicating that the method of reducing carrier gas and increasing aluminum nitride growth time basically offsets the adverse effect of replacing the graphite disk on the quality of the aluminum nitride buffer layer crystal; and compared with Comparative Example 3, the temperature difference between the center and the edge of the barrier layer in Example 1 is significantly reduced, so that its maximum warping degree is improved, the barrier layer thickness uniformity is reduced from 3.82% to 2.45%, and the aluminum component uniformity is reduced from 2.88% to 1.04%; at the same time, the improvement of the temperature field significantly improves the quality of the epitaxial crystal, and GaN(002) and (102) are both improved by about 70 arcsec, indicating that the special graphite disk of the present invention combined with the aluminum nitride growth optimization method significantly improves the quality and uniformity of the gallium nitride epitaxial wafer.

[0151] The above is a detailed introduction to an epitaxial wafer and a preparation method thereof provided in the embodiments of the present application. Specific examples are used in the present application to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a silicon-based gallium nitride epitaxial wafer, characterized in that: The steps include: A base is provided, and is placed in an epitaxial reaction chamber. The base comprises a groove (10). A bottom wall (11) of the groove (10) is raised along a first direction, and the bottom wall (11) is a convex spherical surface. The groove (10) has a side wall (12), and the side wall (12) is connected to the bottom wall (11) and has an angle α, which satisfies: 5°≤α≤30°. Providing a substrate, and placing the substrate in the groove (10) of the base; Passing a carrier gas, an aluminum source and a nitrogen source to prepare a nucleation layer (200) on the surface of the substrate; completing epitaxial growth on the surface of the nucleation layer (200); The step of introducing a carrier gas, an aluminum source and a nitrogen source to prepare a nucleation layer (200) on the surface of the substrate satisfies any one of the following characteristics: a) the flow rate of the carrier gas is 70 to 161.5 slm, the flow rate of the aluminum source is 200 to 400 sccm, and the time for preparing the nucleation layer (200) is 20.4 to 72 min; b) The flow rate of the carrier gas is 70 to 161.5 slm, the flow rate of the aluminum source is 204 to 480 sccm, and the time for preparing the nucleation layer (200) is 20 to 60 minutes.

2. The method for preparing a silicon-based gallium nitride epitaxial wafer according to claim 1, characterized in that: The chord height of the convex spherical surface is 30 to 1000 μm.

3. The method for preparing a silicon-based gallium nitride epitaxial wafer according to claim 1, characterized in that: The base is made of graphite; and / or, The surface of the groove (10) is provided with a silicon carbide coating.

4. The method for preparing a silicon-based gallium nitride epitaxial wafer according to claim 1, characterized in that: The flow rate of the nitrogen source is 1500-12000 sccm.

5. The method for preparing a silicon-based gallium nitride epitaxial wafer according to claim 4, characterized in that: The epitaxial reaction chamber includes at least two groups of gas delivery pipes; the gas delivery pipes include a first delivery pipe and a second delivery pipe, the first delivery pipe is arranged at the top of the epitaxial reaction chamber, and the second delivery pipe is arranged at the bottom of the epitaxial reaction chamber.

6. The method for preparing a silicon-based gallium nitride epitaxial wafer according to claim 5, characterized in that: The step of introducing a carrier gas, an aluminum source and a nitrogen source to prepare a nucleation layer (200) on the surface of the substrate satisfies at least one of the following characteristics: c) the total flow rate of the carrier gas is 100-170 slm, the total flow rate of the aluminum source is 200-400 sccm; the ammonia gas in the first delivery pipe has a first flow rate Q1, and the carrier gas has a second flow rate Q2; the ammonia gas in the second delivery pipe has a third flow rate Q3, and the carrier gas has a fourth flow rate Q4; Satisfy: Q1:Q3=2.1~26:1, and Q2:Q4=1:1.1~2; d) the total flow rate of the carrier gas is 100-170 slm, the total flow rate of the aluminum source is 200-400 sccm, the ammonia gas in the first delivery pipe has a fifth flow rate Q5, and the carrier gas has a sixth flow rate Q6; the ammonia gas in the second delivery pipe has a seventh flow rate Q7, and the carrier gas has an eighth flow rate Q8; Satisfies: Q5:Q7=2~20:1, and Q6:Q8=1:1.1~2.

7. The method for preparing a silicon-based gallium nitride epitaxial wafer according to claim 1, characterized in that: The carrier gas comprises hydrogen; and / or, The aluminum source includes trimethylaluminum; and / or, The nitrogen source comprises ammonia; and / or, The substrate is single crystal silicon.

8. The method for preparing a silicon-based gallium nitride epitaxial wafer according to claim 1, characterized in that: The step of completing epitaxial preparation on the surface of the nucleation layer (200) further comprises: Preparing a buffer layer (300) on the nucleation layer (200); Preparing a channel layer (400) on the buffer layer (300); Preparing a barrier layer (600) on the channel layer (400); A surface layer (700) is prepared on the barrier layer (600).

9. The method for preparing a silicon-based gallium nitride epitaxial wafer according to claim 8, characterized in that: Before the step of preparing the barrier layer (600) on the channel layer (400), the method further comprises: An insertion layer (500) is prepared on the channel layer (400).

10. A silicon-based gallium nitride epitaxial wafer, characterized in that: The epitaxial wafer is prepared by the method for preparing the epitaxial wafer according to any one of claims 1 to 9.

11. The silicon-based gallium nitride epitaxial wafer according to claim 10, characterized in that: The silicon-based gallium nitride epitaxial wafer comprises: A substrate layer (100); a nucleation layer (200), the nucleation layer (200) being located on one side of the substrate layer (100); a buffer layer (300), the buffer layer (300) being located on a side of the nucleation layer (200) away from the substrate layer (100); A channel layer (400), the channel layer (400) being located on a side of the buffer layer (300) away from the nucleation layer (200); A barrier layer (600), the barrier layer (600) being located on a side of the channel layer (400) away from the buffer layer (300); A surface layer (700), wherein the surface layer (700) is located on a side of the barrier layer (600) away from the channel layer (400).

12. The silicon-based gallium nitride epitaxial wafer according to claim 11, characterized in that: The thickness of the nucleation layer (200) is 150-300 nm.

13. The silicon-based gallium nitride epitaxial wafer according to claim 11, characterized in that: The buffer layer (300) comprises at least one of aluminum gallium nitride, gallium nitride, and a superlattice structure; The superlattice structure includes AlN / GaN, AlN / AlGaN, AlGaN / GaN, Al x Ga 1-x N / A y Ga 1-y At least one of N, where 0≤y <x≤1。 14. The silicon-based gallium nitride epitaxial wafer according to claim 11, characterized in that: The channel layer (400) is undoped gallium nitride, and the thickness of the channel layer (400) is 80 to 400 nm; and / or, The barrier layer (600) is aluminum gallium nitride, and the thickness of the barrier layer (600) is 12 to 30 nm; and / or, The surface layer (700) includes one of nGaN, SiN or pGaN.

15. The silicon-based gallium nitride epitaxial wafer according to claim 11, characterized in that: An insertion layer (500) is further provided between the channel layer (400) and the barrier layer (600); The insertion layer (500) is aluminum nitride, and the thickness of the insertion layer (500) is 1 to 5 nm.

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