A voltage output constraint control method for parallel converters

Abstract

The present invention relates to a parallel converter voltage output constraint control method, which uses the backstepping control technology to constrain and synchronously control the output voltage and current of the parallel converter system respectively: establish a dynamic mathematical model of the parallel converter system; based on the dynamic mathematical model of the parallel converter system, use coordinate transformation to convert it into a new magnetic suspension system state space equation suitable for using the backstepping control technology; consider the system startup process to select the time-varying voltage tracking error constraint boundary, set the expected output voltage to determine the current sharing target; use the backstepping control technology to design the controller to achieve the output voltage constraint and current synchronization control target. While ensuring the limited time tracking of the system, the present invention can effectively suppress the influence of load disturbance and line parameter mismatch on the system operation, and ensure the reliable and stable operation of the parallel Buck converter system.

Description

Technical Field

[0001] The present invention relates to a control method, in particular to a voltage output constraint control method for a parallel converter, and belongs to the technical field of power electronics. Background Art

[0002] Parallel converters offer advantages such as large capacity, high efficiency, high reliability, and low cost. However, coupling effects between modules make them susceptible to external disturbances and uncertainties, as well as mismatches caused by inconsistent line parameters. This makes constant load voltage control and converter current sharing challenging. While traditional adaptive algorithms can achieve voltage and current sharing, they fall short of the growing demand for high performance and reliability. Some employ sliding-mode control to achieve voltage tracking and current sharing, but this inherently suffers from chattering. To address load disturbances, some employ finite-time load observers to extract load disturbances and combine them with finite-time control techniques to achieve voltage tracking and current sharing, but this is affected by mismatches in parallel line parameters. Other literature has applied H∞ control to parallel converter control, improving the system's dynamic performance and robustness. Other researchers have combined dynamic performance specification with sliding-mode control to achieve voltage-constrained control of a single-buck converter.

[0003] However, it is worth noting that existing research on parallel converter control almost exclusively focuses on voltage tracking accuracy during load disturbances, without specifying specific voltage performance requirements or considering parallel line parameter mismatches. This makes it difficult to guarantee load output voltage anti-interference capabilities and current synchronization performance. In fact, with the rapid development of power electronics technology, load voltage anti-interference performance is one of our goals. In particular, parallel line parameter mismatches can cause parallel modules to generate circulating power, affecting current synchronization and voltage tracking performance while seriously shortening the service life of power electronic components, which cannot be ignored. Summary of the Invention

[0004] The main purpose of the present invention is: to address the deficiencies and gaps in the existing technology, the present invention provides a voltage output constraint control method for a parallel converter, selects a barrier Lyapunov function and a time-varying constraint boundary to improve the system's rapid tracking capability and anti-interference performance, achieves the system output voltage to be stable during load disturbances and the inductor current to remain consistent, and ensures that the anti-interference performance of the entire system is optimized in real time.

[0005] In order to achieve the above objectives, the present invention provides a voltage output constraint control method for parallel converters, comprising the following steps:

[0006] Step 1: Construct a dynamic mathematical model of the parallel converter that comprehensively considers load disturbance and line resistance mismatch;

[0007] Step 2: Select a time-varying constraint boundary that comprehensively considers the system voltage startup time, overshoot, and steady-state error, and set the voltage and current control targets;

[0008] Step 3: Design a load disturbance finite-time observer, a shunt current estimation model, and a line resistance mismatch differential estimator.

[0009] Step 4: Use backstepping and finite time control techniques to design the voltage output constraint controller and the parallel current sharing controller respectively.

[0010] The dynamic mathematical model of the parallel converter considering the load disturbance and line resistance mismatch in step 1 is:

[0011]

[0012] Where E is the DC voltage source, U c is the output voltage, is the inductor current, C is the filter capacitor, L1 and L2 are the filter inductors, μ1 and μ2 are the system control inputs, R=R0+ΔR, R0 is the nominal value of the load resistance, ΔR represents the load disturbance, L0 is the nominal value of the inductor L1 and L2, D1, D2, and D3 represent the load disturbance and line resistance mismatch.

[0013] In step 2, the time-varying constraint boundary considering the system voltage startup time, overshoot, and steady-state error is selected as

[0014]

[0015] Where c1 represents the time-varying constraint boundary of the voltage tracking error, c2 represents the time-varying constraint boundary of the voltage tracking error change rate, ρ1,ρ 1∞ ,w1,ρ2,ρ 2∞ ,w2 is a positive scalar, ρ1 represents the maximum limit of overshoot and undershoot of voltage tracking error, ρ 1∞ represents the maximum limit of the steady-state error preset, w1 represents the voltage start-up time, ρ2 represents the maximum limit of the voltage tracking error change rate, ρ 2∞ It represents the maximum limit of the voltage steady-state error change rate, and w2 represents the voltage change rate stabilization time;

[0016] The voltage and current control targets are set to

[0017]

[0018] Where U d is the desired output voltage.

[0019] In step 3:

[0020] A) The load disturbance finite-time observer is designed as

[0021]

[0022] Where, are the estimated values ​​of x1, x2 and the estimated disturbance D1, l1, l2, l3, σ1, σ2 are the designed observer parameters;

[0023] B) The parallel current estimation model is designed as

[0024] Where, Current estimated value;

[0025] C) The line resistance mismatch differential estimator is designed as

[0026]

[0027] Where, is the differentiator output, is the input signal, ζ, ξ1, ξ2 are the differential estimator parameters to be designed.

[0028] The controller design steps in step 4 are:

[0029] A) Voltage Output Constraint Controller

[0030] Take x d =U d , define the variable e1 = x1-x d , For e1, Where α is the virtual control input variable, and the logarithmic Lyapunov function is constructed as Taking the derivative of V1 with respect to t, we get

[0031]

[0032] make Then formula (7) can be obtained

[0033]

[0034] Where k1, s1, and γ are designable controller parameters.

[0035] for have Construct the logarithmic Lyapunov function as Taking the derivative of V2 with respect to t, we get

[0036]

[0037] The control input is designed to be

[0038]

[0039] Where k2 and s2 are the designed controller parameters.

[0040] B) Parallel current sharing controller

[0041] definition but Select Lyapunov function Taking the derivative of V3 with respect to t, we get

[0042]

[0043] The control input is designed to be

[0044]

[0045] Where, k3, s3 are the designed controller parameters;

[0046] C) Combining equations (9), (10), (11), and (12), we can get

[0047]

[0048] Using Young's inequality

[0049]

[0050] And because Then formula (13) can be transformed into

[0051]

[0052] Select by parameters

[0053]

[0054] Then formula (15) can be written as

[0055] The designed controller can achieve the finite time output voltage constraint and current control objectives.

[0056] The beneficial effects of the present invention are:

[0057] While ensuring the finite-time stability of the system, this control method can effectively suppress the impact of load disturbances and line parameter mismatches on system operation; it allows the load output voltage at system startup to converge to the desired output voltage within a finite time under the specified error constraint boundary, and can use the constraint boundary to make the voltage deviation fall back in the shortest time during load disturbances; it can also synchronize the inductive currents of the parallel converters within a finite time, effectively avoiding the generation of circulating power, thereby improving the energy utilization of the parallel system and ensuring that the performance of the output voltage constraint process is optimized in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Attachment Figure 1 Schematic diagram of the structure of the parallel converter of the present invention.

[0059] Attachment Figure 2 This is the load disturbance output voltage simulation curve of the present invention.

[0060] Attachment Figure 3 This is the load disturbance voltage tracking deviation and constraint boundary curve of the present invention.

[0061] Attachment Figure 4 This is the action curve of the constraint controller of the present invention.

[0062] Attachment Figure 5 This is the current simulation curve of the inductor L1 of the present invention.

[0063] Attachment Figure 6 This is the current simulation curve of the inductor L2 of the present invention.

[0064] Attachment Figure 7 This is the aggregate interference D1 estimation curve of the present invention.

[0065] Attachment Figure 8 This is the aggregate interference D2 estimation curve of the present invention.

[0066] Attachment Figure 9 This is the aggregate interference D3 estimation curve of the present invention.

[0067] In the figure: 1-DC voltage source E; 2-inductor L1; 3-inductor L2; 4-filter capacitor; 5-load resistor. DETAILED DESCRIPTION

[0068] The present invention is further described below with reference to a preferred embodiment.

[0069] Example 1:

[0070] As attached Figure 1 As shown, Buck1 and Buck2 jointly power the load R. They control the on and off of IGBT1 and IGBT2 respectively, making them work in continuous conduction mode to generate a stable current i on inductors L1 and L2. L1and i L2 , while maintaining a stable load voltage Uc while supplying current to load R. During system startup, controllers u1 and u2 quickly complete voltage tracking and achieve the current sharing target. During load disturbances, the system generates a voltage tracking error. The constraint controller quickly adjusts u1 and u2 to generate a control variable that ensures a rapid voltage drop until the voltage tracking error is restored.

[0071] The system parameters of the parallel converter are as follows: DC power supply voltage 50V, inductor L1 is 12mH, inductor L2 is 13mH, filter capacitor C is 10 -3 μF, IGBT switching frequency is 10kHz.

[0072] Under the above parameter conditions, the system operating conditions are designed as follows: (I) System startup process: The running time is t=0s, and the expected output voltage of this process is selected as U d =24 V, load resistance R = 12 Ω; (II) Simulated load disturbance application process: expected output voltage 24 V, causing load R to drop from 12 Ω to 6 Ω; (II) Simulated load disturbance removal process: expected output voltage 24 V, causing load R to increase from 6 Ω to 12 Ω.

[0073] The system is simulated according to the above working condition design to verify the system's ability to resist load disturbances during the system startup and operation. Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 shown.

[0074] Attachment Figure 2 The voltage output curve is shown in the figure. As can be seen from the figure, the system can reach the desired output voltage of 24V in 8ms. In the case of a load disturbance of t=2s, the load voltage only drops by 0.3V and returns to normal within 2ms. In the case of a disturbance removal of t=4s, the load voltage only rises by 0.3V and returns to normal within 2ms. The output voltage remains constant throughout the load disturbance process as shown in the figure. Figure 3 The dotted line shows the constraint boundary c1.

[0075] Attachment Figure 4 The constraint controller action curve is shown in Figure 2. It can be seen that at t = 2s and t = 4s, when the load disturbance is applied and removed, the constraint controller generates a significant force, minimizing the output voltage deviation. This demonstrates the effectiveness of the constraint controller.

[0076] Attachment Figure 5 , Attachment Figure 6These are the current simulation curves of inductor L1 and inductor L2, as can be seen from the figure, at the startup moment, the two converters quickly provide current to the load to achieve the desired voltage of 24V, and the load disturbance application and load disturbance removal moments occur at t=2s and t=4s, respectively, which generate small current rise and fall values ​​to ensure minimum voltage fluctuation, and provide stable current in the hysteresis process to ensure smooth operation of the system, and inductor L1 and inductor L2 achieve the current sharing control target in the whole process.

[0077] Attachment Figure 7 The figure shows the disturbance D1 estimation curve. It can be seen from the figure that when load disturbances occur at t=2s and t=4s, the observer can make adjustments quickly and quickly restore stability after the load disturbance disappears.

[0078] Attachment Figure 8 , Attachment Figure 9 Shown are the interference D2 and D3 estimation curves respectively. It can be seen from the figure that in the entire control process, the differential estimator can effectively obtain the line mismatch situation to ensure the effective completion of the control target.

[0079] The above results show that the control method of the present invention can effectively suppress the influence of load and line parameter mismatch while ensuring the anti-interference ability of the system, and ensure the stable and reliable operation of the parallel converter within the output voltage constrained range.

Claims

1. A voltage output constraint control method for parallel converters, characterized in that: The following steps are involved: Step 1: Construct a dynamic mathematical model of parallel converters that comprehensively considers load disturbances and line resistance mismatch Where E is the DC voltage source, U c is the output voltage, is the inductor current, C is the filter capacitor, L1, L2 are the filter inductors, μ1, μ2 are the system control inputs, R=R0+ΔR, R0 is the nominal value of the load resistance, ΔR represents the load disturbance, L0 is the nominal value of the inductor L1, L2, D1, D2, D3 represent the load disturbance and line resistance mismatch; Step 2: Considering the system voltage startup time, overshoot, and steady-state error, the time-varying constraint boundary is selected as Where c1 represents the time-varying constraint boundary of the voltage tracking error, c2 represents the time-varying constraint boundary of the voltage tracking error change rate, ρ1,ρ 1∞ ,w1,ρ2,ρ 2∞ , w2 is a positive scalar, ρ1 represents the maximum limit of overshoot and undershoot of voltage tracking error, ρ 1∞ represents the maximum limit of the steady-state error preset, w1 represents the voltage start-up time, ρ2 represents the maximum limit of the voltage tracking error change rate, ρ 2∞ represents the maximum limit of the voltage steady-state error change rate, and w2 represents the voltage change rate stabilization time; The voltage and current control targets are set as Where U d is the expected output voltage; Step 3: Design the load disturbance finite time observer, the shunt current estimation model, and the line resistance mismatch differential estimator A) The load disturbance finite-time observer is designed as In the formula, are the estimated values ​​of x1, x2 and the estimated disturbance D1, l1, l2, l3, σ1, σ2 are the designed observer parameters; B) The parallel current estimation model is designed as In the formula, The current Estimated value; C) The line resistance mismatch differential estimator is designed as In the formula, is the differentiator output, is the input signal, ζ, ξ1, ξ2 are the differential estimator parameters to be designed; Step 4: Use backstepping and finite time control techniques to design the voltage output constraint controller and parallel current sharing controller respectively. A) Voltage Output Constraint Controller Take x d =U d , define variable e1 = x1-x d , For e1, Where α is a virtual control input variable, and the logarithmic Lyapunov function is constructed as Taking the derivative of V1 with respect to t, we get make Then formula (7) can be obtained Where k1, s1, and γ are designable controller parameters; for have Construct the logarithmic Lyapunov function as Taking the derivative of V2 with respect to t, we get The control input is designed to be Where, k2, s2 are the designed controller parameters; B) Parallel current sharing controller definition but Select the Lyapunov function Taking the derivative of V3 with respect to t, we get The control input is designed to be Where, k3, s3 are the designed controller parameters; C) Combining equations (9), (10), (11), (12), we can get Using Young's inequality And because Then formula (13) can be transformed into Select by parameters Then formula (15) can be written as The designed controller can achieve finite-time output voltage constraint and current control objectives.

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