Dead time control circuit, voltage converter and switching power supply

Abstract

The present application is applicable to the technical field of switching power supply, and provides a dead time control circuit, a voltage converter and a switching power supply. The dead time control circuit includes a sampling module, a comparison module, a counting module and a first delay module. The comparison module is electrically connected to the sampling module and the counting module respectively, the counting module is electrically connected to the first delay module, the sampling module is used to be electrically connected to the gate of the lower switch tube, the drain of the lower switch tube and the source of the upper switch tube respectively, and the first delay module is used to be electrically connected to the driving module. The dead time control circuit provided in the embodiment of the present application delays the input signal through the synergistic effect of the sampling module, the comparison module, the counting module and the first delay module, thereby adjusting the first driving signal and realizing the control of the dead time. After multiple cycles of adjustment and control, the dead time is gradually stabilized within a preset range, thereby improving the conversion efficiency of the voltage converter.

Description

Technical Field

[0001] The present application belongs to the technical field of switching power supplies, and in particular relates to a dead time control circuit, a voltage converter and a switching power supply. Background Art

[0002] In traditional voltage converters (such as DC / DC converters), if the upper and lower switches are turned on at the same time, a large current will flow directly from the positive power supply (VDD) to the ground (GND). Therefore, a control circuit is configured in the synchronous rectification DC / DC converter to ensure that the upper and lower switches are not turned on at the same time. However, the time between the turn-on moment of the upper switch and the turn-off moment of the lower switch will form a dead time, but the body diode of the switch will be turned on during the dead time. If the dead time is too long, the body diode will store too much charge, making the SW rise time uncontrollable, and there may be excessive ringing and device breakdown. In order to solve the above problems, zero-level detection technology is usually used, that is, by collecting the voltage V at the SW sw and GND as the input of the comparator. When the voltage V sw When it is less than 0V, the lower switch tube will be turned on. In this way, the dead time is determined by the delay of the comparator and the drive circuit and V sw The time it takes for the voltage to drop below 0 V is jointly determined by the time it takes for the voltage to drop below 0 V. However, the delay of the comparator and the drive circuit will change with the changes in process parameters and environment, resulting in the dead time being unable to be stable and controllable. Summary of the invention

[0003] The embodiments of the present application provide a dead time control circuit, a voltage converter and a switching power supply, which can solve the problem that the dead time in the existing voltage conversion circuit cannot be stably controlled.

[0004] In a first aspect, an embodiment of the present application provides a dead time control circuit, comprising a sampling module, a comparison module, a counting module and a first delay module; the comparison module is electrically connected to the sampling module and the counting module respectively, the counting module is electrically connected to the first delay module, the sampling module is used to be electrically connected to the gate of the lower switch tube, the drain of the lower switch tube and the source of the upper switch tube respectively, and the first delay module is used to be electrically connected to the driving module;

[0005] The sampling module is used to generate a sampling trigger signal according to a first driving signal of the gate of the lower switch tube, sample the drain of the lower switch tube when the sampling trigger signal is at a first level, and output the sampling signal; the sampling module is also used to stop sampling the drain of the lower switch tube when the sampling trigger signal is at a second level, and keep outputting the sampling signal; the comparison module is used to output a comparison signal according to the sampling signal and a reference signal when the sampling trigger signal is at the second level; the counting module is used to count according to the comparison signal to obtain a counting value; the first delay module is used to determine a delay time according to the counting value; and the driving module is used to adjust the first driving signal according to the delay time.

[0006] In a possible implementation of the first aspect, the sampling module includes a sample holder, a first input end of the sample holder is electrically connected to the gate of the lower switch tube, a second input end of the sample holder is electrically connected to the drain of the lower switch tube and the source of the upper switch tube, respectively, and a first output end and a second output end of the sample holder are electrically connected to the comparison module.

[0007] In a possible implementation of the first aspect, the comparison module includes a comparator, an enable end of the comparator is electrically connected to the sampling module for receiving the sampling trigger signal, a first input end of the comparator is electrically connected to the sampling module, a second input end of the comparator is used to receive the reference signal, and an output end of the comparator is electrically connected to the counting module.

[0008] In a possible implementation manner of the first aspect, the counting module includes a counter, an input end of the counter is electrically connected to the comparison module, and an output end of the counter is electrically connected to the first delay module.

[0009] In a possible implementation of the first aspect, the first delay module includes a first delay device, a control end of the first delay device is electrically connected to the counting module, an input end of the first delay device is used to receive an input signal, and an output end of the first delay device is used to be electrically connected to the driving module.

[0010] In a second aspect, an embodiment of the present application provides a voltage converter, comprising a driving module, an upper switch tube, a lower switch tube, and a dead time control circuit according to any one of the first aspects, wherein the driving module is electrically connected to the gate of the upper switch tube, the gate of the lower switch tube, and the first delay module in the dead time control circuit, respectively, and the source of the upper switch tube is electrically connected to the drain of the lower switch tube and the sampling module in the dead time control circuit, respectively;

[0011] The dead time control circuit is used to determine the delay time, and the driving module is used to adjust the first driving signal according to the delay time.

[0012] In a possible implementation manner of the second aspect, the driving module includes a first driving unit and a second driving unit, the first driving unit is electrically connected to the gate of the upper switch tube, and the second driving unit is electrically connected to the gate of the lower switch tube;

[0013] The first driving unit is used to output the second driving signal to the gate of the upper switch tube, and the second driving unit is used to output the first driving signal to the gate of the lower switch tube.

[0014] In a possible implementation of the first aspect, the voltage converter further includes a second delay module, the second delay module is electrically connected to the first drive unit, and the second delay module is used to delay the input signal for a preset time before transmitting it to the first drive unit.

[0015] In a possible implementation manner of the first aspect, the second delay module includes a second delay device, an input end of the second delay device is used to receive the input signal, and an output end of the second delay device is used to be electrically connected to the first driving unit.

[0016] In a third aspect, an embodiment of the present application provides a switching power supply, comprising the voltage converter described in any one of the second aspects.

[0017] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0018] The dead time control circuit provided by the embodiment of the present application includes a sampling module, a comparison module, a counting module and a first delay module. Among them, the sampling module generates a sampling trigger signal according to the first driving signal of the gate of the lower switch tube, samples the drain of the lower switch tube when the sampling trigger signal is at the first level, and outputs the sampling signal. The sampling module can also stop sampling the drain of the lower switch tube when the sampling trigger signal is at the second level, and keep the output sampling signal at this time, that is, keep the sampling value unchanged, and the comparison module is enabled, that is, the comparison module compares the sampling signal with the reference signal when the sampling trigger signal is at the second level, and outputs the comparison signal. The counting module counts according to the comparison signal to obtain the count value. The first delay module determines the delay time according to the count value, and the driving module adjusts the first driving signal according to the delay time. It can be seen from this that the dead time control circuit provided by the embodiment of the present application delays the input signal through the synergistic effect of the sampling module, the comparison module, the counting module and the first delay module, thereby adjusting the first driving signal to achieve control of the dead time. If the dead time is greater than the preset value, the dead time control circuit can increase the delay time, thereby controlling the turn-off time of the lower switch tube, even if the falling edge of the first drive signal output by the driving module is delayed. Since the dead time is the time between the turn-on time of the upper switch tube and the turn-off time of the lower switch tube, if the falling edge of the first drive signal driving the lower switch tube is delayed, the dead time will be reduced accordingly. If the dead time at this time is still greater than the preset value, the dead time control circuit will continue to increase the delay time to continue to reduce the dead time. After multiple cycles of cyclic adjustment, the dead time may disappear, which indicates that the delay time is greater than the preset time, and the dead time control circuit needs to reduce the delay time to ensure the existence of the dead time. After multiple cycles of adjustment and control, the dead time is gradually stabilized within the preset range, thereby improving the conversion efficiency of the voltage converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 It is a principle block diagram of an existing voltage converter;

[0021] Figure 2 It is a principle block diagram of an existing voltage converter using zero-level detection technology;

[0022] Figure 3 is a principle block diagram of a dead time control circuit provided in one embodiment of the present application;

[0023] Figure 4 It is a schematic diagram of working waveforms of a sampling module and a comparison module provided in an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of the working principle of the first delay module provided in one embodiment of the present application;

[0025] Figure 6 is a schematic diagram of the working waveform of the first delay module provided in one embodiment of the present application;

[0026] Figure 7 1 is a complete working waveform diagram of a dead time control circuit provided by an embodiment of the present application;

[0027] Figure 8 is a principle block diagram of a voltage converter provided by an embodiment of the present application;

[0028] Fig. 9 This is a principle block diagram of a voltage converter provided in another embodiment of the present application.

[0029] In the figure, 10, dead time control circuit; 101, sampling module; 102, comparison module; 103, counting module; 104, first delay module; 20, driving module; 201, first driving unit; 202, second driving unit; 30, second delay module. DETAILED DESCRIPTION

[0030] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0031] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0032] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0034] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0036] like Figure 1 As shown, in a traditional voltage converter (such as a DC / DC converter), if the upper switch Q1 and the lower switch Q2 are turned on at the same time, a large current will flow directly from the positive power supply (VDD) to the ground (GND). Therefore, a control circuit is configured in the synchronous rectification DC / DC converter to ensure that the upper and lower switches are not turned on at the same time. However, the time between the turn-on moment of the upper switch and the turn-off moment of the lower switch will form a dead time, but the body diode of the switch will be turned on during the dead time. If the dead time is too long, the body diode will store too much charge, making the SW rise time uncontrollable, and there may be excessive ringing and device breakdown. In order to solve the above problems, such as Figure 2 As shown, the existing voltage converter usually adopts zero-level detection technology, that is, by collecting the voltage V at SW sw and GND as the input of the comparator. When the voltage V sw When it is less than 0V, the lower switch tube will be turned on. In this way, the dead time is determined by the delay of the comparator and the drive circuit and V sw The time it takes for the voltage to drop below 0 V is jointly determined by the time it takes for the voltage to drop below 0 V. However, the delay of the comparator and the drive circuit will change with the changes in process parameters and environment, resulting in the dead time being unable to be stable and controllable.

[0037] The designer can select the type of the upper switch tube Q1 and the lower switch tube Q2 according to the actual situation, that is, both can use fully controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors. For example, the upper switch tube Q1 and the lower switch tube Q2 can be selected as NMOS tubes.

[0038] Based on the above problems, the dead time control circuit provided by the embodiment of the present application includes a sampling module, a comparison module, a counting module and a first delay module. Among them, the sampling module generates a sampling trigger signal according to the first driving signal of the gate of the lower switch tube, samples the drain of the lower switch tube when the sampling trigger signal is at the first level, and outputs the sampling signal. The sampling module can also stop sampling the drain of the lower switch tube when the sampling trigger signal is at the second level, and keep the output sampling signal at this time, that is, keep the sampling value unchanged, and the comparison module is enabled, that is, the comparison module compares the sampling signal with the reference signal when the sampling trigger signal is at the second level, and outputs the comparison signal. The counting module counts according to the comparison signal to obtain the count value. The first delay module determines the delay time according to the count value, and the driving module adjusts the first driving signal according to the delay time. It can be seen from this that the dead time control circuit provided by the embodiment of the present application delays the input signal through the synergistic effect of the sampling module, the comparison module, the counting module and the first delay module, thereby adjusting the first driving signal to achieve control of the dead time. If the dead time is greater than the preset value, the dead time control circuit can increase the delay time, thereby controlling the turn-off time of the lower switch tube, even if the falling edge of the first drive signal output by the driving module is delayed. Since the dead time is the time between the turn-on time of the upper switch tube and the turn-off time of the lower switch tube, if the falling edge of the first drive signal driving the lower switch tube is delayed, the dead time will be reduced accordingly. If the dead time at this time is still greater than the preset value, the dead time control circuit will continue to increase the delay time to continue to reduce the dead time. After multiple cycles of cyclic adjustment, the dead time may disappear, which indicates that the delay time is greater than the preset time, and the dead time control circuit needs to reduce the delay time to ensure the existence of the dead time. After multiple cycles of adjustment and control, the dead time is gradually stabilized within the preset range, thereby improving the conversion efficiency of the voltage converter.

[0039] In order to illustrate the technical solution described in this application, a specific embodiment is provided below for illustration.

[0040] Figure 3 FIG. 1 shows a principle block diagram of a dead time control circuit 10 provided in an embodiment of the present application. Figure 3As shown, the dead time control circuit 10 includes a sampling module 101, a comparison module 102, a counting module 103 and a first delay module 104. The comparison module 102 is electrically connected to the sampling module 101 and the counting module 103 respectively, the counting module 103 is electrically connected to the first delay module 104, the sampling module 101 is used to be electrically connected to the gate of the lower switch tube Q2, the drain of the lower switch tube Q2 and the source of the upper switch tube Q1 respectively, and the first delay module 104 is used to be electrically connected to the driving module 20.

[0041] Specifically, the sampling module 101 is based on the V lg Generate sampling trigger signal V sample , and the sampling trigger signal V sample When the voltage is at the first level, the drain of the lower switch Q2 (i.e., V sw ) to sample and output the sampling signal V sw-sample The sampling module 101 can also sample When the voltage is at the second level, the drain sampling of the lower switch tube Q2 is stopped, and the output sampling signal V is maintained. sw-sample , that is, keep the sampling value unchanged, the comparison module 102 is enabled, that is, the comparison module 102 is enabled when the sampling trigger signal V sample When the sampling signal V sw-sample and the reference signal V Ref Compare and output comparison signal V cmpout The counting module 103 calculates the value of the comparison signal V cmpout The first delay module 104 determines the delay time T according to the count value. delay , and the delayed input signal V pwm The delay time T is transmitted to the driving module 20, and the driving module 20 delay Adjust the first drive signal V output by the downward switch tube Q2 lg It can be seen that the dead time control circuit 10 provided in the embodiment of the present application, through the synergistic effect of the sampling module 101, the comparison module 102, the counting module 103 and the first delay module 104, controls the input signal V pwm Delay is performed to adjust the first drive signal V lg , to achieve control of the dead time. If the dead time is greater than the preset value, the dead time control circuit 10 can increase the delay time T delay , thereby controlling the turn-off time of the lower switch tube Q2, even if the first drive signal V output by the drive module 20 lg The falling edge time of the upper switch tube Q1 is delayed. Since the dead time is the time between the turn-on time of the upper switch tube Q1 and the turn-off time of the lower switch tube Q2, if the first drive signal V lgIf the dead time is still greater than the preset value, the dead time control circuit 10 will continue to increase the delay time T delay , so that the dead time continues to decrease. After multiple cycles of cyclic adjustment, the dead time may disappear, which indicates that the delay time T delay If the delay time is greater than the preset time, the dead time control circuit 10 needs to reduce the delay time T delay To ensure the existence of dead time. After multiple cycles of adjustment and control, the dead time is gradually stabilized within the preset range. At the same time, the influence of the drive circuit and the delay of the comparator is relatively small. By adjusting the delay time by digital and analog control, the dead time can be more accurately controlled to improve the conversion efficiency of the converter. In addition, the combination of digital control and analog control reduces the design difficulty, and the digital control has high reliability and high integration.

[0042] It should be noted that the preset value can be configured by the system or set by the user according to the design requirements of the corresponding circuit, and is not limited here. After the preset value is determined, the preset time can be determined.

[0043] It should be noted that the first level may be a high level, and the second level may be a low level. sample When the voltage is high, the sampling module 101 samples the drain of the lower switch tube Q2 and outputs a sampling signal V sw-sample When the sampling trigger signal V sample When the sampling module 101 is at a low level, it stops sampling the drain of the lower switch tube Q2 and keeps outputting the sampling signal V sw-sample The comparison module 102 samples the trigger signal V sample When it is low, the sampling signal V sw-sample and the reference signal V Ref Compare and output comparison signal V cmpout .

[0044] It should be noted that the counting module 103 outputs the comparison signal V cmpout When it is at a high level, an addition count is performed, and the comparison signal V output by the comparison module 102 is cmpout When the level is low, a subtraction count is performed. The counting module 103 can store the count value. The count value is a binary number, and the size of the binary number is determined by the comparison signal V output by the comparison module 102. cmpout Sure.

[0045] For example, if the default count value of the counting module 103 is set to 100, if the comparison signal V output by the comparison module 102 is cmpoutis high level. At this time, the count value output by the counting module 103 is 101.

[0046] It should be noted that the change in the count value of each cycle will take effect in the next cycle. After multiple cycles of adjustment, the actual dead time will approach the preset target value and switch back and forth at the boundary of the preset range (the count value will switch back and forth between two pre-designed values). At this time, it can be considered that the dead time has reached the target value.

[0047] In one embodiment of the present application, the sampling module 101 includes a sample holder, a first input end of the sample holder is electrically connected to the gate of the lower switch tube Q2, a second input end of the sample holder is electrically connected to the drain of the lower switch tube Q2 and the source of the upper switch tube Q1, respectively, and a first output end and a second output end of the sample holder are electrically connected to the comparison module 102.

[0048] Specifically, the sample-and-hold device is used to sample the analog signal and hold the sampled value until the next sampling cycle during the process of converting the analog signal into a digital signal. lg Generate sampling trigger signal V sample , and the sampling trigger signal V sample When it is at a high level, it samples the drain of the lower switch tube Q2 and outputs a sampling signal V sw-sample . When sampling trigger signal V sample When it is low level, sampling stops and the sampled value is held.

[0049] It should be noted that the sample-and-hold device generally includes an operational amplifier and a feedback resistor. The operational amplifier performs sampling, and the feedback resistor is used to hold the sampled value.

[0050] In one embodiment of the present application, the comparison module 102 includes a comparator, the enable terminal of the comparator is electrically connected to the sampling module 101, and is used to receive the sampling trigger signal V sample The first input terminal of the comparator is electrically connected to the sampling module 101, and the second input terminal of the comparator is used to receive the reference signal V Ref , the output end of the comparator is electrically connected to the counting module 103.

[0051] Specifically, the enable terminal of the comparator is used to receive the sampling trigger signal V sample The comparator samples the trigger signal V sample Enable. When the sampling trigger signal V sample When the sampling trigger signal V sample When it is low, the comparator will sample the signal V sw-sample and the reference signal V Ref For comparison, if the sampling signal Vsw-sample Greater than the reference signal V Ref , the comparison signal V output by the comparator cmpout is low level, if the sampling signal V sw-sample Less than the reference signal V Ref , the comparison signal V output by the comparator cmpout is high level.

[0052] It should be noted that if the sampling signal V sw-sample Equal to the reference signal V Ref , can output the corresponding level signal according to the configuration of the comparator, which can be a low level, a high level, or ignored, depending on the design of the comparator.

[0053] Combine the following Figure 4 The specific working process of the sampling module 101 and the comparison module 102 is described in detail.

[0054] Figure 4 In, V lg is the first driving signal output by the driving module 20, V sample is the sampling trigger signal, V sw is the drain voltage of the lower switch tube Q2, V sw-sample is the sampling signal, V Ref is the reference signal, V cmpout is the comparison signal. Figure 4 It can be seen that the time periods t1-t2, t3-t4, t5-t6 and t7-t8 are all sampling trigger signals V sample When the sampling module 101 is high, V sw Sampling and outputting V sw-sample , the comparator is not enabled and is in a low level state. The time periods t2-t3, t4-t5, t6-t7 and t8-t9 are all sampling trigger signals V sample When the level is low, the sampling module 101 stops sw Sampling and holding the output V sw-sample , the comparator is enabled and the sampling signal V sw-sample and the reference signal V Ref The sampling signal V is used for comparison. sw-sample Less than the reference signal V Ref , the comparison signal V output by the comparator cmpout The sampling signal V is high level, and the sampling signal V sw-sample Greater than the reference signal V Ref , the comparison signal V output by the comparator cmpout is low level.

[0055] In one embodiment of the present application, the counting module 103 includes a counter, an input end of the counter is electrically connected to the comparison module 102 , and an output end of the counter is electrically connected to the first delay module 104 .

[0056] Specifically, the counter is used to compare the signal V cmpout Counting, if the comparison signal V cmpout is high level, the counter performs addition counting. If the comparison signal V cmpout When the level is low, the counter counts down.

[0057] For example, if the default count value of the counting module 103 is set to 100, if the comparison signal V cmpout is high level, at this time, the count value output by the counting module 103 is 101. cmpout is low level, at this time, the count value output by the counting module 103 is 99. The counter can be a CMOS counter, such as a counter of model CD4026.

[0058] It should be noted that by increasing the number of binary bits, the error between the actual dead time and the target value can be further reduced, and the dead time can be controlled more accurately.

[0059] In one embodiment of the present application, the first delay module 104 includes a first delay device, a control end of the first delay device is electrically connected to the counting module 103, and an input end of the first delay device is used to receive an input signal V pwm The output end of the first delay device is used to be electrically connected to the driving module 20.

[0060] Specifically, the first delay device is used to determine the delay time T according to the count value. delay , the input signal V pwm After a delay, it is transmitted to the driving module 20 to adjust the first driving signal V output by the driving module 20 lg The falling edge time.

[0061] It should be noted that if Figure 5 As shown, the first delay device can adjust the delay time Delay according to the size of the count value. Whenever the count value increases or decreases by the preset value, the corresponding delay time Delay will also change accordingly. delay The change range of is the product of the change range of the count value and the step time, that is:

[0062]

[0063] Where, ∆T delay is the change range of delay time, ∆Data is the change range of count value, t stepis the step time.

[0064] It should be noted that the delay time T delay Used to instruct the driving module 20 to adjust the first driving signal V lg , specifically, if Figure 6 As shown, the delay time T delay The falling edge time of the first driving signal V output by the driving module 20 lg The falling edge time of is the same time. The dead time control circuit 10 can increase the delay time T delay , so that the first drive signal V lg There will also be a corresponding delay at the falling edge, that is, the delay time T delay It is used to control the closing time of the lower switch tube Q2. delay The falling edge of the first drive signal V lg Pull down.

[0065] Combine the following Figure 7 The specific working process of the dead time control circuit 10 is described in detail.

[0066] Figure 7 In, V hg is the second driving signal output by the driving module 20, that is, the voltage signal at the gate of the upper switch tube Q1, Dead-zone is the dead zone time, T delay is the delay time. Figure 7 It can be seen that the time periods t1-t2, t3-t4, t5-t6 and t8-t9 are all dead time. The input signal V is measured by the synergistic effect of the sampling module 101, the comparison module 102, the counting module 103 and the first delay module 104. pwm Delay is performed to adjust the first drive signal V lg , to achieve control of the dead time. In the first cycle, the dead time of the time period t1-t2 is greater than the preset value, and the dead time control circuit 10 can increase the delay time T delay , so that the first drive signal V lg The falling edge of the t3-t4 period will also have a corresponding delay. Therefore, in the second cycle, the dead time of the t3-t4 period will be reduced accordingly. If the dead time of the t3-t4 period is still greater than the preset value, the dead time control circuit 10 will continue to increase the delay time T delay , so that the input signal V pwm Therefore, in the third cycle, the dead time of the time period t5-t6 continues to decrease. If the dead time of the time period t5-t6 is still greater than the preset value, the dead time control circuit 10 will continue to adjust the dead time, but in the next cycle, the second drive signal V hgThe rising edge of the first driving signal V lg The falling edge of is at the same time, that is, time t7, which indicates that the dead time disappears. Characterizing the delay time T delay If the delay time is greater than the preset time, the dead time control circuit 10 needs to reduce the delay time T delay To ensure the existence of dead time. In the last cycle, dead time exists. Therefore, the delay time T is continuously adjusted. delay , to adjust the dead time. After multiple cycles of adjustment and control, the dead time can be stabilized within a preset range, thereby improving the conversion efficiency of the voltage converter.

[0067] In one embodiment of the present application, Figure 8 As shown, the voltage converter includes a driving module 20, an upper switch tube Q1, a lower switch tube Q2 and the above-mentioned dead time control circuit 10. The driving module 20 is electrically connected to the first delay module 104 in the dead time control circuit 10, the gate of the upper switch tube Q1 and the gate of the lower switch tube Q2, respectively. The source of the upper switch tube Q1 is electrically connected to the drain of the lower switch tube Q2 and the sampling module 101 in the dead time control circuit 10.

[0068] Specifically, the dead time control circuit 10 is used to determine the delay time T delay , the input signal V pwm After a delay, the signal is transmitted to the driving module 20, and the driving module 20 transmits the signal according to the delay time T delay Regulate the first drive signal V output by the gate of the downward switch tube Q2 lg The lower switch tube Q2 is driven by the first driving signal V lg On or off.

[0069] It should be noted that the driving module 20 is also used to output a second driving signal V to the gate of the upper switch tube Q1. hg , the upper switch tube Q1 is driven by the second driving signal V hg On or off.

[0070] In one embodiment of the present application, Fig. 9 As shown, the driving module 20 includes a first driving unit 201 and a second driving unit 202 . The first driving unit 201 is electrically connected to the gate of the upper switch tube Q1 , and the second driving unit 202 is electrically connected to the gate of the lower switch tube Q2 .

[0071] Specifically, the first driving unit 201 is used to output a second driving signal V to the gate of the upper switch tube Q1. hg , the upper switch tube Q1 is driven by the second driving signal V hg The second driving unit 202 is used to output a first driving signal V to the gate of the lower switch tube Q2. lgThe lower switch tube Q2 is driven by the first driving signal V lg On or off.

[0072] It should be noted that the first driving unit 201 and the second driving unit 202 may include an amplifier, a driver or a transistor, etc., for amplifying the input signal V pwm , and provide sufficient current and voltage amplitude to drive the upper switch tube Q1 and the lower switch tube Q2. The first driving unit 201 and the second driving unit 202 can both be timing control circuits for generating correct timing signals for controlling the switching tubes to be turned on and off.

[0073] In one embodiment of the present application, Fig. 9 As shown, the voltage converter further includes a second delay module 30, which is electrically connected to the first driving unit 201 and is used to delay the input signal V pwm The signal is transmitted to the first driving unit 201 after a preset delay.

[0074] Specifically, set the input signal V pwm The second delay module 30 between the input signal V pwm A fixed delay time, namely a preset time, is provided before reaching the driving module 20. The preset time may be pre-designed and will not change due to changes in process parameters or environmental conditions.

[0075] It should be noted that the second delay module 30 may be a simple delay line (such as an RC network composed of resistors and capacitors) or a specially designed delay unit such as a delay phase-locked loop or a delay line array.

[0076] In one embodiment of the present application, the second delay module 30 includes a second delay device, the input end of which is used to receive an input signal V pwm The output end of the second delay device is used to be electrically connected to the first driving unit 201.

[0077] Specifically, the second delay device is used to provide a preset time, that is, the input signal Vpwm is delayed by the preset time and then transmitted to the first driving unit 201 , so as to improve the accuracy of the second driving signal Vhg output by the first driving unit 201 .

[0078] The present application also discloses a switching power supply, including the above-mentioned voltage converter. The switching power supply adopts the above-mentioned voltage converter to stabilize the dead time within a preset range, improve the conversion efficiency of the voltage converter, and further improve the reliability of the switching power supply.

[0079] Since the processing and functions implemented by the switching power supply in this embodiment basically correspond to the embodiments, principles and examples of the aforementioned dead time control circuit, for the details not fully described in this embodiment, please refer to the relevant descriptions in the aforementioned embodiments, and no further elaboration will be made here.

[0080] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A dead time control circuit, characterized in that: It includes a sampling module, a comparison module, a counting module and a first delay module; the comparison module is electrically connected to the sampling module and the counting module respectively, the counting module is electrically connected to the first delay module, the sampling module is used to be electrically connected to the gate of the lower switch tube, the drain of the lower switch tube and the source of the upper switch tube respectively, and the first delay module is used to be electrically connected to the driving module; The sampling module is used to generate a sampling trigger signal according to the first driving signal of the gate of the lower switch tube, sample the drain of the lower switch tube when the sampling trigger signal is at a first level, and output the sampling signal; the sampling module is also used to stop sampling the drain of the lower switch tube when the sampling trigger signal is at a second level, and keep outputting the sampling signal; the comparison module is used to output a comparison signal according to the sampling signal and a reference signal when the sampling trigger signal is at the second level; the counting module is used to count according to the comparison signal to obtain a count value; the first delay module is used to determine a delay time according to the count value; the driving module is used to adjust the first driving signal according to the delay time; The comparison module includes a comparator, an enable end of the comparator is electrically connected to the sampling module and is used to receive the sampling trigger signal, a first input end of the comparator is electrically connected to the sampling module, a second input end of the comparator is used to receive the reference signal, and an output end of the comparator is electrically connected to the counting module; The counting module is used to perform an addition count when the comparison signal output by the comparison module is at a high level, and is also used to perform a subtraction count when the comparison signal output by the comparison module is at a low level.

2. The dead time control circuit according to claim 1, characterized in that: The sampling module includes a sample holder, a first input end of the sample holder is electrically connected to the gate of the lower switch tube, a second input end of the sample holder is electrically connected to the drain of the lower switch tube and the source of the upper switch tube respectively, and a first output end and a second output end of the sample holder are both electrically connected to the comparison module.

3. The dead time control circuit according to claim 1, characterized in that: The counting module comprises a counter, an input end of the counter is electrically connected to the comparison module, and an output end of the counter is electrically connected to the first delay module.

4. The dead time control circuit according to claim 1, characterized in that: The first delay module includes a first delay device, a control end of the first delay device is electrically connected to the counting module, an input end of the first delay device is used to receive an input signal, and an output end of the first delay device is used to be electrically connected to the driving module.

5. A voltage converter, characterized in that: It comprises a driving module, an upper switch tube, a lower switch tube and the dead time control circuit according to any one of claims 1 to 4, wherein the driving module is electrically connected to the gate of the upper switch tube, the gate of the lower switch tube and the first delay module in the dead time control circuit respectively, and the source of the upper switch tube is electrically connected to the drain of the lower switch tube and the sampling module in the dead time control circuit respectively; The dead time control circuit is used to determine the delay time, and the driving module is used to adjust the first driving signal according to the delay time.

6. The voltage converter according to claim 5, characterized in that: The driving module comprises a first driving unit and a second driving unit, the first driving unit is electrically connected to the gate of the upper switch tube, and the second driving unit is electrically connected to the gate of the lower switch tube; The first driving unit is used to output the second driving signal to the gate of the upper switch tube, and the second driving unit is used to output the first driving signal to the gate of the lower switch tube.

7. The voltage converter according to claim 6, characterized in that: The voltage converter further includes a second delay module, which is electrically connected to the first driving unit and is used for delaying the input signal for a preset time before transmitting it to the first driving unit.

8. The voltage converter according to claim 7, characterized in that: The second delay module includes a second delay device, an input end of the second delay device is used to receive the input signal, and an output end of the second delay device is used to be electrically connected to the first driving unit.

9. A switching power supply, characterized in that: A voltage converter comprising any one of claims 5 to 8.

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