A unified time system

Abstract

The present invention relates to the technical field of time unification and synchronization, and discloses a time unification system, including a core processing module, a standard frequency module, a satellite signal receiving module, and a transceiver module, wherein the core processing module is electrically connected to the standard frequency module, the satellite signal receiving module, and the transceiver module, respectively. The present invention solves the problems of large error in output time information existing in the prior art.

Description

Technical Field

[0001] The invention relates to the technical field of time unification and synchronization, and in particular to a time unification system. Background Art

[0002] The time unification system is mainly used in aerospace and other fields. In the aerospace field, the synchronous operation of equipment is extremely critical, so the error requirements of the time unification system are extremely high in the aerospace field. However, due to the particularity of the use environment, the environment in which the equipment is used in the aerospace field is extremely complex. Especially when working at high altitudes, the temperature changes are very obvious, and it is very easy to have extreme cold or overheating environments.

[0003] When the ambient temperature changes significantly, the stability of electronic equipment is greatly affected. In particular, devices such as crystal oscillators that provide system reference frequency will change with the change of their own temperature, and the output frequency will also change accordingly. When the system reference frequency changes, the error of the output time information will become larger. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides a time unification system to solve the problem of large error in output time information in the prior art.

[0005] The technical solution adopted by the present invention to solve the above problems is:

[0006] A time unification system comprises a core processing module, a standard frequency module, a satellite signal receiving module and a transceiver module. The core processing module is electrically connected to the standard frequency module, the satellite signal receiving module and the transceiver module respectively.

[0007] As a preferred technical solution, the standard frequency module includes a DAC module electrically connected to each other and a voltage-controlled constant temperature crystal oscillator. The core processing module can control the DAC module to output different voltages, thereby controlling the output frequency of the constant temperature crystal oscillator.

[0008] As a preferred technical solution, the satellite signal receiving module is used to obtain the time information provided by the satellite as a reference standard to correct the local time and the frequency output by the standard frequency module.

[0009] As a preferred technical solution, the satellite signal receiving module includes an antenna and a satellite signal receiving chip. The antenna is electrically connected to the satellite signal receiving chip, and the satellite signal receiving chip is electrically connected to the core processing module.

[0010] As a preferred technical solution, the core processing module includes an FPGA and an ARM electrically connected to each other, the satellite signal receiving chip is electrically connected to the FPGA and the ARM respectively, the constant temperature crystal oscillator is electrically connected to the FPGA, and the ARM is electrically connected to the DAC module and the transceiver module respectively.

[0011] As a preferred technical solution, the FPGA module includes an XC7A35T-2FGG484I chip and an N25Q128A chip. Pin P22 of the FPGA module XC7A35T-2FGG484I chip is connected to the DI port of the N25Q128A chip, pin R22 is connected to the DO port of the N25Q128A chip, pin P21 is connected to the WP port of the N25Q128A chip, pin R21 is connected to the HOLD port of the N25Q128A chip, and pin P22 is connected to the CS port of the N25Q128A chip.

[0012] As a preferred technical solution, the ARM module includes: an STM32F407ZET6 chip and an SX32Y025 chip. The STM32F407ZET6 chip is electrically connected to the satellite receiving module, and the STM32F407ZET6 chip is electrically connected to the SX32Y025 chip.

[0013] As a preferred technical solution, the Ethernet module includes: a KSZ9031RNX chip, a G4 pin of the STM32F407ZET6 chip connected to a CLK125_NDO port of the KSZ9031RNX chip, and a J4 pin of the STM32F407ZET6 chip connected to a XI port of the KSZ9031RNX chip.

[0014] As a preferred technical solution, the constant temperature crystal oscillator module includes: an OCLX oscillator, a first OPA863SIDBVR chip, a second OPA863SIDBVR chip, a SN74AHC1G08DBV chip, capacitors C93, C95, C96, C98, C100, C101, C102, C103, resistors R29, R30, R32, R34, R35, R36, R37, R39, R41, R42, the OCLX oscillator VDD port is connected to a +12V voltage, and capacitors C93 and C96 are connected at the same time; the OUT port is connected in series with capacitor C103, the other end of capacitor C103 is connected to resistors R32 and R37, and is connected to the first OPA863S Pin 3 of the IDBVR chip; Pin 5 of the first OPA863SIDBVR chip is connected to +3.3V, and coupling capacitors C95 and C98 are connected at the same time; Pin 4 of the first OPA863SIDBVR chip is connected to resistor R29, and resistor R30 is connected in series to pin 1; the other end of resistor R30 is connected to port B of the SN74AHC1G08DBV chip, and resistor R41 is connected in series to port Y of the chip. Port A and port VCC are connected to +3.3V voltage, and capacitor C100 is connected at the same time, and resistor R34 is connected in series to port Y; Pin 4 of the second OPA863SIDBVR chip is connected to resistor R35, and resistor R36 is connected in series to pin 1 of the chip. Pin 5 of the chip is connected to +5V, and capacitors C101 and C102 are connected at the same time.

[0015] As a preferred technical solution, the transceiver module includes one or more of the following modules: an Ethernet module, a CAN serial port transceiver module, and an RS232 serial port transceiver module.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention can automatically correct errors of electronic components such as crystal oscillators caused by changes in ambient temperature when the ambient temperature changes, and output a more stable time signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural block diagram of the present invention;

[0019] Figure 2 It is the first part of the circuit structure diagram of the present invention;

[0020] Figure 3 It is the second part of the circuit structure diagram of the present invention;

[0021] Figure 4 It is the third part of the circuit structure diagram of the present invention;

[0022] Figure 5 The fourth part is the circuit structure diagram of the present invention;

[0023] Figure 6 The fifth part of the circuit structure diagram of the present invention;

[0024] Figure 7 The sixth part of the circuit structure diagram of the present invention;

[0025] Figure 8 It is the seventh part of the circuit structure diagram of the present invention;

[0026] Fig. 9 The eighth part of the circuit structure diagram of the present invention;

[0027] Fig.10 It is the ninth part of the circuit structure diagram of the present invention;

[0028] Fig.11 It is the tenth part of the circuit structure diagram of the present invention;

[0029] Fig.12 The eleventh part of the circuit structure diagram of the present invention;

[0030] Fig.13 It is the twelfth part of the circuit structure diagram of the present invention;

[0031] Fig.14 The thirteenth part of the circuit structure diagram of the present invention;

[0032] Fig.15 It is the fourteenth part of the circuit structure diagram of the present invention;

[0033] Fig.16 The fifteenth part of the circuit structure diagram of the present invention;

[0034] Fig.17 The sixteenth part of the circuit structure diagram of the present invention;

[0035] Fig.18 The seventeenth part of the circuit structure diagram of the present invention;

[0036] Fig.19 The eighteenth part of the circuit structure diagram of the present invention;

[0037] Fig. 20 It is the nineteenth part of the circuit structure diagram of the present invention;

[0038] Fig.21 The twentieth part of the circuit structure diagram of the present invention;

[0039] Fig. 22 This is the twenty-first part of the circuit structure diagram of the present invention.

[0040] Fig.23 This is the twenty-second part of the circuit structure diagram of the present invention. DETAILED DESCRIPTION

[0041] The present invention will be further described in detail below in conjunction with embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0042] Example 1

[0043] like Figures 1 to 23 As shown, a time unification system can provide multiple timing signals for other systems, including a core processing module, a standard frequency module, a satellite signal receiving module, an Ethernet module, a CAN serial port transceiver module, and an RS232 serial port transceiver module. After the satellite signal receiving module of this system obtains time information through the satellite, it sends the time information to the ARM module, sends a second pulse signal to the FPGA module, corrects the local time information and standard frequency of this system, interacts with the outside world through the Ethernet module, the CAN serial port transceiver module, and the RS232 serial port transceiver module, and outputs the local time information. The system can receive the time information input by the user through the Ethernet module, the CAN serial port transceiver module, and the RS232 serial port transceiver module to modify the local time information.

[0044] Preferably, the core processing module includes but is not limited to processors such as FPGA and ARM. Various processors are interconnected and interact with each other.

[0045] The local time of the present invention is maintained by the frequency output by the standard frequency module. The standard frequency module includes a DAC module and a constant temperature crystal oscillator. The core processing module can control the DAC module to output different voltages, thereby controlling the output frequency of the constant temperature crystal oscillator. When the ambient temperature changes, the core processing module can adjust the output frequency of the crystal oscillator and correct the frequency. The output of the constant temperature crystal oscillator is connected to the FPGA processor of the core processing module.

[0046] The present invention uses the time information provided by the satellite obtained by the satellite signal receiving module as a reference standard, and sends the time information and the second pulse to the core processing module to correct the local system time and the frequency output by the standard frequency module. The satellite signal receiving module includes an antenna and a satellite signal receiving chip. After the satellite signal receiving module receives the information from the satellite, the time information is transmitted to the ARM module in the core processing module, which decodes the information, obtains the time parameters, and corrects the current local system time in real time. At the same time, the satellite signal receiving module sends an accurate second pulse signal to the FPGA in the core processing module. The FPGA uses the second pulse signal as a reference standard to check whether the frequency output by the standard frequency module is consistent with the theoretical value. If not, the FPGA calculates the deviation and sends the deviation to the ARM, which controls the DAC module to correct the frequency output by the standard frequency module.

[0047] When the present invention can receive satellite signals, the time information output is the time information sent by the satellite. When the present invention loses the satellite signal, the time information output is the local time information.

[0048] Example 2

[0049] This example will describe in detail the operation process of this system.

[0050] After the system is working, under the condition that the satellite signal can be received. After the satellite signal receiving chip UT986 receives the satellite time information through the antenna, it passes the time information to the ARM module. After ARM decodes the information, it obtains the time parameters and corrects the local time of the current system in real time. And ARM sends the decoded time information to the KSZ9031RNX chip, CAN serial port transceiver module, and RS232 serial port transceiver module in the Ethernet module synchronously, and outputs the time information to the outside. The ARM module transmits the local time information to the FPGA module in real time through the FSMC protocol.

[0051] After the satellite signal receiving chip UT986 receives the satellite time information through the antenna and passes the time information to the ARM module, the satellite signal receiving chip UT986 will send a precise second pulse signal to the FPGA module.

[0052] The local time of this system is maintained by the frequency output by the standard frequency module. The constant temperature crystal oscillator in the standard frequency module will output a fixed standard frequency under normal circumstances. The frequency output by the constant temperature crystal oscillator is input into the FPGA module. The FPGA module will use the second pulse signal sent by the satellite signal receiving chip UT986 as a reference standard to verify whether the input frequency is consistent with the theoretical value.

[0053] When the input frequency matches the theoretical value, the FPGA module uses the standard frequency to maintain the local time. The FPGA module will maintain the local time and transmit the local time information to the ARM module in real time through the FSMC protocol.

[0054] When the system works under ultra-high or ultra-low temperature conditions, the standard frequency output by the constant temperature crystal oscillator will have errors, which will cause the frequency output by the constant temperature crystal oscillator to be inconsistent with the theoretical value. The FPGA will calculate the deviation from the theoretical value and send it to the ARM module through the FSMC protocol. The ARM module controls the DAC module AD5663BRMZ chip through the SPI protocol and outputs an electrical signal according to the deviation value. After the electrical signal is input into the OPA863SIDBVR chip for processing, the OPA863SIDBVR chip outputs a voltage value, which is input into the constant temperature crystal oscillator to correct the output frequency. The FPGA module uses the corrected standard frequency to maintain the local time. The FPGA module will maintain the local time in the future and transmit the local time information to the ARM module in real time through the FSMC protocol.

[0055] When the system suddenly loses the satellite signal, the satellite signal receiving chip will not transmit time information to ARM nor send second pulse signals to FPGA. The constant temperature crystal oscillator will output the corrected frequency before the satellite signal is lost. The system maintains the local time through this frequency, and the time information output by the system is the local time information.

[0056] like Figures 1 to 23 As shown, as a further optimization of Example 1, based on Example 1, this embodiment also includes the following technical features:

[0057] FPGA modules include: XC7A35T-2FGG484I chip, N25Q128A chip, OT322550MJBA4SL chip, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C38, C39, C40, C41, C42, C43, C44, C45, C46, ​​C47, C48, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, C61, C62, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72, C73, C74, C75, C76, C77, C78, ​​C79, C80, C81, C82 , C83, C84, C85, C86, C87, C88, C89, C90, C91, C92, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, L6, D2;

[0058] ARM modules include: STM32F407ZET6 chip, SX32Y025 chip, C144, C145, C146, C147, C148, C149, C150, C151, C152, C153, C154, C155, C156, C156, C158, C159, C160, C161, C162, C163, C164, R65, R66, R67, L7;

[0059] Ethernet module includes: KSZ9031RNX chip, HR911130A Ethernet interface, C165, C166, C167, C168, C169, C170, C171, C172, C173, C174, C175, C176, C177, C178, C179, C180, C181, C182, C183, C184, C185, C186, C187, C188, C189, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, L8, L9, L10;

[0060] Satellite signal receiving module includes: UT986 module, FPF2004 power switch, C190, C191, C192, C193, C194, C195, C196, C197, C198, C199, C200, C201, C202, C203, C204, C205, C206, R86, R87, R88, R89, R 90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R10 5. R106, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, L11, L12;

[0061] DAC module includes: AD5663BRMZ chip, C107, C109;

[0062] The constant temperature crystal oscillator module includes: OCLX oscillator, OPA863SIDBVR chip, SN74AHC1G08DBV chip, C93, C95, C96, C98, C100, C101, C102, C103, R29, R30, R32, R34, R35, R36, R37, R39, R41, R42;

[0063] CAN serial port transceiver module includes: SN65VDH230 transceiver, C110, R44; RS232 serial port communication module includes: MAX3232 chip, C116, C118, C120, C122, C123;

[0064] Pin P22 of FPGA module XC7A35T-2FGG484I chip is connected to DI port of N25Q128A chip, pin R22 is connected to DO port of N25Q128A chip, pin P21 is connected to WP port of N25Q128A chip, pin R21 is connected to HOLD port of N25Q128A chip, pin P22 is connected to CS port of N25Q128A chip, pin A13 is connected to U21 A port of SN74AHC1G08DBV chip, pin A14 is connected to U19 A port of SN74AHC1G08DBV chip, pin C18 is connected to Y port of SN74AHC1G08DBV chip, A20 is connected to TIMEPULSE port of UT986 chip, pin T1 is connected to STM3 2F407ZET6 chip PE10 pin, U1 pin connects to STM32F407ZET6 chip PE12 pin, U2 pin connects to STM32F407ZET6 chip PE13 pin, V2 pin connects to STM32F407ZET6 chip PE14 pin, R3 pin connects to STM32F407ZET6 chip PE9 pin, R2 pin connects to STM32F407ZET6 chip PE7 pin, W2 pin connects to STM32F407ZET6 chip PD8 pin, Y2 pin connects to STM32F407ZET6 chip PD10 pin, W1 pin connects to STM32F407ZET6 chip PE15 pin, Y1 pin connects to STM32F407ZET6 chip ET6 chip PD9 pin, AA1 pin connects to STM32F407ZET6 chip PD11 pin, AB1 pin connects to STM32F407ZET6 chip PD14 pin, AB2 pin connects to STM32F407ZET6 chip PD15 pin, AA3 pin connects to STM32F407ZET6 chip PD12 pin, T4 pin connects to STM32F407ZET6 chip PE11 pin, B1 pin connects to STM32F407ZET6 chip PF3 pin, A1 pin connects to STM32F407ZET6 chip PF4 pin, B2 pin connects to STM32F407ZET6 chip PF5 pin, D1 pin connects to STM32F407ZET6 chip 6 chip PF1 pin, E2 pin is connected to STM32F407ZET6 chip PF0 pin, D2 pin is connected to STM32F407ZET6 chip PF2 pin, G1 pin is connected to STM32F407ZET6 chip PG12 pin, K1 pin is connected to STM32F407ZET6 chip G9 pin, J1 pin is connected to STM32F407ZET6 chip PF13 pin, H2 pin is connected to STM32F407ZET6 chip PF12 pin, K2 pin is connected to STM32F407ZET6 chip PD7 pin, J2 pin is connected to STM32F407ZET6 chip PG10 pin, M1 pin is connected to STM32F407ZET6 chip PD4 pin,Pin L1 is connected to the PD6 pin of the STM32F407ZET6 chip, pin M3 is connected to the PD3 pin of the STM32F407ZET6 chip, pin M2 is connected to the PD5 pin of the STM32F407ZET6 chip, pin R1 is connected to the PE8 pin of the STM32F407ZET6 chip, pin P1 is connected to the PD1 pin of the STM32F407ZET6 chip, and pin P2 is connected to the STM32F407ZET6 chip. 7ZET6 chip PD0 pin, V3 pin connects to STM32F407ZET6 chip G4 pin, AB3 pin connects to SN74AHC1G08DBV chip U16 A port, Y3 pin connects to 2X13 port 9, Y4 pin connects to 2X13 port 8, AA4 pin connects to 2X13 port 10, V4 pin connects to STM32F407ZET6 chip G3 pin, R4 pin connects to ST The A8 pin of the M32F407ZET6 chip, the U6 pin is connected to the G2 pin of the STM32F407ZET6 chip, the V5 pin is connected to the G5 pin of the STM32F407ZET6 chip, the Y6 pin is connected to the G6 pin of the STM32F407ZET6 chip, the AA6 pin is connected to the 11th port of the 2X13, the J5 pin is connected to the RXD port of the ADM2582E chip at U23, and the H5 pin is connected to the U20 pin. The RXD port of the ADM2582E chip, the G4 pin is connected to the CLK125_NDO port of the KSZ9031RNX chip, the K4 pin is connected to the 4th pin of the SN74AHC1G08DBV, the J4 pin is connected to the XI port of the KSZ9031RNX chip, the N3 pin is connected to the PG1 pin of the STM32F407ZET6 chip, and the N2 pin is connected to the PG0 pin of the STM32F407ZET6 chip.

[0065] The VCCINT port of the FPGA module XC7A35T-2FGG484I chip is connected to capacitors C29, C30, C31, C32, C33, C34, C35, C36, and C37 in parallel. The upper end of the capacitor is connected to a +1V voltage and the lower end is connected in parallel to DGND. The VCCBRAM port is connected to capacitors C27 and C28 in parallel, with a +1V voltage on the upper end and DGND on the lower end. The VCCAUX port is connected to capacitors C19, C20, C21, C22, C23, C24, C25, and C26 in parallel, with DGND on the lower end and +1.8V voltage on the upper end. At the same time, capacitor C17 is connected in series with the VCCADC_0 port and the VCCBATT_0 port, and the other end of the capacitor is connected to DGND.

[0066] The M1_0 port, VP_0 port, VN_0 port, VREFP_0 port, VREFN_0 port, DXP_0 port, and DXN_0 port of the FPGA module XC7A35T-2FGG484I are connected in parallel to DGND, the CFGBVS_0 port and M0_0 port are connected in parallel to +3.3V, the DONE_0 port is connected to the pull-up resistor R21, the INIT_B_0 port is connected to the pull-up resistor R20, the PROGRAM_B_0 is connected to the pull-up resistor R19, the M2_0 is connected to the pull-up resistor R22, the other end of the resistor is connected to the resistor R23, and the other end of the R23 resistor is connected to DGND.

[0067] The FPGA module XC7A35T-2FGG484I chip VCCO_0 port is connected to parallel capacitors C49 and C50, the capacitors are connected to DGND at the bottom and +3.3V voltage at the top. The VCCO_13 port is connected to +3.3V voltage. The VCCO_14 port is connected to parallel capacitors C68, C69, C70, C71, C72, C73, C74, C75, and C76, the capacitors are connected to DGND at the bottom and +3.3V voltage at the top. The VCCO_15 port is connected to parallel capacitors C85, C86, C87, C88, C89, C90, C91, and C92, the capacitors are connected to DGND at the bottom and +3.3V voltage at the top. +3.3V voltage, VCCO_16 port is connected to parallel capacitors C40, C41, C42, C43, C44, C45, C46, ​​C47, C48, the capacitors are connected to DGND at the bottom and +3.3V voltage at the top, VCCO_34 port is connected to parallel capacitors C60, C61, C62, C63, C64, C65, C66, C67, the capacitors are connected to DGND at the bottom and +3.3V voltage at the top, VCCO_35 port is connected to parallel capacitors C77, C78, ​​C79, C80, C81, C82, C83, C84, the capacitors are connected to DGND at the bottom and +3.3V voltage at the top.

[0068] The CS port of the FPGA module N25Q128A chip is connected to the pull-up resistor R17, the DO port is connected to the pull-up resistor R16, the VCC port is externally connected to +3.3V, the bypass capacitor C38, and the HOLD port is connected to the pull-up resistor R18.

[0069] The VDD port of the FPGA module OT322550MJBA4SL chip is connected to the inductor L6, and the other end of the inductor L6 is connected to +3.3V. The Tri-state port is connected to the resistor R25, and the other end of the resistor R25 is connected to the series capacitor C39. The other end of the capacitor C38 is connected in parallel with the VDD port. The OUTPUT port is connected in series with the resistor R24, and the other end of the resistor R24 ​​is connected to the H4 pin of the FPGA module XC7A35T-2FGG484I chip.

[0070] ARM module STM32F407ZET6 chip PA1 pin is connected to KSZ9031RNX chip RX_CLK port, PA2 pin is connected to KSZ9031RNX chip MDIO port, PA4 pin is connected to AD5663BRMZ chip SYNC# port, PA5 pin is connected to AD5663BRMZ chip SCLK port, PA7 pin is connected to KSZ9031RNX chip RX_DV port, PA9 pin is connected to UT986 chip TXD1 port, PA10 pin is connected to UT986 chip RXD1 port, PA11 pin is connected to SN65VDH230 chip RXD port, PA12 pin is connected to S N65VDH230 chip TXD port, PA13 pin connects to 2X13 pin 17, PA14 pin connects to 2X13 pin 18, PA15 pin connects to 2X13 pin 20, PC0 pin connects to KSZ9031RNX chip RESET_N port, PC1 pin connects to KSZ9031RNX chip MDC port, PC2 pin connects to KSZ9031RNX chip TXD2 port, PC3 pin connects to KSZ9031RNX chip GTX_CLK port, PC4 pin connects to KSZ9031RNX chip RXD0 port, PC5 pin connects to KSZ9031RNX chip RXD1 port, Pin PC6 is connected to DIN2 port of MAX3232 chip, pin PC7 is connected to ROUT2 port of MAX3232 chip, pin PC12 is connected to DIN1 port of MAX3232 chip, pin PB0 is connected to RXD2 port of KSZ9031RNX chip, pin PB1 is connected to RXD3 port of KSZ9031RNX chip, pin PA15 is connected to pin 19 of 2X13, pin PB5 is connected to DIN port of AD5663BRMZ chip, pin PB8 is connected to TXD3 port of KSZ9031RNX chip, pin PB11 is connected to TX_EN port of KSZ9031RNX chip, and pin PB12 is connected to KSZ9031RNX chip. 1RNX chip TXD0 port, PB13 pin is connected to KSZ9031RNX chip TXD1 port, PD2 pin is connected to MAX3232 chip ROUT1 port, PE2 pin is connected to AD5663BRMZ chip LDAC# port, PE3 pin is connected to AD5663BRMZ chip CLR# port, PG7 pin is connected to 2X13 pin 25, PG8 pin is connected to 2X13 pin 26, PH0 and PH1 ports are connected to capacitors C144 and C145 respectively, the other end of the capacitor is connected to DGND, SX32Y025 crystal oscillator is connected between the capacitors, and the crystal oscillator is connected in parallel with resistor R65, and the chip BOOT0 port is connected to DGND.

[0071] The VDDA port and VREF+ port of the ARM module STM32F407ZET6 chip are connected in parallel with capacitors C162 and C163, and then in series with inductor L7. The other end of the capacitor is connected to DGND, and the other end of the inductor is connected to +3.3V.

[0072] The RESET port of the ARM module MAX811 chip is connected to the pull-up resistor R67, the VCC port is connected to the coupling capacitor C164, and the MR is connected to the pull-up resistor R66.

[0073] The DVDDH port of the Ethernet module KSZ9031RNX chip is connected to +3.3V voltage, the DVDDL port is connected to +1.2V voltage, the INT_N port is connected to the pull-up resistor R70, the ISET port is connected to the pull-down resistor R71, the P_GND port, the VSS port, and the NCD1 port are connected to DGND, the MDC port is connected to the pull-up resistor R73, the MDIO port is connected to the pull-up resistor R72, the PHYAD0 port is connected to the LD2_K port of the chip HR911130A through the resistor R68, and then connected to the coupling capacitor C186, the PHYAD1 port is connected to the LD2_A port of the Ethernet interface HR911130A through the resistor R69, and then connected to the coupling capacitor C187, and the TXRXM_D port is connected to the Ethernet interface H The TRD3- port and TXRXP_D port of R911130A are connected to the TRD3+ port of Ethernet interface HR911130A, the TXRXM_C port is connected to the TRD2- port of Ethernet interface HR911130A, the TXRXP_C port is connected to the TRD2+ port of Ethernet interface HR911130A, the TXRXM_B port is connected to the TRD1- port of Ethernet interface HR911130A, the TXRXP_B port is connected to the TRD1+ port of Ethernet interface HR911130A, the TXRXM_A port is connected to the TRD0- port of Ethernet interface HR911130A, and the TXRXP_A port is connected to the TRD0+ port of Ethernet interface HR911130A.

[0074] The LD2_A port and LD1_A port of the Ethernet interface HR911130A are connected to +3.3V, the M2 and M1 ports are connected to DGND, the CT port is connected to coupling capacitors C188 and C189, the E1_125M_CLK port is connected to a pull-up resistor R74, the E1_125M_CLK port is connected to a pull-up resistor R74, the MII_RXDV port is connected to a pull-up resistor R75, the MII_RXD3 port, the MII_RXD2 port, the MII_RXD1 port, and the MII_RXD0 port are connected to pull-up resistors R76, R77, R78, and R79 respectively, the PHY1_AD0 / LED1 port of the Ethernet interface HR911130A is connected to a pull-up resistor R80, and the MII_RXC port and the PHY1_AD0 / LED2 port are connected to pull-down resistors R81 and R82 respectively.

[0075] The VIN port of the FPF2004 chip in the satellite signal receiving module is connected to a pull-up resistor R86, and is also connected to coupling capacitors C192 and C193. The ON port is connected to a pull-up resistor R89, the FLAGB port is connected to a pull-up resistor R88, the VOUT port is connected to a coupling capacitor C190, and is also connected in parallel with a resistor R87. The other end of the resistor is connected in series with a diode D13 and is connected to a pull-up resistor R84. The other end of the diode is connected to coupling capacitors C194 and C195. TVS diode D15 is connected in parallel at both ends of the coupling capacitor. The anode of the parallel coupling resistor is connected to inductor L11 and resistor R85 in parallel. At the same time, the other end of R85 is connected in series with resistor R83, the other end of inductor L11 is connected in series with inductor L12, and the other end of inductor L12 is connected in parallel with capacitor C191, ESD diode D14 and SMA female connector P7.

[0076] The VCC port of the satellite timing module UT986 chip is connected to the pull-up resistor R92, and the coupling resistors C196, C197, C198, C199, and C200 are connected at the same time. The TVS diode D19 and the ESD diode D18 are connected in parallel at both ends of the capacitor. The TIME PULSE port is connected to an external resistor R90, and the RSV port is connected to an external resistor R94.

[0077] The VDD port of the constant temperature crystal oscillator module OCLX oscillator (SOXO13BF10MASGS) is connected to +12V voltage, and coupling capacitors C93 and C96 are connected at the same time. The OUT port is connected in series with capacitor C103. At the same time, the other end of capacitor C103 is connected to pull-up resistor R32 and pull-down resistor R37, and connected to pin 3 of U10 OPA863SIDBVR chip. Pin 5 of the chip is connected to +3.3V, and coupling capacitors C95 and C98 are connected at the same time. Pin 4 of the chip is connected to pull-down resistor R29, and resistor R30 is connected in series to pin 1. The other end of resistor R30 is connected to port B of the SN74AHC1G08DBV chip, and resistor R41 is connected in series to port Y of the chip. Port A and VCC are connected to +3.3V voltage, and coupling capacitor C100 is connected at the same time. Resistor R34 is connected in series to port Y.

[0078] Pin 4 of the constant temperature crystal oscillator module U12 OPA863SIDBVR chip is connected to the pull-down resistor R35, and the series resistor R36 is connected to the chip pin 1. The chip pin 5 is connected to +5V, and the coupling capacitors C101 and C102 are connected at the same time.

[0079] The VREF port of the DAC module AD5663BRMZ chip is connected to the coupling capacitor C109, the VDD port is connected to VREF50, and the coupling capacitor C107 is also connected.

[0080] A capacitor C110 is connected between the VCC port and the GND port of the CAN serial port transceiver module SN65VDH230 chip, and a resistor R44 is connected between the CANH port and the CANL port.

[0081] The V- port of the RS232 serial communication module MAX3232 chip is connected to a coupling capacitor C123, a capacitor C122 is connected in series between the C2+ port and the C2- port, a capacitor C120 is connected in series between the C1+ port and the C1- port, a capacitor C118 is connected to the V+ port, a +3.3V voltage is connected to the VDD port, and a coupling capacitor C116 is connected at the same time.

[0082] As described above, the present invention can be preferably implemented.

[0083] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0084] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. According to the technical essence of the present invention, within the spirit and principles of the present invention, any simple modification, equivalent replacement and improvement made to the above embodiment still falls within the protection scope of the technical solution of the present invention.

Claims

1. A time unified system, characterized in that: It includes a core processing module, a standard frequency module, a satellite signal receiving module, and a transceiver module, wherein the core processing module is electrically connected to the standard frequency module, the satellite signal receiving module, and the transceiver module respectively; The standard frequency module includes a DAC module electrically connected to each other and a voltage-controlled constant temperature crystal oscillator. The core processing module can control the DAC module to output different voltages, thereby controlling the output frequency of the constant temperature crystal oscillator. The satellite signal receiving module is used to obtain the time information provided by the satellite as a reference standard to correct the local time and the frequency output by the standard frequency module; The satellite signal receiving module includes an antenna and a satellite signal receiving chip, the antenna is electrically connected to the satellite signal receiving chip, and the satellite signal receiving chip is electrically connected to the core processing module; The core processing module includes an FPGA and an ARM electrically connected to each other, a satellite signal receiving chip electrically connected to the FPGA and the ARM respectively, a constant temperature crystal oscillator electrically connected to the FPGA, and the ARM electrically connected to the DAC module and the transceiver module respectively; The FPGA module includes an XC7A35T-2FGG484I chip and an N25Q128A chip. The P22 pin of the XC7A35T-2FGG484I chip of the FPGA module is connected to the DI port of the N25Q128A chip, the R22 pin is connected to the DO port of the N25Q128A chip, the P21 pin is connected to the WP port of the N25Q128A chip, the R21 pin is connected to the HOLD port of the N25Q128A chip, and the P22 pin is connected to the CS port of the N25Q128A chip. The ARM module includes: an STM32F407ZET6 chip and an SX32Y025 chip. The STM32F407ZET6 chip is electrically connected to the satellite receiving module, and the STM32F407ZET6 chip is electrically connected to the SX32Y025 chip. The Ethernet module includes: KSZ9031RNX chip, the G4 pin of the STM32F407ZET6 chip is connected to the CLK125_NDO port of the KSZ9031RNX chip, and the J4 pin of the STM32F407ZET6 chip is connected to the XI port of the KSZ9031RNX chip; The constant temperature crystal oscillator module includes: an OCLX oscillator, a first OPA863SIDBVR chip, a second OPA863SIDBVR chip, a SN74AHC1G08DBV chip, capacitors C93, C95, C96, C98, C100, C101, C102, C103, resistors R29, R30, R32, R34, R35, R36, R37, R39, R41, R42, the OCLX oscillator VDD port is connected to a +12V voltage, and capacitors C93 and C96 are connected at the same time; the OUT port is connected in series with a capacitor C103, the other end of the capacitor C103 is connected to resistors R32 and R37, and is connected to the first OPA863SIDBVR chip Pin 3 of the chip; Pin 5 of the first OPA863SIDBVR chip is connected to +3.3V, and coupling capacitors C95 and C98 are connected at the same time; Pin 4 of the first OPA863SIDBVR chip is connected to resistor R29, and resistor R30 is connected in series to pin 1; The other end of resistor R30 is connected to port B of the SN74AHC1G08DBV chip, and resistor R41 is connected in series to port Y of the chip. Port A and VCC are connected to +3.3V voltage, and capacitor C100 is connected at the same time, and resistor R34 is connected in series to port Y; Pin 4 of the second OPA863SIDBVR chip is connected to resistor R35, and resistor R36 is connected in series to pin 1 of the chip. Pin 5 of the chip is connected to +5V, and capacitors C101 and C102 are connected at the same time; The DAC module includes an AD5663BRMZ chip, pins 1 and 2 of the AD5663BRMZ chip are respectively connected to pin 3 of the second OPA863SIDBVR chip, and pin K4 of the XC7A35T-2FGG484I chip is connected to resistor R34.

2. A time unification system according to claim 1, characterized in that: The transceiver module includes one or more of the following modules: Ethernet module, CAN serial port transceiver module, RS232 serial port transceiver module.

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