A method for manufacturing a satellite navigation three-dimensional chip

Abstract

The present invention provides a method for manufacturing a satellite navigation three-dimensional chip, and relates to the field of three-dimensional chip manufacturing. The method is based on a method for manufacturing a satellite navigation three-dimensional chip, and includes: S1. First, three-dimensional structure design is performed using professional design software, and the optimization of electrical performance, thermal management and physical size is considered. Silicon via technology is used to achieve vertical integration between chip layers to ensure rapid signal transmission and high-density integration. At the same time, graphene and carbon nanotube composite materials are selected to prepare high thermal conductivity nanomaterials for use as thermal interface materials. By using professional design software for three-dimensional structure design and using silicon via technology to achieve vertical integration between chip layers, this solution can ensure rapid signal transmission and high-density integration, and graphene and carbon nanotube composite materials are selected as thermal interface materials. Combined with a carefully designed heat diffusion layer layout and micro-cooling channels, the thermal management efficiency of the chip is significantly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional chip manufacturing, and in particular to a method for manufacturing a satellite navigation three-dimensional chip. Background Art

[0002] The manufacturing method and characteristics of the satellite navigation chip ZMX2301A can be summarized as follows: Packaging process: ZMX2301A uses a single-chip packaging process and adopts a 7mmx7mmLGA-28 packaging format. This packaging method is suitable for GPS / Beidou single-chip applications, providing compact size and good performance. Integrated design: The chip integrates all the necessary chips required for the GPS / Beidou receiver, including GPS / Beidou RF and baseband, 0.5ppm temperature compensated oscillator, regulator and passive components. This integrated design simplifies external hardware requirements, and users only need to connect the antenna and power supply to start using it. Temperature curve: During the manufacturing process, the chip is recommended to be processed using a specific temperature curve to ensure good performance and reliability. For lead-free and SnPb processes, there are clear preheating, ramping, reflow and cooling steps to ensure the quality of the chip during the production process.

[0003] The defects or challenges are as follows: High integration: Although high integration can reduce the demand for external components, it also increases the internal heat generation. If the thermal management design is not appropriate, it may affect the performance and life of the chip. Packaging limitations: The use of specific packaging formats (such as 7mmx7mmLGA-28) may limit the flexibility of chip design, especially when trying to introduce new features or improve existing features. Production process complexity: High-precision temperature control and complex production process requirements may increase production costs and complexity, especially in large-scale production. Environmental adaptability: For applications with high requirements for temperature compensation and stability, the chip needs to maintain high performance under a wide range of environmental conditions, which may pose additional challenges to design and testing. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a satellite navigation three-dimensional chip, which solves the problems of high requirements for temperature compensation and stability and the use of a specific packaging format that limits the flexibility of chip design.

[0006] (II) Technical solution

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions: A method for manufacturing a satellite navigation three-dimensional chip, comprising:

[0008] S1. First, use professional design software to design the three-dimensional structure, consider the optimization of electrical performance, thermal management and physical size, use silicon via technology to achieve vertical integration between chip layers, ensure fast signal transmission and high-density integration, and at the same time, use graphene and carbon nanotube composite materials to prepare high thermal conductivity nanomaterials, which are used as thermal interface materials to optimize the heat conduction path and improve thermal management efficiency;

[0009] S2. The layout of the heat diffusion layer is specially considered in the design to ensure that the heat can be evenly distributed and effectively transferred to the cooling channel or chip surface to avoid the generation of hot spots.

[0010] S3, adopts new hybrid material packaging technology, combines high thermal conductivity nanomaterials with traditional packaging materials, and introduces scalable interconnection structure to adapt to different circuit designs and thermal diffusion requirements;

[0011] S4, using laser direct writing lithography technology and electrochemical deposition process to precisely manufacture micro cooling channels, which process includes selecting appropriate lithography masks, adjusting laser parameters and electrochemical deposition parameters to form cooling channels with precise dimensions and optimized layout;

[0012] S5. Develop a power management strategy based on environmental perception, using environmental sensors such as temperature and humidity to collect ambient data, combined with the workload information inside the chip, and determine the optimal power consumption state through machine learning model analysis;

[0013] S6, integrated adaptive frequency adjustment technology, dynamically adjusts the processor's operating frequency according to the real-time monitored chip temperature and load conditions, and uses high-precision temperature sensors and signal processing algorithms to ensure fast and accurate frequency adjustment response;

[0014] S7. Utilize multi-layer mixed signal integration technology to effectively isolate analog, digital and RF modules through specially made isolation layer materials to reduce mutual interference. Special consideration is given to layout optimization of signal paths and isolation layers during design.

[0015] S8. Integrate smart materials containing microcapsules into key structures to achieve a self-healing mechanism. The repair agent contained in the microcapsules can be automatically released when microcracks appear in the material, repair the damage through chemical reactions, and enhance the long-term reliability of the chip. Carry out detailed experiments to verify the distribution uniformity of the microcapsules, the repair efficiency, and the impact on chip performance;

[0016] S9. Implement environmentally friendly production processes, optimize the selection and use of chemical reagents, introduce energy recovery and waste treatment systems, ensure the environmental friendliness of the production process, monitor data on the production line in real time, use data-driven methods to identify production bottlenecks and efficiency improvement opportunities, and apply artificial intelligence algorithms to optimize production processes, improve production efficiency and reduce costs;

[0017] S10. Design and implement a comprehensive performance and reliability testing program, including but not limited to environmental testing, mechanical testing, and long-term stability testing, to ensure the performance and stability of the chip under various extreme conditions, conduct root cause analysis on problems found during the testing process, and provide feedback to the design and manufacturing process for optimization.

[0018] Preferably, the laser parameters include power, focal length and scanning speed, and the electrochemical deposition parameters include electrolyte concentration and current density.

[0019] Preferably, the isolation layer material is a high dielectric constant material, the environmental test is a high and low temperature test, a humidity test and a salt spray test, and the mechanical test is a vibration and impact test.

[0020] Preferably, the novel hybrid material packaging technology includes using epoxy resin combined with graphene sheets and carbon nanotubes in a specific ratio of 2:3.

[0021] Preferably, the machine learning model is a deep neural network trained through a training data set, and the data set training model includes steps such as feature selection, model parameter tuning and cross-validation to ensure the accuracy and generalization ability of the prediction, and the data set includes historical data of temperature, humidity, workload and power consumption status.

[0022] Preferably, the high-precision temperature sensor adopts a high-precision temperature sensor based on micro-electromechanical system technology, and the signal processing algorithm includes steps such as filtering, denoising and temperature compensation. A digital signal processor is used to realize real-time data processing to ensure the accuracy and reliability of temperature data.

[0023] Preferably, the layout of the isolation layer is optimized by using a material with a high dielectric constant and low loss, such as aluminum oxide or silicon nitride, to effectively isolate electromagnetic interference between different functional modules.

[0024] Preferably, the experimental verification of the uniformity of microcapsule distribution, repair efficiency and impact on chip performance includes scanning electron microscopy analysis, energy dispersive X-ray spectroscopy analysis and mechanical property testing to verify the uniform distribution of microcapsules in smart materials, the repair efficiency under different stress conditions, and the impact of the self-repair mechanism on the electrical performance of the chip.

[0025] (III) Beneficial effects

[0026] The present invention provides a method for manufacturing a satellite navigation three-dimensional chip. It has the following beneficial effects:

[0027] By using professional design software for three-dimensional structure design and adopting silicon via technology to achieve vertical integration between chip layers, this solution can ensure fast signal transmission and high-density integration. Graphene and carbon nanotube composite materials are selected as thermal interface materials, combined with carefully designed heat diffusion layer layout and micro cooling channels, which significantly improves the thermal management efficiency of the chip. The new hybrid material packaging technology is used, combined with high thermal conductivity nanomaterials and traditional packaging materials, and a retractable interconnect structure is introduced, which not only improves the thermal conductivity of the package, but also increases the adaptability of circuit design and heat diffusion requirements, thereby improving the overall packaging performance and reliability. The integration of power management strategy based on environmental perception and adaptive frequency adjustment technology enables the chip to dynamically adjust power consumption and processor frequency according to real-time temperature and load conditions. The application of multi-layer mixed signal integration technology and special isolation layer materials effectively isolates the interference between analog, digital and radio frequency modules, optimizes the signal path and isolation layer layout, thereby improving the signal processing capability and overall performance of the chip. When microcracks appear, the microcapsule can automatically release the repair agent for chemical reaction repair. Detailed experimental verification proves the positive impact of this mechanism on chip performance. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] An embodiment of the present invention provides a method for manufacturing a satellite navigation three-dimensional chip, including: S1. First, use professional design software to design a three-dimensional structure, consider the optimization of electrical performance, thermal management and physical size, use silicon via technology to achieve vertical integration between chip layers, ensure fast signal transmission and high-density integration, and at the same time, select graphene and carbon nanotube composite materials to prepare high thermal conductivity nanomaterials, which are used as thermal interface materials to optimize the heat conduction path and improve thermal management efficiency.

[0030] S2. The layout of the heat diffusion layer is specially considered in the design to ensure that the heat can be evenly distributed and effectively transferred to the cooling channel or chip surface to avoid the generation of hot spots.

[0031] S3. A new hybrid material packaging technology is used, which combines high thermal conductivity nanomaterials with traditional packaging materials, and introduces a scalable interconnect structure to adapt to different circuit designs and thermal diffusion requirements. The new hybrid material packaging technology includes the use of epoxy resin combined with graphene sheets and carbon nanotubes in a specific ratio of 2:3.

[0032] S4. Use laser direct writing lithography technology and electrochemical deposition process to precisely manufacture micro cooling channels. The process includes selecting appropriate lithography masks, adjusting laser parameters and electrochemical deposition parameters to form cooling channels with precise dimensions and optimized layout. Laser parameters include power, focal length and scanning speed, and electrochemical deposition parameters are electrolyte concentration and current density.

[0033] S5. Develop a power management strategy based on environmental perception. Use environmental sensors such as temperature and humidity to collect ambient data. Combined with the workload information inside the chip, determine the optimal power consumption state through machine learning model analysis. The data set training model includes feature selection, model parameter tuning, and cross-validation steps to ensure the accuracy and generalization ability of the prediction. The data set includes historical data on temperature, humidity, workload, and power consumption state.

[0034] S6, integrated adaptive frequency adjustment technology, dynamically adjusts the processor's operating frequency according to the real-time monitored chip temperature and load conditions, uses high-precision temperature sensors and signal processing algorithms to ensure fast and accurate frequency regulation response. The signal processing algorithm includes filtering, denoising and temperature compensation steps, and uses a digital signal processor to achieve real-time data processing to ensure the accuracy and reliability of temperature data.

[0035] S7. Multi-layer mixed signal integration technology is used to effectively isolate analog, digital and RF modules through special isolation layer materials to reduce mutual interference. Special consideration is given to the layout optimization of signal paths and isolation layers during design. The isolation layer material is a high dielectric constant material. Environmental tests include high and low temperature tests, humidity tests and salt spray tests. Mechanical tests include vibration and impact tests. The layout optimization of the isolation layer uses materials with high dielectric constants and low losses, such as aluminum oxide or silicon nitride, to effectively isolate electromagnetic interference between different functional modules.

[0036] S8. Integrate smart materials containing microcapsules into key structures to achieve a self-repair mechanism. The repair agent contained in the microcapsules can be automatically released when microcracks appear in the material, repair damage through chemical reactions, and enhance the long-term reliability of the chip. Carry out detailed experiments to verify the uniformity of microcapsule distribution, repair efficiency, and impact on chip performance. The experimental verification of microcapsule distribution uniformity, repair efficiency, and impact on chip performance includes scanning electron microscopy analysis, energy dispersive X-ray spectroscopy analysis, and mechanical property testing to verify the uniform distribution of microcapsules in smart materials, the repair efficiency under different stress conditions, and the impact of the self-repair mechanism on the electrical performance of the chip.

[0037] S9. Implement environmentally friendly production processes, optimize the selection and use of chemical reagents, introduce energy recovery and waste treatment systems, ensure the environmental friendliness of the production process, monitor data on the production line in real time, use data-driven methods to identify production bottlenecks and efficiency improvement opportunities, and apply artificial intelligence algorithms to optimize production processes, improve production efficiency and reduce costs.

[0038] S10. Design and implement a comprehensive performance and reliability testing program, including but not limited to environmental testing, mechanical testing, and long-term stability testing, to ensure the performance and stability of the chip under various extreme conditions, conduct root cause analysis on problems found during the testing process, and provide feedback to the design and manufacturing process for optimization.

[0039] Table 1: Data comparison table

[0040]

[0041] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a satellite navigation three-dimensional chip, characterized in that: include: S1. First, use professional design software to design the three-dimensional structure, consider the optimization of electrical performance, thermal management and physical size, use silicon via technology to achieve vertical integration between chip layers, ensure fast signal transmission and high-density integration, and at the same time, use graphene and carbon nanotube composite materials to prepare high thermal conductivity nanomaterials, which are used as thermal interface materials to optimize the heat conduction path and improve thermal management efficiency; S2. Consider the layout of the heat diffusion layer in the design to ensure that the heat is evenly distributed and effectively conducted to the cooling channel or chip surface to avoid hot spots; S3, adopts new hybrid material packaging technology, combines high thermal conductivity nanomaterials with traditional packaging materials, and introduces scalable interconnection structure to adapt to different circuit designs and thermal diffusion requirements; S4, using laser direct writing lithography technology and electrochemical deposition process to precisely manufacture micro cooling channels, which process includes selecting appropriate lithography masks, adjusting laser parameters and electrochemical deposition parameters to form cooling channels with precise dimensions and optimized layout; S5. Develop a power management strategy based on environmental perception, use temperature and humidity environmental sensors to collect ambient data, combine it with the workload information inside the chip, and determine the optimal power consumption state through machine learning model analysis; S6, integrated adaptive frequency adjustment technology, dynamically adjusts the processor's operating frequency according to the real-time monitored chip temperature and load conditions, and uses high-precision temperature sensors and signal processing algorithms to ensure fast and accurate frequency adjustment response; S7. Use multi-layer mixed signal integration technology to effectively isolate analog, digital and RF modules through special isolation layer materials to reduce mutual interference. Consider the layout optimization of signal paths and isolation layers during design. S8. Integrate smart materials containing microcapsules into key structures to achieve a self-healing mechanism. The repair agent contained in the microcapsules can be automatically released when microcracks appear in the material, repair the damage through chemical reactions, and enhance the long-term reliability of the chip. Carry out detailed experiments to verify the distribution uniformity of the microcapsules, the repair efficiency, and the impact on chip performance; S9. Implement environmentally friendly production processes, optimize the selection and use of chemical reagents, introduce energy recovery and waste treatment systems, ensure the environmental friendliness of the production process, monitor data on the production line in real time, use data-driven methods to identify production bottlenecks and efficiency improvement opportunities, and apply artificial intelligence algorithms to optimize production processes, improve production efficiency and reduce costs; S10. Design and implement a comprehensive performance and reliability test program, including environmental testing, mechanical testing, and long-term stability testing, to ensure the performance and stability of the chip under various extreme conditions, conduct root cause analysis on problems found during the test, and provide feedback to the design and manufacturing process for optimization.

2. The method for manufacturing a satellite navigation three-dimensional chip according to claim 1, characterized in that: The laser parameters include power, focal length and scanning speed, and the electrochemical deposition parameters include electrolyte concentration and current density.

3. The method for manufacturing a satellite navigation three-dimensional chip according to claim 1, characterized in that: The isolation layer material is a high dielectric constant material, the environmental test is a high and low temperature test, a humidity test and a salt spray test, and the mechanical test is a vibration and impact test.

4. The method for manufacturing a satellite navigation three-dimensional chip according to claim 1, characterized in that: The machine learning model is a deep neural network trained by a training data set, and the data set training model includes feature selection, model parameter tuning and cross-validation steps to ensure the accuracy and generalization ability of the prediction. The data set includes historical data of temperature, humidity, workload and power consumption status.

5. The method for manufacturing a satellite navigation three-dimensional chip according to claim 1, characterized in that: The high-precision temperature sensor adopts a high-precision temperature sensor based on micro-electromechanical system technology. The signal processing algorithm includes filtering, denoising and temperature compensation steps, and uses a digital signal processor to achieve real-time data processing to ensure the accuracy and reliability of temperature data.

6. The method for manufacturing a satellite navigation three-dimensional chip according to claim 1, characterized in that: The layout of the isolation layer is optimized by using materials with high dielectric constant and low loss, such as aluminum oxide or silicon nitride, which effectively isolates electromagnetic interference between different functional modules.

7. The method for manufacturing a satellite navigation three-dimensional chip according to claim 1, characterized in that: The experimental verification of the uniformity of microcapsule distribution, repair efficiency and chip performance impact includes scanning electron microscopy analysis, energy dispersive X-ray spectroscopy analysis and mechanical property testing to verify the uniform distribution of microcapsules in smart materials, the repair efficiency under different stress conditions, and the impact of the self-repair mechanism on the electrical performance of the chip.

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