A non-volatile semiconductor memory device having both RAM operation and NVM characteristics

Abstract

The present application provides a non-volatile semiconductor memory device with RAM operation and NVM features, including: a memory cell composed of 10 semiconductor elements, the memory cell includes an SRAM memory cell part composed of 6 semiconductor elements and a non-volatile memory part composed of 4 semiconductor elements; wherein the non-volatile memory part includes two groups of dual elements, each group of dual elements includes a non-volatile memory cell transistor and an N-type channel transistor or a P-type channel transistor connected in series, and each transistor of the dual element is connected to the SRAM memory cell part; the non-volatile memory cell transistor is a P-type channel transistor, and a charge storage layer including an insulating layer is provided above the channel region of the non-volatile memory cell transistor, and an insulating layer and a gate are stacked in sequence above the charge storage layer; the two groups of dual elements are respectively connected to the positive storage node and the negative storage node of the SRAM memory cell part. It is at least beneficial to reduce the manufacturing cost and improve the integration density of the memory cell.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more particularly to a non-volatile semiconductor memory device having RAM operation and NVM characteristics. Background Art

[0002] As shown in the Nikkei Technology Online Special (March, 2014), Static Random Access Memory (SRAM) enables high-speed random access and low power consumption, and its application areas are very wide, as shown in the following examples, including network work equipment, communication infrastructure equipment, measuring instruments, imaging systems, as well as industrial equipment and game consoles. If necessary, battery backup SRAM can also be used to maintain the data in the SRAM with an additional battery after the system is turned off. However, in this case, the data retention time of the SRAM is limited to about three years due to battery aging.

[0003] Currently, non-volatile SRAM (nvSRAM) operated by random access memory (RAM) has been applied to smart meters, programmable logic controllers (PLC), factory automation (FA) equipment, information technology (IT) equipment, office automation (OA) equipment, automobiles and wearable devices, with memory capacity up to 16Mbit. In the systems of the above devices, the nvSRAM can operate in the same way as traditional SRAM through standard SRAM control signals and control timing.

[0004] When the power is turned off or a power outage occurs, the nvSRAM chip can detect the drop in power supply voltage and store the data in the SRAM cell in the chip to the non-volatile memory (called a storage operation). In addition, when the power is turned on or recovered from a power outage, the data in the non-volatile memory of the nvSRAM chip can be returned to the SRAM storage cell (called a read-back operation), so that the host system can use the data saved in the non-volatile memory during the power outage interruption. The advantage of this is that the non-volatile data recovery process can be used after the power is turned on, but the performance of the current non-volatile static memory needs to be improved. Summary of the invention

[0005] The embodiments of the present application provide a non-volatile semiconductor memory device having RAM operation and NVM characteristics, which is at least beneficial to reducing manufacturing costs and improving the integration density of memory cells.

[0006] On the one hand, an embodiment of the present application provides a non-volatile semiconductor memory device with RAM operation and NVM features, characterized in that volatile RAM operation and non-volatile RAM data storage can be performed, and the non-volatile semiconductor memory device includes: a memory cell composed of 10 semiconductor elements, the memory cell includes an SRAM memory cell part composed of 6 semiconductor elements and a non-volatile memory part composed of 4 semiconductor elements; wherein the non-volatile memory part includes two groups of dual elements, each group of dual elements includes a non-volatile memory cell transistor and an N-type channel transistor connected in series, and each transistor in the dual elements is connected to the SRAM memory cell part; the non-volatile memory cell transistor is a P-type channel transistor, and a charge storage layer including an insulating layer is provided above the channel region of the non-volatile memory cell transistor, and an insulating layer and a gate are stacked in sequence above the charge storage layer; the two groups of dual elements are respectively connected to the positive storage node and the negative storage node of the SRAM memory cell part.

[0007] In some embodiments, the threshold voltage Vth of the nonvolatile memory cell transistor is a positive voltage in a programmed state, and the threshold voltage Vth of the nonvolatile memory cell transistor is a negative voltage in an erased state.

[0008] In some embodiments, the charge storage layer includes an insulating layer and a first floating gate stacked in sequence, and an insulating layer and a second control gate are stacked in sequence above the first floating gate; the six semiconductor elements of the SRAM storage unit part are six element transistors, and the six element transistors and the channel region of the N-type channel transistor of the non-volatile memory part all have an insulating layer and a second floating gate stacked in sequence above the channel region, and a second control gate is provided above the second floating gate, and the second floating gate and the second control gate are electrically connected to each other.

[0009] In some embodiments, in the SRAM storage cell portion, one N-type well is used to set two P-type channel transistors, one P-type well is used to set two N-type channel transistors, and the two P-type wells are respectively located on both sides of one N-type well; in the non-volatile memory portion, one P-type well is used to set one N-type channel transistor, one N-type well is used to set one non-volatile storage cell transistor, the two P-type wells of the non-volatile memory portion are respectively located on the side of the two P-type wells of the SRAM storage cell away from the N-type well, and the two N-type wells of the non-volatile memory portion are respectively located on the side of the two P-type wells of the non-volatile memory portion away from the SRAM storage cell portion.

[0010] On the other hand, an embodiment of the present application provides a non-volatile semiconductor memory device having RAM operation and NVM features, characterized in that volatile RAM operation and non-volatile RAM data storage can be performed, and the non-volatile semiconductor memory device includes:

[0011] A memory cell composed of 10 semiconductor elements, the memory cell including an SRAM memory cell portion composed of 6 semiconductor elements and a non-volatile memory portion composed of 4 semiconductor elements;

[0012] The nonvolatile memory portion includes two groups of dual elements, each group of dual elements includes a nonvolatile memory cell transistor and a P-type channel transistor connected in series, and each transistor of the dual elements is connected to the SRAM memory cell portion;

[0013] The non-volatile memory cell transistor is a P-type channel transistor, a charge storage layer including an insulating layer is provided above the channel region of the non-volatile memory cell transistor, and an insulating layer and a gate are sequentially stacked above the charge storage layer;

[0014] The two sets of dual elements are respectively connected to the positive storage node and the negative storage node of the SRAM storage cell portion.

[0015] In some embodiments, the threshold voltage Vth of the nonvolatile memory cell transistor is a negative voltage in both a programmed state and an erased state.

[0016] In some embodiments, the charge storage layer includes an insulating layer and a first floating gate stacked in sequence, and an insulating layer and a second control gate are stacked in sequence above the first floating gate; the six semiconductor elements of the SRAM storage unit part are six element transistors, and the six element transistors and the channel region of the P-type channel transistor of the non-volatile memory part all have an insulating layer and a second floating gate stacked in sequence above the channel region, and a second control gate is provided above the second floating gate, and the second floating gate and the second control gate are electrically connected to each other.

[0017] In some embodiments, in the SRAM memory cell portion, an N-type well is used to set two P-type channel transistors, and a P-type well is used to set two N-type channel transistors, and the two P-type wells are respectively located on both sides of an N-type well; in the non-volatile memory portion, an N-type well is used to set a non-volatile memory cell transistor and a P-type channel transistor, and the two N-type wells of the non-volatile memory portion are respectively located on the side of the two P-type wells of the SRAM memory cell away from the N-type well.

[0018] The technical solution provided by the embodiment of the present application has at least the following advantages: In the embodiment of the present application, in the memory cell of the non-volatile semiconductor memory device, the non-volatile memory portion is not composed of 6 elements including 2 non-volatile memory cell transistors, but is composed of 4 elements including 2 non-volatile memory cell transistor elements, the memory cell of the non-volatile semiconductor memory device includes 10 elements, and the non-volatile memory cell transistor is a P-type channel transistor with a floating gate and a charge storage layer. In addition, the non-volatile memory portion is composed of two groups of dual elements, each group of dual elements includes a non-volatile memory cell transistor and an N-type channel transistor, or includes a non-volatile memory cell transistor and a P-type channel transistor, and the volatile memory cell transistor is a P-type channel transistor with a floating gate or a charge storage layer.

[0019] Thus, in the memory cell of the nonvolatile semiconductor memory device, the nonvolatile memory portion is a structure composed of four elements including two nonvolatile memory cell transistors. Since the number of elements in the memory cell is 10, greater integration can be achieved using existing manufacturing technology. In addition, since the nonvolatile memory cell transistor is composed of a P-type channel transistor, the nonvolatile memory portion in the nonvolatile semiconductor memory device can achieve a larger storage capacity and a longer data retention time at a higher temperature. In addition, in the memory cell of the nonvolatile semiconductor memory device, when the nonvolatile memory portion includes a nonvolatile memory cell transistor that is a P-type channel transistor and an N-type channel transistor, the threshold voltage Vth of the nonvolatile memory cell transistor is negative in the erase state and positive in the programming state. Thus, the erase state and the programming state can be identified by adding VccS to the gate of the nonvolatile memory cell transistor, depending on whether the nonvolatile memory cell transistor is in the off state or the on state. When the nonvolatile memory cell transistor is a P-channel transistor and other transistors of the nonvolatile memory portion are also P-channel transistors, the area increase phenomenon caused by well division can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 An equivalent circuit diagram of a memory cell structure of a non-volatile semiconductor memory device having RAM operation and NVM characteristics provided for related technology;

[0022] Figure 2 An operation timing diagram of a memory cell of a non-volatile semiconductor memory device having RAM operation and NVM characteristics is provided for the related art;

[0023] Figure 3 A schematic diagram of a threshold voltage Vth state of a memory cell of a non-volatile semiconductor memory device having RAM operation and NVM characteristics provided in the related art;

[0024] Figure 4 An equivalent circuit diagram of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0025] Figure 5 A schematic diagram of a threshold voltage Vth state of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0026] Figure 6 An operation timing diagram of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0027] Figure 7 A cross-sectional view of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0028] Figure 8 Another cross-sectional view of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM features provided by an embodiment of the present application;

[0029] Fig. 9 Another cross-sectional view of a memory cell of the first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0030] Fig.10 An equivalent circuit diagram of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0031] Fig.11 A schematic diagram of a threshold voltage Vth state of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0032] Fig.12 An operation timing diagram of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0033] Fig.13 A cross-sectional view of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0034] Fig.14 Another cross-sectional view of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application;

[0035] Fig.15 Another cross-sectional view of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application. DETAILED DESCRIPTION

[0036] As can be seen from the background technology, the performance of current non-volatile static memory needs to be improved.

[0037] It should be noted that NVM (Non-Volatile Memory) is a non-volatile memory.

[0038] Figure 1 An equivalent circuit diagram of a memory cell structure of a non-volatile semiconductor memory device having RAM operation and NVM characteristics provided for related technology; Figure 2 An operation timing diagram of a memory cell of a non-volatile semiconductor memory device having RAM operation and NVM characteristics is provided for the related art; Figure 3 A schematic diagram of a threshold voltage Vth state of a memory cell of a non-volatile semiconductor memory device having RAM operation and NVM characteristics is provided in the related art.

[0039] After analysis, it was found that Figure 1In the related art, the memory cell of nvSRAM (non-volatile static memory or non-volatile semiconductor memory device) consists of an SRAM memory cell part and a non-volatile memory part. The SRAM memory cell part includes a standard configuration CMOS (Complementary Metal Oxide Semiconductor) trigger (P1-N1, P2-N2) and two access transistors (A1 and A2), that is, a typical configuration of 6 transistors. The non-volatile memory part consists of two groups of three elements (T1-M1-T3 and T2-M2-T4), and in each group, a transistor is connected in series at both ends of the non-volatile memory cell transistors M1 and M2. T1-M1-T3 and T2-M2-T4 are respectively located between the storage node DT of the SRAM memory cell part and the power supply Vcc and between the storage node / DT of the SRAM memory cell part and the power supply Vcc. Figure 1 The control signals and power supplies for operating the nvSRAM memory cells are also shown. Among them, Vcc represents the power supply voltage applied to the nvSRAM memory cell from the outside, VccS represents the power supply generated from the Vcc in the nvSRAM and supplied only to the SRAM memory cell part, BL is the bit line, / BL is the inverted bit line corresponding to its inverted data, and WL is the word line in the SRAM memory cell part. The storage nodes of the SRAM memory cell part are DT and / or DT. "Recall" and "Store" of the non-volatile memory part are control signals during the "readback operation" and during the "storage operation", respectively, and VPE represents the erase / programming power supply used when performing erase operations and programming operations on the non-volatile memory cell transistors (M1 and M2) of the non-volatile storage part. In the related art, VccS and VPE are generated by the external power supply Vcc and controlled by a known circuit (not shown in the figure) in the nvSRAM chip.

[0040] refer to Figure 2 , Figure 2 This diagram shows how each power supply voltage and each control signal change over time each time the nvSRAM memory cell operates (timing diagram). This is an operation example of the related art. Figure 3 , Figure 3 The gate threshold voltage (Vth) of the nonvolatile memory cell transistors M1 and M2 is shown. The operation of the nvSRAM memory cell is described in detail below.

[0041] The operation of nvSRAM memory cell can be roughly divided into the following three parts:

[0042] (1) Recall operation

[0043] When the power is turned on, the nonvolatile data stored in the nonvolatile memory section is transferred to the SRAM storage unit section;

[0044] (2) SRAM operation (static storage operation)

[0045] It is the same as traditional SRAM, so I won’t go into details here;

[0046] (3) Store operation

[0047] When the power is turned off, the data in the SRAM storage cell section is copied to the nonvolatile memory section for backup.

[0048] Since the configuration of the SRAM memory cell portion is the same as that of the SRAM in the related art, the SRAM operation in (2) above is omitted. Each operation will be described below.

[0049] The nonvolatile memory cell transistors M1 and M2 are N-channel nonvolatile memory cell transistors of a Silicon Oxide Nitride Semiconductor (SNOS) structure. Figure 3The relationship between the Vth state of the nonvolatile memory cell transistor and the data "1" or "0" is shown. If the data is "1", M1 is in the erased state, its Vth is negative, and M2 is in the programmed state, its Vth is positive; if the data is "0", M1 is in the programmed state, its Vth is positive, and M2 is in the erased state, its Vth is negative. In addition, during normal operation, Vcc and VccS are set to 5V. The following will be explained with the operation when the initial data of the nonvolatile memory part of the nvSRAM memory cell is "0". First, the power supply Vcc of the nvSRAM memory cell is turned on, and the circuit in the nvSRAM memory cell starts charging. At time t1, the voltage reaches Vcc at which the circuit can operate, and each signal shown in the figure is fixed at L (GND) or H (Vcc). At this time, the power supply VccS of the SRAM memory cell part is maintained at the ground potential. Therefore, BL, / BL, DT, and / DT of the SRAM memory cell part may have residual charge depending on the state before time t1. During the period from time t2 to time t3, WL is set to H, and the above-mentioned node (circuit node) is discharged and set to L. At time t4, when Recall=H, the nonvolatile memory cell transistors M1 and M2 of the nonvolatile memory portion are charged by Vcc through T1 and T2. At this time, since VPE=L, M2 with negative Vth in the erase state is in the on state, and M1 with positive Vth in the programming state is in the off state. Therefore, the drain of T4 is charged to Vcc through M2, and T3 is not charged, and its drain remains at a low level in the discharge state. Next, at time t5, Store=H, T3 and T4 are turned on, and the power supply VccS of the SRAM memory cell portion rises. T3 and T4 are in the on state, but / DT is charged through T2-M2-T4, and DT is not charged because M1 in T1-M1-T3 is in the off state. Afterwards, when VccS rises to a voltage higher than the operating voltage of the SRAM memory cell section, P2 and N1 of the SRAM memory cell section are turned on, and P1 and N2 are turned off, DT is set to L, / DT is set to H, and the respective storage states of M1 and M2 (M1 = programming state, M2 = erasing state) are transmitted to the SRAM memory cell section, and DL = L and / DL = H are transmitted to the SRAM memory cell section as data "0" to complete the readback operation. In this way, the data "0" stored in the non-volatile memory section set in the SRAM memory cell section can start the subsequent SRAM operation.

[0050] Next, the storage operation of the related art nvSRAM storage cell will be described. In addition to the above-mentioned read-back operation, Recall=L and Store=H are set during the SRAM operation. The storage operation is started by detecting the voltage drop in the Vcc power supply. Figure 2At time t8 in the example, it is detected that the voltage drops to a predetermined voltage, WL=L, and then BL and / BL are discharged and set to L. At this time, the voltages of nodes DT and / DT of the SRAM memory cell portion remain unchanged (in this example, DT=L and / DT=H). Next, during the period from time t9 to time t10, a negative high voltage (e.g. -15V) is applied to VPE. Positive charge is injected into the nitride layer immediately below the gates of the non-volatile memory cell transistors M1 and M2, and the Vth of M1 and M2 are both negative (erase operation)

[0051] Next, during the period from t11 to t12, a positive high voltage (e.g., +15V) is applied to VPE, and the program operation starts. Since Recall=L and Store=H, T1 and T2 should be turned off because Recall=L, and T4 should be turned on because Store=H, but because / DT=H and T2 is turned off because / DT=H, T4 is turned off. Therefore, the source and drain of M2 become floating potentials, and the channel voltage of M2 increases due to coupling with the gate voltage VPE (capacitive coupling), and the potential difference required for the programming operation cannot be obtained. Therefore, M2 cannot be programmed and remains in the erased state. On the other hand, T1 is in the off state when M1 is connected, but since Store=H and DT=L, T3 is turned on, and the channel of M1 is set to L=GND. Therefore, since the channel potential of M1 remains at GND even when VPE is applied, negative charges are injected into the nitride layer just below the gate of the nonvolatile memory cell transistor M1, its Vth becomes positive, and only M1 is in the programming state (programming operation). Therefore, M2 is in the erased state and M1 is in the programming state, which is the same as the storage state data "0" of the nonvolatile memory portion during the above-mentioned readback operation. In this way, the data "0" of the SRAM memory cell portion is transferred to the nonvolatile memory portion, so that even if the VccS power supply drops as the Vcc power supply drops, causing the data in the SRAM memory cell portion to disappear, the nonvolatile memory cell transistors M1 and M2 can continue to retain the data.

[0052] As described above, the memory cell of the nonvolatile semiconductor memory device in the related art is composed of 6 SRAM memory cell parts and 6 nonvolatile memory parts, totaling 12 elements. The 6 elements of the nonvolatile memory part are necessary, which means that the number of elements in the memory cell of the nonvolatile semiconductor memory device is more than that of the conventional SRAM memory cell, and the area of ​​the memory cell is also larger, so compared with the SRAM memory cell, it is difficult to increase the capacity of the memory cell of the nonvolatile semiconductor memory device under the same manufacturing process.

[0053] The non-volatile memory part uses non-volatile storage elements, such as Silicon Oxide Nitride Oxide Semiconductor (SONOS), Metal Nitride Oxide Semiconductor (MNOS), Silicon Oxide Nitride Semiconductor (SNOS) or floating gate transistors, etc. This requires the use of transistors T3 and T4 to electrically isolate the non-volatile storage element connected to the node (circuit node) of the SRAM storage cell part.

[0054] Furthermore, since non-volatile semiconductor memory devices can perform SRAM data backup without a battery or power supply, it is required that in a high temperature environment where the battery is difficult to work continuously for a long time or in outdoor use scenarios, it is hoped that the non-volatile semiconductor memory devices can operate at higher temperatures and have long-term data retention. However, conventional non-volatile devices with structures such as SONOS, MNOS, and SNOS have data retention problems at higher temperatures.

[0055] On the other hand, the inventors found that a programming method was proposed for transistors of a non-volatile memory composed of P-type channel transistors with a SONOS structure using the band-to-band tunneling phenomenon (BTBT phenomenon), which can prove that the voltage applied to the source and drain during the programming process can be reduced to below Vcc instead of a high voltage.

[0056] The inventors also found that a non-volatile memory cell composed of a P-type channel transistor with a floating gate structure has a higher data retention characteristic than a non-volatile memory cell composed of a traditional transistor. For example, under high temperature conditions of 150°C, after 1 million rewrites, the data retention time of the non-volatile memory cell composed of a P-type channel transistor with a floating gate structure exceeds that of the non-volatile memory cell composed of a traditional transistor by 10 years.

[0057] However, if the transistor of the nonvolatile memory is a P-channel transistor, a negative voltage needs to be applied to the gate of the memory transistor during a read operation, for example, when the memory transistor is turned on. Therefore, when the nonvolatile semiconductor memory device is operated using the nonvolatile memory cell transistor, a negative voltage must be generated during the call operation at power-on. Therefore, in addition to the generation and control of the VccS power supply of the SRAM memory cell portion, a control circuit for generating a negative voltage for the nonvolatile memory cell transistor needs to be provided, so that the area of ​​the negative voltage generation circuit and the negative voltage voltage control circuit will also increase, and since a negative voltage needs to be generated during the power-on operation, the startup time will also increase.

[0058] On the other hand, nonvolatile semiconductor memory devices are also required to be able to operate at a Vcc lower than 1.2 V. However, in the above nonvolatile memory, it is difficult to control the gate of the transistor in the range from GND to Vcc to turn the transistor on or off, that is, it is difficult for the nonvolatile semiconductor memory device to operate at a low voltage.

[0059] On the other hand, the inventors found that the non-volatile memory part can have an MTJ element (magnetic tunnel junction element), and a solution that can form a non-volatile semiconductor memory device memory unit with 10 elements. However, in the process of forming the magnetic tunnel junction element, a manufacturing method that is not available in the existing CMOS manufacturing technology is required, and the requirements for the manufacturing plant are high, so there is a problem of increased manufacturing costs. In addition, the magnetic tunnel junction element also has the problem of data retention at high temperatures.

[0060] In addition, the inventors have found that when the non-volatile memory cell transistor is a P-type channel transistor, the non-volatile memory cell transistor can form a floating gate structure, so a floating gate can be formed above the channel region and a control gate can be formed above the floating gate through an insulating film. Other transistors constituting the memory may not have a floating gate, but may have a transistor structure with a single gate.

[0061] Since the heights of the memory transistors using the floating gate structure and the transistors using the traditional single-layer gate structure from the silicon surface are different, it is difficult to process both at the same time during the gate processing step in the manufacturing process. They must be processed separately, so the distance between the two must be increased. In this way, it may be difficult to reduce the area of ​​the memory cell.

[0062] In addition, when the non-volatile memory cell transistor is a P-channel transistor, a high voltage needs to be applied to the N-well of the P-channel transistor during its operation. This means that the non-volatile memory cell transistor cannot share the N-well with the transistor element in the SRAM memory cell part, which requires the use of the Vcc power supply, thereby increasing the area of ​​the memory cell. In addition, the non-volatile memory cell transistor must be kept at a certain distance from the SRAM memory cell part to avoid high voltage leakage and high voltage coupling (electrostatic coupling) affecting the operation of the SRAM memory cell part.

[0063] To solve the above problems, the embodiment of the present application provides a memory cell of a non-volatile semiconductor memory device having RAM operation and NVM features, which has at least the following advantages: the non-volatile memory portion is a structure composed of four elements including two non-volatile memory cell transistors. Since the number of elements of the memory cell is 10, greater integration can be achieved using existing manufacturing technology. In addition, since the non-volatile memory cell transistor is composed of a P-type channel transistor, the non-volatile memory portion in the non-volatile semiconductor memory device can achieve a larger storage capacity and a longer data retention time at a higher temperature. In addition, in the memory cell of the non-volatile semiconductor memory device, when the non-volatile memory portion includes a non-volatile memory cell transistor that is a P-type channel transistor and an N-type channel transistor, the threshold voltage Vth of the non-volatile memory cell transistor is negative in the erase state and positive in the programming state. In this way, the erase state and the programming state can be identified by adding VccS to the gate of the non-volatile memory cell transistor, depending on whether the non-volatile memory cell transistor is in the off state or the on state. When the nonvolatile memory cell transistor is a P-channel transistor and other transistors of the nonvolatile memory portion are also P-channel transistors, the area increase phenomenon caused by well division can be reduced.

[0064] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0065] On the one hand, an embodiment of the present application provides a non-volatile semiconductor memory device with RAM operation and NVM features, including: a memory cell composed of 10 semiconductor elements, the memory cell including an SRAM memory cell part composed of 6 semiconductor elements and a non-volatile memory part composed of 4 semiconductor elements; wherein the non-volatile memory part includes two groups of dual elements, each group of dual elements includes a non-volatile memory cell transistor and an N-type channel transistor connected in series, and each transistor of the dual elements is connected to the SRAM memory cell part; the non-volatile memory cell transistor is a P-type channel transistor, and a charge storage layer including an insulating layer is provided above the channel region of the non-volatile memory cell transistor, and an insulating layer and a gate are stacked in sequence above the charge storage layer; the two groups of dual elements are respectively connected to the positive storage node and the negative storage node of the SRAM memory cell part.

[0066] It should be noted that in the following description, a nonvolatile semiconductor memory device having both RAM operation and NVM characteristics will be referred to as a nonvolatile semiconductor memory device.

[0067] In the embodiment of the present application, in the memory cell of the nonvolatile semiconductor memory device, the nonvolatile memory portion is not composed of 6 elements including two nonvolatile memory cell transistor elements, but is composed of 4 elements including 2 nonvolatile memory cell transistor elements, and the memory cell of the nonvolatile semiconductor memory device includes 10 elements, and the nonvolatile memory cell transistor is a P-type channel transistor with a floating gate and a charge storage layer including a nitride film. In addition, the nonvolatile memory portion is composed of two groups of elements, each group of elements includes a nonvolatile memory cell transistor and an N-type channel transistor, and the former is a P-type channel transistor with a floating gate and a charge storage layer including a nitride film.

[0068] Thus, in the memory cell of the nonvolatile semiconductor memory device, the nonvolatile memory portion is a structure composed of four elements including two nonvolatile memory cell transistors. Since the number of elements in the memory cell is 10, greater integration can be achieved using existing manufacturing technology. In addition, since the nonvolatile memory cell transistor is composed of a P-type channel transistor, the nonvolatile memory of the nonvolatile semiconductor memory device can achieve a larger storage capacity and a longer data retention time at a higher temperature. In addition, in the memory cell of the nonvolatile semiconductor memory device, the nonvolatile memory cell transistor in the nonvolatile memory portion is composed of a P-type channel transistor, and its threshold voltage Vth is negative in the erase state and positive in the programming state. Thus, the erase state and the programming state can be identified by adding VccS to the gate of the nonvolatile memory cell transistor, depending on whether the nonvolatile memory cell transistor is in the off state or the on state.

[0069] In some embodiments, the threshold voltage value Vth of the nonvolatile memory cell transistor is a positive voltage in a programmed state, and the threshold voltage value Vth of the nonvolatile memory cell transistor is a negative voltage in an erased state.

[0070] In this way, when performing a call operation after power-on, there is no need to apply a high voltage to the gate of the non-volatile memory cell transistor, thereby saving the time of generating and controlling the high voltage immediately after power-on, which helps to speed up the startup process.

[0071] In some embodiments, the charge storage layer includes an insulating layer and a first floating gate stacked in sequence, and an insulating layer and a second control gate are stacked in sequence above the first floating gate; the six semiconductor elements of the SRAM storage unit part are six element transistors, and the six element transistors and the channel region of the N-type channel transistor of the non-volatile memory part all have an insulating layer and a second floating gate stacked in sequence above them, and a second control gate is provided above the second floating gate, and the second floating gate and the second control gate are electrically connected to each other.

[0072] In the technical solution provided in the embodiment of the present application, the non-volatile memory cell transistor has a two-layer gate structure, wherein the first floating gate is formed above the channel region through an insulating layer, and the first control gate is formed above the floating gate through another insulating layer. The six transistor elements of the SRAM memory cell part and the N-type channel transistor of the non-volatile memory part all form a second floating gate above the channel region through an insulating layer, and further form a second control gate above the second floating gate, and the second floating gate and the second control gate are electrically connected to each other, that is, in the non-volatile semiconductor memory device provided in the embodiment of the present application, the transistor elements of the SRAM memory cell part and the transistor elements of the non-volatile memory part all have a double-layer gate structure consisting of a floating gate and a control gate. Since all elements in the memory cell have a double-layer gate structure, when manufacturing the non-volatile semiconductor memory device, the spacing between the gate patterns of each transistor can be narrower, thereby realizing the miniaturization of the overall area of ​​the memory cell.

[0073] In some embodiments, in the SRAM storage cell portion, one N-type well is used to set two P-type channel transistors, one P-type well is used to set two N-type channel transistors, and the two P-type wells are located on both sides of one N-type well; in the non-volatile memory portion, one P-type well is used to set one N-type channel transistor, one N-type well is used to set one non-volatile storage cell transistor, the two P-type wells of the non-volatile memory portion are respectively located on the side of the two P-type wells of the SRAM storage cell away from the N-type well, and the two N-type wells of the non-volatile memory portion are respectively located on the side of the two P-type wells of the non-volatile memory portion away from the SRAM storage cell portion.

[0074] In this way, when a high voltage is applied to the non-volatile memory cell transistor, the N-type well of the non-volatile memory cell transistor and the N-type well of the SRAM memory cell portion can be fully separated, thereby preventing interference to the SRAM memory cell portion when a high voltage is applied to the non-volatile memory cell transistor, thereby improving the reliability of the memory cell operation.

[0075] Figure 4An equivalent circuit diagram of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Figure 5 A schematic diagram of a threshold voltage Vth state of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Figure 6 An operation timing diagram of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Figure 7 A cross-sectional view of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Figure 8 Another cross-sectional view of a memory cell of a first non-volatile semiconductor memory device having RAM operation and NVM features provided by an embodiment of the present application; Fig. 9 Another cross-sectional view of a memory cell of the first non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application.

[0076] refer to Figure 4 In some embodiments, the memory cell of the nonvolatile semiconductor memory device provided in the embodiments of the present application is composed of an SRAM memory cell part and a nonvolatile memory part, the nonvolatile memory part includes two groups of dual elements, and the two groups of dual elements are respectively connected to the circuit nodes DT and / DT of the SRAM memory cell part. The SRAM memory cell part is composed of 6 transistors.

[0077] On the other hand, in an embodiment of the present application, the non-volatile memory portion includes two groups of element groups, the first element group includes MP1 and T1, and the second element group includes MP2 and T2, wherein MP1 and MP2 are non-volatile memory cell transistors and are P-type channel transistors, T1 and T2 are N-type channel transistors, MP1 is connected in series with T1, and MP2 is connected in series with T2, and the non-volatile memory cell transistors (MP1 and MP2) both have a two-layer gate structure consisting of a first floating gate and a first control gate, and even if the non-volatile memory cell transistors (MP1 and MP2) are P-type transistors having a nitride film charge storage layer between the gate and the channel, the following operations can be implemented.

[0078] In addition, the element groups are respectively located between the positive storage node DT of the SRAM memory cell part and the power supply Vcc, and between the negative storage node / DT of the SRAM memory cell part and the power supply Vcc.

[0079] also, Figure 4Also shown are some control signals and power supplies for operating the memory cells of the nonvolatile semiconductor memory device. Vcc (not shown) represents the power supply voltage applied from the outside to the memory cells of the nonvolatile semiconductor memory device, VccS represents the power supply generated from Vcc in the nonvolatile semiconductor memory device and supplied only to the SRAM memory cell portion, BL is the bit line, / BL is the complementary bit line, and WL is the word line in the SRAM memory cell portion. The storage nodes of the SRAM memory cell portion are DT and / DT. "Recall" of the nonvolatile memory portion is the control signal during the "readback operation", VPE represents the erase power supply used when performing an erase operation on the nonvolatile memory cell transistors (MP1 and MP2) of the nonvolatile memory portion, and represents the programming power supply used when performing a programming operation on the nonvolatile memory cell transistors (MP1 and MP2) of the nonvolatile memory portion. In order to realize the programming operation and the erase operation on MP1 and MP2, VNW is the power supply for controlling the potential of the N-type well where MP1 and MP2 are located. In some embodiments, VccS and VPE are generated by an external power source Vcc and controlled by a control circuit (not shown) in the nonvolatile semiconductor memory device chip.

[0080] In some embodiments, reference Figure 6 , Figure 6 The operation of a storage unit of a non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application is represented in the order of readback operation, SRAM operation, and storage operation. It should be noted that regarding the SRAM operation, since the structure of the SRAM storage unit part is the same as that of the conventionally known SRAM, its operation is also the same, so the description is omitted.

[0081] The following describes the case where the data is "0".

[0082] In some embodiments, reference Figure 4 , Figure 5 as well as Figure 6 , the power supply Vcc of the nonvolatile semiconductor memory device is turned on, and the circuit in the nonvolatile semiconductor memory device starts to charge. At the same time, VPE and VNW also rise to Vcc. At time t1, the specified voltage VDIS is reached, Recall is set to a low level L (GND), and VPE and VNW are set to a high level H (Vcc). At this time, VccS, which is the power supply of the SRAM, is maintained at a low level L. Therefore, BL, / BL, DT, / DT of some parts of the SRAM memory cell may also have residual charges, so during the period from time t2 to t3, WL is set to a high level H, and BL, / BL, DT, / DT are discharged, so that BL, / BL, DT, / DT are low level L.

[0083] During the period from time t4 to t6, Recall is at a high level H and VPE is at a low level L, and the source of MP1 is grounded through T1 or the source of MP2 is grounded through T2. For example, when the data is "0", since VPE is at a low level L, the P-type channel transistor MP1 with a positive threshold voltage is turned on, and the P-type channel transistor MP2 with a negative threshold voltage is turned off. Since Recall is at a high level H, T1 and T2 are turned on, the storage node DT is discharged to the GND potential through MP1, and the storage node / DT is electrically floating because MP2 is turned off.

[0084] At time t5, the voltage of VccS rises and when it exceeds the operating voltage of the SRAM storage cell part, since P2 and N1 of the SRAM storage cell part are in the on state and P1 and N2 are in the off state, DT is discharged to a low level L and / DT is charged to a high level H. At time t6 when Recall is at a low level L, DT of the SRAM storage cell part is at a low level L and / DT is at a high level H.

[0085] Therefore, when the data is "0", the state of the non-volatile memory part is MP1 in the programming state and MP2 in the erasing state, MP1 transfers the data "0" (DT is low level L, / DT is high level H) to the SRAM storage unit part, and the read back operation ends.

[0086] In this way, the non-volatile storage unit part transmits the data "0" to the SRAM storage unit part, so that the data stored in the non-volatile memory is "0", and the subsequent SRAM operation can be started.

[0087] In some embodiments, when the data is "1", Figure 5 The states of MP1 and MP2 shown in FIG. 1 are opposite to those described above, and the relationship between the charge and discharge of DT and / DT is also opposite to those described above, DT is at a high level H and / DT is at a low level L.

[0088] In some embodiments, since the SRAM memory cell part is a CMOS structure, the discharge operation based on WL being at the high level H during the period from time t2 to time t3 may also be omitted.

[0089] Next, the storage operation of the embodiment of the present application is described. In addition to the above-mentioned read-back operation, the SRAM operation also sets Recall to a low level L, and VPE and VNW are both set to Vcc. Under this potential setting, MP1 and MP2 are both in the off state, so no potential is provided to the memory nodes DT and / DT of the SRAM storage unit part. In addition, the memory retention of MP1 and MP2 will not be affected.

[0090] In some embodiments, a storage operation may be initiated when the Vcc supply voltage drops below a specified voltage. Figure 6 At time t7, it is detected that Vcc drops to a predetermined voltage VSW, WL is at a low level L, and then BL and / BL are discharged to a low level L. As a result, the voltages of the nodes DT and / DT of the SRAM memory cell are maintained (for example, when the data is "0", DT is at a low level L and / DT is at a high level H).

[0091] Next, during the period from time t8 to time t9, for the erase state operation, VPE is set to the GND level (from Vcc), and from time t9 to time t10, a negative high voltage VNEG, such as -12V, is applied to VPE, and a positive high voltage VPEW, such as +4V, is applied to VNW. Due to FN tunneling (Fowler-Nordheim tunneling), electrons are pulled out from the charge storage layer (i.e., the floating gate of MP1 and the floating gate of MP2), and the threshold voltage Vth of the non-volatile memory cell transistor is negatively shifted, that is, the erase state operation is realized.

[0092] Next, the voltage for performing the erase state operation is reset during time t10 to t11, and then, for the program state operation, VPE is set to GND (from VNEG) and then to Vcc. In addition, VNW is set to Vcc from VPEW.

[0093] Next, during the period from time t12 to t13, a positive high voltage VPPG, such as +12V, is applied to VPE, and a positive low voltage VPPW, such as +4V, is applied to VNW to start the programming state operation. At this time, the drain of MP1 is connected to DT and is at a low level L. Therefore, due to the band-to-band tunneling (BTBT) effect, electrons are injected into the charge storage layer including the floating gate, and its threshold voltage Vth is positively shifted, that is, the programming state operation is realized. On the other hand, MP2 will not have the BTBT phenomenon because its drain connection / DT is at a high level, so MP2 will not have a shift in the threshold voltage Vth, and the threshold voltage Vth in the erased state remains unchanged.

[0094] That is, even after the Vcc power supply drops and the VccS power supply drops starting at time t14, the data in the SRAM memory cell portion is lost, data "0" is still retained in MP1 and MP2 as the threshold voltage Vth of MP1 and the threshold voltage Vth of MP2 (MP1 is in the programmed state and MP2 is in the erased state).

[0095] Figure 7A cross-sectional view of a storage unit of a non-volatile semiconductor storage device having RAM operation and NVM characteristics provided in an embodiment of the present application. It should be noted that: Figure 7 It is mainly used to indicate the relative position relationship between the gate structure and the well, and does not constitute a restriction on the actual distance or size of the components in the memory cell. Figure 7 Will Figure 4 The equivalent circuit diagram corresponds to the semiconductor structure of the nonvolatile semiconductor memory device memory. Figure 7 (exist Figure 7 Only MP1 is shown, or only MP2 is shown), the gate of the non-volatile memory cell transistor is a two-layer gate structure with a floating gate, and the other transistors are transistors with a single-layer gate structure.

[0096] In some embodiments, a memory cell of a nonvolatile semiconductor memory device is formed on a P-type substrate, P-type channel transistors P1 and P2 of a SRAM memory cell portion are formed in an N-type well (LV N-well) corresponding to low voltage operation, N-type channel transistors N1, N2, A1, and A2 are formed in a P-type well (LV P-well) corresponding to low voltage operation, nonvolatile memory transistors MP1 and MP2 composed of P-type channel transistors are formed in an N-type well (HV N-well) corresponding to high voltage operation, and N-type channel transistors T1 and T2 connected to the sources of the above MP1 and MP2 are formed in a P-type well (HV P-well) corresponding to high voltage operation.

[0097] In some embodiments, reference Figure 7 The nonvolatile memory cell transistor constituting the memory cell has a double-layer gate structure including a floating gate, while the other transistors have a single-layer gate structure. Therefore, the height of the nonvolatile memory cell transistor from the silicon surface is different from the height of the other transistors from the silicon surface.

[0098] It should be noted that if the heights of the gates of the transistors in the memory cell are not consistent, it is difficult to process two gates of different heights at the same time during the manufacturing process of the gates. If they are processed separately, the distance between the transistors needs to be increased, which will lead to the problem of insufficient miniaturization. Figure 8 The non-volatile memory cell transistors that make up the memory cell have a double-layer gate structure, which includes a floating gate and a control gate. The other transistors also have a double-layer gate structure, and the control gate and the floating gate are short-circuited (electrically connected). This makes the height of all transistors in the memory cell the same (the height from the silicon substrate), so the gate processing conditions in the manufacturing process are also the same, and the size (area) of the memory cell can be further reduced.

[0099] In some embodiments, reference Figure 4 , Figure 6 and Figure 7 , or refer to Figure 4 , Figure 6 and Figure 8 , P1 and P2 of the SRAM storage cell part are set in a low voltage N-type well (LV N-well), N1, N2, A1, A2 are set in a low voltage P-type well (LV P-well), and in addition, the non-volatile storage cell transistors MP1 and MP2 of the non-volatile memory part are set in a high voltage N-type well (HV N-well), and T1 and T2 are set in a high voltage P-type well (HV P-well). Therefore, the high voltage applied to the N-type well (HV N-well) during the erase state operation and the programming state operation of the non-volatile storage cell transistor can prevent the data of the SRAM storage cell part from being destroyed by electrical interference.

[0100] In some embodiments, reference Fig. 9 Among the six elements constituting the SRAM memory cell portion, an N-type well (LV N-well) including two P-type channel transistors has a P-type well (LV P-well) on both sides, and the N-type channel transistor elements N1, A1 and N2, A2 in the six elements of the SRAM memory cell portion are arranged in the P-type well (LV P-well), and a P-type well (HV P-well) of the N-type channel transistors T1 and T2 of the non-volatile memory portion is formed outside the P-type well (LV P-well), and an N-type well (HV N-well) of the non-volatile memory transistor is formed on the outermost side.

[0101] As a result, the N-type well (HV N-well) of the non-volatile memory cell transistor to which a high voltage is applied can be isolated from the N-type well (LV N-well) of the SRAM memory cell portion, thereby alleviating the electrical interference to the SRAM memory cell portion when a high voltage is applied to the non-volatile memory cell transistor.

[0102] Fig.10 An equivalent circuit diagram of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Fig.11 A schematic diagram of a threshold voltage Vth state of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Fig.12 An operation timing diagram of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Fig.13 A cross-sectional view of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Fig.14 Another cross-sectional view of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application; Fig.15 Another cross-sectional view of a memory cell of a second non-volatile semiconductor memory device having RAM operation and NVM characteristics provided by an embodiment of the present application.

[0103] On the other hand, an embodiment of the present application provides a non-volatile semiconductor memory device with RAM operation and NVM features, including: a memory cell composed of 10 semiconductor elements, the memory cell including an SRAM memory cell part composed of 6 semiconductor elements and a non-volatile memory part composed of 4 semiconductor elements; wherein the non-volatile memory part includes two groups of dual elements, each group of dual elements includes a non-volatile memory cell transistor and a P-type channel transistor connected in series, and each transistor of the dual elements is connected to the SRAM memory cell part; the non-volatile memory cell transistor is a P-type channel transistor, and a charge storage layer including an insulating layer is provided above the channel region of the non-volatile memory cell transistor, and an insulating layer and a gate are stacked in sequence above the charge storage layer; the two groups of dual elements are respectively connected to the positive storage node and the negative storage node of the SRAM memory cell part.

[0104] In the embodiment of the present application, in the memory cell of the nonvolatile semiconductor memory device, the nonvolatile memory portion is not composed of 6 elements including two nonvolatile memory cell transistor elements, but is composed of 4 elements including 2 nonvolatile memory cell transistor elements, and the memory cell of the nonvolatile semiconductor memory device includes 10 elements, and the nonvolatile memory cell transistor is a P-type channel transistor with a floating gate or a charge storage layer made of a nitride film. In addition, the nonvolatile memory portion is composed of two groups of elements, each group of elements includes: a nonvolatile memory cell transistor and a P-type channel transistor, the former being a P-type channel transistor with a floating gate or a charge storage layer made of a nitride film.

[0105] In the memory cell of the nonvolatile semiconductor memory device provided in the embodiment of the present application, the nonvolatile memory portion is composed of four elements, the four elements include two nonvolatile memory cell transistors, and the number of memory cell elements can be reduced to 10 elements. In this way, the memory capacity can also be increased using conventional manufacturing technology. In addition, the nonvolatile memory cell transistor is composed of a P-type channel transistor, so that data can be retained for a long time at a higher temperature. Moreover, since the other transistors of the nonvolatile memory portion are also composed of P-type channel transistors, the phenomenon of area increase caused by well segmentation can be reduced.

[0106] In some embodiments, the threshold voltage value Vth of the nonvolatile memory cell transistor is a negative voltage in both the programmed state and the erased state.

[0107] In this way, the gate voltage of the nonvolatile memory cell transistor is independent of the Vcc voltage, so the on or off of the nonvolatile memory cell transistor can be controlled with a lower voltage.

[0108] In some embodiments, the charge storage layer includes an insulating layer and a first floating gate stacked in sequence, and an insulating layer and a second control gate are stacked in sequence above the first floating gate; the six semiconductor elements of the SRAM storage cell part are six element transistors, and the six element transistors and the channel region of the P-type channel transistor of the non-volatile memory part all have an insulating layer and a second floating gate stacked in sequence above them, and a second control gate is provided above the second floating gate, and the second floating gate and the second control gate are electrically connected to each other.

[0109] In the technical solution provided in the embodiment of the present application, the non-volatile memory cell transistor has a two-layer gate structure, wherein a first floating gate is formed above the channel region through an insulating layer, a first control gate is formed above the floating gate through another insulating layer, and six transistor elements of the SRAM memory cell part and the P-type channel transistor of the non-volatile memory part form a second floating gate above the channel region through an insulating layer, and further form a second control gate above the second floating gate, and the second floating gate and the second control gate are electrically connected to each other. That is, in the non-volatile semiconductor memory device provided in the embodiment of the present application, the transistor elements of the SRAM memory cell part and the transistor elements of the non-volatile memory part both have a double-layer gate structure consisting of a floating gate and a control gate.

[0110] Therefore, all transistor elements in the memory cell have a double-layer gate structure, the spacing between the gate patterns of each transistor can be reduced, the area of ​​the memory cell can be reduced, and a non-volatile semiconductor memory device with higher integration can be produced.

[0111] In some embodiments, in the SRAM memory cell portion, an N-type well is used to set two P-type channel transistors, and one P-type well is used to set two N-type channel transistors, and the two P-type wells are located on both sides of an N-type well; in the non-volatile memory portion, an N-type well is used to set a non-volatile memory cell transistor and a P-type channel transistor, and the two N-type wells of the non-volatile memory portion are respectively located on one side of the two P-type wells of the SRAM memory cell away from the N-type well.

[0112] When a high voltage is applied to the non-volatile memory cell transistor, the N-type well of the non-volatile memory cell transistor and the N-type well of the SRAM memory cell portion can be sufficiently separated, thereby preventing interference to the SRAM memory cell portion when a high voltage is applied to the non-volatile memory cell transistor, thereby improving the reliability of the memory cell operation.

[0113] In addition, since the high-voltage N-type well can be set in the outermost layer, and the non-volatile memory cell transistors and P-type transistors of the non-volatile memory part are formed based on the high-voltage N-type well, in a memory array with repeatedly arranged memory cells, adjacent memory cells can share the N-type well, thereby making the arrangement of the memory cells more efficient and achieving higher integration.

[0114] Another nonvolatile semiconductor memory device with RAM operation and NVM features provided by an embodiment of the present application is described in detail below. Another nonvolatile semiconductor memory device with RAM operation and NVM features provided by an embodiment of the present application can operate at a lower voltage Vcc.

[0115] In some embodiments, reference Fig.10 The memory cell of the nonvolatile semiconductor memory device involved in the embodiment of the present application has the same circuit connection mode and signal mode as the aforementioned embodiment, and is composed of an SRAM memory cell part and a nonvolatile memory part. The nonvolatile memory part includes two groups of double elements, and the two groups of double elements are respectively connected to the positive storage node DT and the negative storage node / DT of the SRAM memory cell part. The SRAM memory cell part is composed of 6 transistors.

[0116] In some embodiments, the nonvolatile memory portion is configured as follows: the nonvolatile memory portion is composed of two nonvolatile memory cell transistors MP1 and MP2 and two P-type channel transistors connected in series with the corresponding nonvolatile memory cell transistors, that is, MP1 and TP1 are connected in series, MP2 and TP2 are connected in series, MP1 and MP2 are both P-type channel transistors with a two-layer gate structure, and the two-layer gate structure includes a floating gate. Even if the nonvolatile memory cell transistors (MP1 and MP2) are P-type transistors with a charge storage layer made of a nitride film between the gate and the channel, the nonvolatile memory cell transistors can still implement the following operations.

[0117] Of the two groups of dual elements, one group of dual elements (MP1 and P1) is located between the circuit node DT of the SRAM storage cell part and the power supply Vcc, and the other group of dual elements (MP2 and P2) is located between the circuit node / DT of the SRAM storage cell part and the power supply Vcc.

[0118] Since the nonvolatile memory portion has only an N-type well for arranging a P-type transistor, the spacing between transistors can be reduced compared to the well arrangement in the aforementioned embodiment.

[0119] also, Fig.10 The signals and power supplies used to operate the memory cells of the nonvolatile semiconductor memory device are also shown. The signal names are the same as those in the previous embodiment. Figure 4The nonvolatile semiconductor memory device shown is consistent.

[0120] In some embodiments, Fig.12 In the embodiment, as in the above, the operation of a storage unit of a non-volatile semiconductor memory device with RAM operation and NVM characteristics provided by the embodiment of the present application is represented in the order of readback operation, SRAM operation, and storage operation. It should be noted that, regarding the SRAM operation, since the structure of the SRAM storage unit part is the same as that of the conventionally known SRAM, its operation is also the same, so the description is omitted.

[0121] In some embodiments, reference Fig.11 , Fig.11 Indicates the state of the threshold voltage Vth of the nonvolatile memory transistor MP1 and the state of the threshold voltage Vth of MP2 corresponding to the operation. The threshold voltage Vth is set to a negative voltage in both the erase state and the program state. Therefore, the threshold voltage Vth of MP1 and the threshold voltage Vth of MP2 are independent of the Vcc voltage, so the on state or off state of the nonvolatile memory cell transistor can be controlled at a lower voltage.

[0122] The following describes the case where the data is "0".

[0123] In some embodiments, first, the power supply Vcc of the nonvolatile semiconductor memory device is turned on, and the circuit in the nonvolatile semiconductor memory device starts to charge. At the same time, VPE and VNW also rise to Vcc. At time t1, the specified voltage VDIS is reached, and Recall, VPE and VNW are set to a high level H (Vcc). At this time, VccS, which is the SRAM power supply, is maintained at the GND potential. Therefore, BL, / BL, DT and / DT of the SRAM storage unit part may also have residual charge. Therefore, during the period from time t2 to t3, WL is set to a high level H, and BL, / BL, DT, / DT are discharged, so that BL, / BL, DT, / DT are low level L.

[0124] Next, from time t4 to t6, Recall and VPE are set to a negative voltage (VNRG, for example -3V), TP1 and TP2 are turned on, and the source of MP1 is grounded through T1 or the source of MP2 is grounded through T2. For example, when the data is "0", since VPE = VNRG, the P-type channel transistor MP1 with a threshold voltage Vth>VNRG is in the on state, and the P-type channel transistor MP2 with Vth<VNRG is in the off state, so DT is discharged to the GND potential through MP1, and / DT becomes electrically floating because MP2 is in the off state.

[0125] When VccS rises at time t5 during the period from time t4 to t6 and exceeds the operating voltage of the SRAM memory cell part, since P2 and N1 of the SRAM memory cell part are in the on state and P1 and N2 are in the off state, DT is discharged to a low level L and / DT is charged to a high level H. From time t6 to time t7, when Recall and VPE switch from VRNG to Vcc, DT in the SRAM memory cell part is a low level L and / DT is a high level H.

[0126] Therefore, when the data is "0", the state of the non-volatile memory part is MP1 in the programming state and MP2 in the erasing state, MP1 transfers the data "0" (DT is low level L, / DT is high level H) to the SRAM storage unit part, and the read back operation ends.

[0127] In this way, the non-volatile storage unit part transmits the data "0" to the SRAM storage unit part, so that the data stored in the non-volatile memory is "0", and the subsequent SRAM operation can be started.

[0128] In some embodiments, in the embodiments of the present application, since the SRAM storage unit part is a CMOS structure, the discharge operation based on WL being a high level H during the period from time t2 to t3 can also be omitted.

[0129] Next, the storage operation of the embodiment of the present application is described. In addition to the above-mentioned read-back operation, the SRAM operation also sets Recall to a low level L, and VPE and VNW are both set to Vcc. Under this potential setting, MP1 and MP2 are both in the off state, so no potential is provided to the memory nodes DT and / DT of the SRAM storage unit part. In addition, the memory retention of MP1 and MP2 will not be affected.

[0130] In some embodiments, a storage operation may be initiated when the Vcc supply voltage drops below a specified voltage. Fig.12 At time t8, it is detected that the power supply voltage drops to the specified voltage (VSW). Before time t9, WL is first at the low level L, BL and / BL are discharged and set to the low level L, and then VPE starts to be set to a negative voltage. As a result, the voltages of the nodes DT and / DT of the SRAM memory cell part are maintained (for example, when the data is "0", DT is at the low level L and / DT is at the high level H).

[0131] Next, during the period from t9 to t10, a negative high voltage VNEG (e.g. -12V) is applied to VPE, and a positive high voltage VPEW (e.g. +4V) is applied to VNW. Thus, electrons are extracted from the floating gates of MP1 and MP2 through the FN tunneling (Fowler-Nordheim tunneling) phenomenon, and the threshold voltage Vth of MP1 is negatively shifted, and the threshold voltage Vth of MP2 is negatively shifted, that is, the erase state operation is realized.

[0132] Next, during the period from time t10 to t11, the voltage for the erase state operation is reset, and then, for the program state operation, VPE is set to GND (from VNEG) and then to Vcc. In addition, VNW is set from VPEW to Vcc.

[0133] Next, during the period from time t11 to t12, a positive high voltage VPPG (e.g., +12V) is applied to VPE, and a positive low voltage VPPW (e.g., +4V) is applied to VNW to start the programming state operation. At this time, the drain of MP1 is connected to DT, which is at a low level L. Therefore, due to the band-to-band tunneling (BTBT) effect, electrons are injected into the floating gate, and the threshold voltage Vth of MP1 is positively shifted, that is, the programming state operation is realized. On the other hand, since the / DT connected to the drain of MP2 is at a high level, the BTBT phenomenon will not be caused, so the threshold voltage Vth of MP2 will not shift, and the threshold voltage Vth in the erased state remains unchanged.

[0134] On the other hand, since the / DT connected to the drain of MP2 is at a high level, the BTBT phenomenon will not occur, so the threshold voltage Vth of MP2 will not shift, and the threshold voltage Vth in the erased state remains unchanged, so that the data "0" of the SRAM memory cell part is transferred to the non-volatile memory part. In other words, even if the data in the SRAM memory cell part is lost after the Vcc power supply further drops and the VccS power supply drops (after time t13), the data "0" will still be retained in the non-volatile memory cell transistors MP1 and MP2 as the threshold voltage of MP1 and MP2 (MP1 is in the programmed state, and MP2 is in the erased state).

[0135] Fig.13 A cross-sectional view of a storage unit of another non-volatile semiconductor storage device having RAM operation and NVM characteristics provided in an embodiment of the present application. It should be noted that: Fig.13 It is mainly used to indicate the relative position relationship between the gate structure and the well, and does not constitute a restriction on the actual distance or size of the components in the memory cell. Fig.13 Will Fig.10The equivalent circuit diagram corresponds to the semiconductor structure of the nonvolatile semiconductor memory device memory. Fig.13 (exist Fig.13 Only MP1 is shown, or only MP2 is shown), the gate of the non-volatile memory cell transistor is a two-layer gate structure with a floating gate, and the other transistors are transistors with a single-layer gate structure.

[0136] In some embodiments, reference Fig.13 The memory cell of the nonvolatile semiconductor memory device provided in the embodiment of the present application is formed on a P-type substrate, the P-type channel transistors P1 and P2 of the SRAM memory cell part are formed in an N-type well (LV N-well) corresponding to low voltage operation, the N-type channel transistors N1, N2, A1, and A2 are formed in a P-type well (LV P-well) corresponding to low voltage operation, and the nonvolatile memory transistors MP1 and MP2 composed of P-type channel transistors and the N-type channel transistors T1 and T2 connected to the sources of the above MP1 and MP2 are all formed in an N-type well (HV N-well) corresponding to high voltage operation.

[0137] In some embodiments, reference Fig.13 The nonvolatile memory cell transistor constituting the memory cell has a double-layer gate structure including a floating gate, while the other transistors have a single-layer gate structure. Therefore, the height of the nonvolatile memory cell transistor from the silicon surface is different from the height of the other transistors from the silicon surface.

[0138] It should be noted that if the heights of the gates of the transistors in the memory cell are not consistent, it is difficult to process two gates of different heights at the same time during the manufacturing process of the gates. If they are processed separately, the distance between the transistors needs to be increased, which will lead to the problem of insufficient miniaturization. Fig.14 The non-volatile memory cell transistors that make up the memory cell have a double-layer gate structure, which includes a floating gate and a control gate. The other transistors also have a double-layer gate structure, and the control gate and the floating gate are short-circuited (electrically connected). This makes the height of all transistors in the memory cell the same (the height from the silicon substrate), so the gate processing conditions in the manufacturing process are also the same, and the size (area) of the memory cell can be further reduced.

[0139] In addition, since the non-volatile memory parts are all P-type transistors located in the same N-type well, compared with being arranged in different wells, the interval between the transistors can be reduced, which is conducive to further reducing the size of the storage unit.

[0140] In some embodiments, reference Fig.10 , Fig.12 and Fig.13 , or refer to Fig.10 , Fig.12 and Fig.14 , P1 and P2 of the SRAM storage cell part are set in a low voltage N-type well (LV N-well), N1, N2, A1, A2 are set in a low voltage P-type well (LVP-well), and the non-volatile memory parts MP1, MP2, T1 and T2 are all set in a high voltage N-type well (HV N-well). Therefore, the data of the SRAM storage cell part can be prevented from being destroyed by electrical interference, etc. by applying a high voltage to the N-type well (HV N-well) during the erase state operation and programming state operation of the non-volatile memory cell transistor.

[0141] In some embodiments, reference Fig.15 In the SRAM storage cell part, two P-type channel transistors in the six elements are located in the N-type well (LV N-well) with P-type wells (LV P-well) on both sides, and the N-type channel transistor elements N1, A1 and N2, A2 in the six elements of the SRAM storage cell part are arranged in the P-type well (LV P-well), and the P-type channel transistor of the non-volatile memory part and the N-type well (HV N-well) of the non-volatile memory transistor are formed outside the P-type well (LV P-well), and a group of dual elements is arranged in an N-type well (HV N-well) of the non-volatile memory part, and the group of dual elements can be MP1 and TP1, or MP2 and TP2.

[0142] Therefore, the N-type well (HV N-well) of the non-volatile memory cell transistor to which high voltage is applied is fully isolated from the N-type well (LV N-well) of the SRAM memory cell part, which can alleviate the electrical interference to the SRAM memory cell part caused by applying high voltage to the non-volatile memory cell transistor.

[0143] In addition, since the high voltage N-type well (HV N-well) is configured at the outermost side, in the process of arranging repeated memory cells to form a memory array, the N-type wells (HV N-well) of adjacent memory cells can be shared, thereby achieving more efficient memory cell configuration and higher integration.

[0144] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A non-volatile semiconductor memory device having RAM operation and NVM characteristics, characterized in that: A volatile RAM operation and a nonvolatile RAM data storage can be performed, and the nonvolatile semiconductor memory device comprises: A memory cell composed of 10 semiconductor elements, the memory cell including an SRAM memory cell portion composed of 6 semiconductor elements and a nonvolatile memory portion composed of 4 semiconductor elements; The non-volatile memory portion includes two groups of dual elements, each group of dual elements includes a non-volatile memory cell transistor and an N-type channel transistor connected in series, and each transistor in the dual elements is connected to the SRAM memory cell portion; the first dual element includes a first non-volatile memory cell transistor and a first N-type channel transistor, and the second dual element includes a second non-volatile memory cell transistor and a second N-type channel transistor; The non-volatile memory cell transistor is a P-type channel transistor, a charge storage layer including an insulating layer is provided above a channel region of the non-volatile memory cell transistor, and an insulating layer and a gate are sequentially stacked above the charge storage layer; The two groups of dual elements are respectively connected to the positive storage node and the negative storage node of the SRAM storage cell part; in the first dual element, one end of the first non-volatile storage cell transistor is connected to the positive storage node, the other end of the first non-volatile storage cell transistor is connected to one end of the first N-type channel transistor, and the other end of the first N-type channel transistor is connected to the ground potential; in the second dual element, one end of the second non-volatile storage cell transistor is connected to the negative storage node, the other end of the second non-volatile storage cell transistor is connected to one end of the second N-type channel transistor, and the other end of the second N-type channel transistor is connected to the ground potential; The charge storage layer comprises an insulating layer and a first floating gate which are stacked in sequence, and an insulating layer and a second control gate which are stacked in sequence are disposed above the first floating gate; The six semiconductor elements of the SRAM storage unit part are six element transistors, and there are insulating layers and second floating gates stacked in sequence above the channel regions of the six element transistors and above the channel region of the N-type channel transistor of the non-volatile memory part, and there is a second control gate above the second floating gate, and the second floating gate and the second control gate are electrically connected to each other.

2. The nonvolatile semiconductor memory device having RAM operation and NVM characteristics according to claim 1, wherein: The threshold voltage Vth of the nonvolatile memory cell transistor is a positive voltage in a programming state, and the threshold voltage Vth of the nonvolatile memory cell transistor is a negative voltage in an erasing state.

3. The non-volatile semiconductor memory device having RAM operation and NVM characteristics according to claim 1 or 2, characterized in that: In the SRAM storage unit part, one N-type well is used to set two P-type channel transistors, one P-type well is used to set two N-type channel transistors, and the two P-type wells are respectively located on both sides of one N-type well; In the nonvolatile memory portion, a P-type well is used to set an N-type channel transistor, and an N-type well is used to set a nonvolatile memory cell transistor. The two P-type wells of the nonvolatile memory portion are respectively located on the side of the two P-type wells of the SRAM memory cell away from the N-type well, and the two N-type wells of the nonvolatile memory portion are respectively located on the side of the two P-type wells of the nonvolatile memory portion away from the SRAM memory cell portion.

4. A non-volatile semiconductor memory device having RAM operation and NVM characteristics, characterized in that: A volatile RAM operation and a nonvolatile RAM data storage can be performed, and the nonvolatile semiconductor memory device comprises: A memory cell composed of 10 semiconductor elements, the memory cell including an SRAM memory cell portion composed of 6 semiconductor elements and a nonvolatile memory portion composed of 4 semiconductor elements; The nonvolatile memory portion includes two groups of dual elements, each group of dual elements includes a nonvolatile memory cell transistor and a P-type channel transistor connected in series, and each transistor of the dual elements is connected to the SRAM memory cell portion; the first dual element includes a first nonvolatile memory cell transistor and a first P-type channel transistor, and the second dual element includes a second nonvolatile memory cell transistor and a second P-type channel transistor; The non-volatile memory cell transistor is a P-type channel transistor, a charge storage layer including an insulating layer is provided above a channel region of the non-volatile memory cell transistor, and an insulating layer and a gate are sequentially stacked above the charge storage layer; The two groups of dual elements are respectively connected to the positive storage node and the negative storage node of the SRAM storage cell part; in the first dual element, one end of the first non-volatile storage cell transistor is connected to the positive storage node, the other end of the first non-volatile storage cell transistor is connected to one end of the first P-type channel transistor, and the other end of the first P-type channel transistor is connected to the ground potential; in the second dual element, one end of the second non-volatile storage cell transistor is connected to the negative storage node, the other end of the second non-volatile storage cell transistor is connected to one end of the second P-type channel transistor, and the other end of the second P-type channel transistor is connected to the ground potential; The charge storage layer comprises an insulating layer and a first floating gate which are stacked in sequence, and an insulating layer and a second control gate which are stacked in sequence are disposed above the first floating gate; The six semiconductor elements of the SRAM storage unit part are six element transistors, and there are insulating layers and second floating gates stacked in sequence above the channel regions of the six element transistors and above the channel region of the P-type channel transistor of the non-volatile memory part, and there is a second control gate above the second floating gate, and the second floating gate and the second control gate are electrically connected to each other.

5. The nonvolatile semiconductor memory device having RAM operation and NVM characteristics according to claim 4, wherein: The threshold voltage Vth of the nonvolatile memory cell transistor is a negative voltage in both a programming state and an erasing state.

6. The nonvolatile semiconductor memory device having both RAM operation and NVM characteristics according to claim 4 or 5, characterized in that: In the SRAM storage unit part, one N-type well is used to set two P-type channel transistors, one P-type well is used to set two N-type channel transistors, and the two P-type wells are respectively located on both sides of one N-type well; In the nonvolatile memory part, an N-type well is used to set a nonvolatile memory cell transistor and a P-type channel transistor, and the two N-type wells of the nonvolatile memory part are respectively located on the side of the two P-type wells of the SRAM memory cell away from the N-type well.

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