Heterojunction solar cell and preparation method thereof, photovoltaic module

Abstract

The present application relates to the field of solar cells, and specifically provides a heterojunction solar cell and a preparation method thereof, and a photovoltaic module, aiming to solve the problem of how to use LECO technology to improve the conversion efficiency of HJT cells. To this end, the cell of the present application includes: a substrate having a first surface and a second surface; a first intrinsic amorphous silicon layer, a first doped layer, and a first dielectric layer sequentially arranged on the first surface; a first anti-reflection layer, arranged on the first dielectric layer, and having an opening; a first gate line, arranged on the first dielectric layer through the opening of the first anti-reflection layer, and having a contact point with the first doped layer. Through the above-mentioned implementation, the TCO of the conventional HJT cell is changed to a structure of a dielectric layer + anti-reflection layer, and the anti-reflection layer has an opening, and the gate line can pass through the anti-reflection layer through the opening to be formed on the dielectric layer. Through the LECO technology, a contact point between the gate line and the doped layer can be formed, thereby improving the photoelectric conversion efficiency of the HJT cell.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a heterojunction solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] Laser Enhanced Contact Optimization (LECO) is a technology used to manufacture photovoltaic cells. It mainly forms a local photoconductive current between the gate line and the semiconductor-silicon body of the photovoltaic cell by adding voltage and laser. Since the electrode it produces has a nano-electrode structure, it can reduce the recombination loss between metal semiconductors, increase the open circuit voltage, reduce the contact resistance, and improve the conversion efficiency of photovoltaic solar cells.

[0003] At present, LECO technology has a significant effect on Tunnel Oxide Passivated Contact (TOPCon) cells and Passivated Emitter and Rear Cell (PERC) cells, but no significant effect has been found on heterojunction (HJT) cells. Therefore, how to use LECO technology to improve the conversion efficiency of HJT cells has become a technical problem that needs to be solved urgently by technicians in this field.

[0004] Accordingly, the art needs a new technical solution to solve the above problems. Summary of the invention

[0005] In order to overcome the above-mentioned defects, the present application is proposed to provide a heterojunction solar cell and a preparation method thereof, and a photovoltaic module that solves or at least partially solves the technical problem of how to use LECO technology to improve the conversion efficiency of HJT cells.

[0006] In a first aspect, a heterojunction solar cell is provided, comprising:

[0007] a substrate having a first surface and a second surface opposite to the first surface;

[0008] A first intrinsic amorphous silicon layer, a first doped layer and a first dielectric layer are sequentially disposed on the first surface;

[0009] A first anti-reflection layer, disposed on the first dielectric layer, and having an opening;

[0010] The first gate line is disposed on the first dielectric layer through the opening of the first anti-reflection layer and has a contact point with the first doping layer.

[0011] In one technical solution of the above heterojunction solar cell,

[0012] The first anti-reflection layer is one of a silicon nitride layer, a silicon oxide layer, a magnesium fluoride layer or a transparent conductive film layer;

[0013] Alternatively, the first anti-reflection layer is a composite layer formed by a transparent conductive film and one of silicon nitride, silicon oxide and magnesium fluoride.

[0014] In a technical solution of the above heterojunction solar cell, it also includes:

[0015] A second intrinsic amorphous silicon layer, a second doped layer and a second dielectric layer are sequentially disposed on the second surface;

[0016] A second anti-reflection layer, disposed on the second dielectric layer, and having an opening;

[0017] The second gate line is disposed on the second dielectric layer through the opening of the second anti-reflection layer and has a contact point with the second doping layer.

[0018] In a technical solution of the above heterojunction solar cell, it also includes:

[0019] A second intrinsic amorphous silicon layer, a second doped layer, a transparent conductive film layer and a second gate line are sequentially arranged on the second surface.

[0020] In one technical solution of the above heterojunction solar cell,

[0021] The first doping layer and the second doping layer have opposite doping types.

[0022] In a second aspect, the present application provides a method for preparing a heterojunction solar cell, the method comprising:

[0023] forming a first intrinsic amorphous silicon layer, a first doped layer and a first dielectric layer in sequence on a first surface of the substrate;

[0024] Forming a first anti-reflection layer having openings on the first dielectric layer, and forming a first gate line on the first dielectric layer through the openings of the first anti-reflection layer; or forming the first gate line on the first dielectric layer, and forming the first anti-reflection layer in a region of the first dielectric layer other than the first gate line;

[0025] A contact point is formed between the first gate line and the first doped layer.

[0026] In one technical solution of the above-mentioned method for preparing a heterojunction solar cell,

[0027] The first anti-reflection layer is one of a silicon nitride layer, a silicon oxide layer, a magnesium fluoride layer or a transparent conductive film layer;

[0028] Alternatively, the first anti-reflection layer is a composite layer formed by a transparent conductive film and one of silicon nitride, silicon oxide and magnesium fluoride.

[0029] In a technical solution of the above-mentioned method for preparing a heterojunction solar cell, forming a contact point between the first gate line and the first doping layer comprises:

[0030] Laser-assisted sintering is performed on the contact area between the first gate line and the first dielectric layer to form a micro-nano contact point between the first gate line and the first doping layer.

[0031] In a technical solution of the above-mentioned method for preparing a heterojunction solar cell, the method further comprises:

[0032] forming a second intrinsic amorphous silicon layer, a second doping layer, and a second dielectric layer in sequence on a second surface of the substrate opposite to the first surface;

[0033] Forming a second anti-reflection layer having openings on the second dielectric layer, and forming a first gate line on the second dielectric layer through the openings of the second anti-reflection layer; or forming the second gate line on the second dielectric layer, and forming the second anti-reflection layer in a region other than the second gate line on the second dielectric layer;

[0034] A contact point is formed between the second gate line and the second doped layer.

[0035] In a technical solution of the above-mentioned method for preparing a heterojunction solar cell, forming a contact point between the second grid line and the second doped layer comprises:

[0036] Laser-assisted sintering is performed on the contact area between the second gate line and the second dielectric layer to form a micro-nano contact point between the second gate line and the second doping layer.

[0037] In a technical solution of the above-mentioned method for preparing a heterojunction solar cell, the method further comprises:

[0038] A second intrinsic amorphous silicon layer, a second doping layer, a transparent conductive film layer and a second gate line are sequentially formed on a second surface of the substrate opposite to the first surface.

[0039] In a technical solution of the above-mentioned method for preparing a heterojunction solar cell, the doping types of the first doping layer and the second doping layer are opposite.

[0040] In a technical solution of the above-mentioned method for preparing a heterojunction solar cell, the substrate is single crystal silicon; the method further comprises:

[0041] Processing the first surface to form a suede structure;

[0042] The second surface is processed to form the suede surface structure or the polished surface structure.

[0043] In a third aspect, the present application provides a photovoltaic module, comprising at least one cell string, wherein the cell string comprises at least two heterojunction solar cells as described in any one of the technical solutions of the above-mentioned heterojunction solar cells.

[0044] The above one or more technical solutions of the present application have at least one or more of the following beneficial effects:

[0045] In the technical solution for implementing the present application, the structure of the heterojunction solar cell is transformed, and the transparent conductive film layer (Transparent Conductive Oxide, TCO) of the conventional heterojunction solar cell is changed to a dielectric layer + anti-reflection layer structure, and the anti-reflection layer has an opening, and the grid line can pass through the anti-reflection layer through the opening to be formed on the dielectric layer. Furthermore, through the LECO technology, instantaneous high temperature can be generated in the contact area between the bottom of the grid line and the dielectric layer, and partial shuttling of the special slurry can be achieved, and finally the contact point between the grid line and the doping layer is formed, so that the heterojunction solar cell is suitable for the efficiency improvement mechanism of the LECO technology, and the photoelectric conversion efficiency is improved. At the same time, the use of TCO can be saved and the process cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The disclosure of the present application will become easier to understand with reference to the accompanying drawings. It is easy for those skilled in the art to understand that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present application. Among them:

[0047] Figure 1 is a schematic structural diagram of a portion of a heterojunction solar cell according to an embodiment of the present application;

[0048] Figure 2 is a schematic structural diagram of a heterojunction solar cell according to an embodiment of the present application;

[0049] Figure 3 is a schematic structural diagram of a heterojunction solar cell according to another embodiment of the present application;

[0050] Figure 4 It is a schematic flow chart of the main steps of a method for preparing a heterojunction solar cell according to an embodiment of the present application;

[0051] Figure 5 is a schematic structural diagram of a heterojunction solar cell after forming a first dielectric layer according to an embodiment of the present application;

[0052] Figure 6 It is a schematic structural diagram of a heterojunction solar cell after forming a first anti-reflection layer and a first grid line according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0054] In the description of the present application, the terms "first" and "second" are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one such feature. In addition, in the present application, unless otherwise clearly specified and defined, the terms "connected" and "connected" shall be understood in a broad sense, for example, it may be directly connected or indirectly connected through an intermediate medium, it may be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0055] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0056] As described in the background technology, Laser Enhanced Contact Optimization (LECO) is a technology used to manufacture photovoltaic cells. It mainly forms a local photoconductive current between the gate line and the photovoltaic semiconductor-silicon body by adding voltage and laser. Since the electrode it produces has a nano-electrode structure, it can reduce the composite loss between metal semiconductors, increase the open circuit voltage, reduce the contact resistance, and improve the conversion efficiency of photovoltaic solar cells.

[0057] The main principles of LECO technology include the following three aspects:

[0058] 1. Use laser-induced local charge flow effect to induce thermal migration of electrode materials to the interface of semiconductor silicon materials;

[0059] 2. Induce physical diffusion and electrochemical reaction of silver colloidal particles in the gate line paste through the isolation layer;

[0060] 3. Produce micro-nano-level interlaced fusion between electrode materials / passivation layers / semiconductors.

[0061] At present, LECO technology has significantly improved the efficiency of TOPCon cells and PERC cells. Especially for TOPCon cells, LECO technology has begun to replace the Selective Emitter (SE) technology to achieve higher efficiency. According to statistics, after the TOPCon cell is superimposed with LECO technology, the conversion efficiency can be increased by 0.2%-0.5%.

[0062] However, LECO technology has not yet had a significant effect on heterojunction HJT cells. In comparison, HJT cells have greatly reduced their efficiency advantage. Therefore, how to use LECO technology to improve the conversion efficiency of HJT cells has become a technical problem that needs to be solved urgently by technicians in this field.

[0063] In order to solve the above problems, the inventors found through research and development the reason why LECO technology has no effect on heterojunction HJT batteries. This is mainly because the gate line of the HJT battery is not in direct contact with silicon, but in contact with the TCO layer. The direct contact between the gate line and the TCO layer has a lower contact resistance, which cannot be further reduced. In addition, LECO technology relies on local heating of the laser to form contact points. Since there is no direct contact between the gate line and silicon, micro-nano structure contact cannot be achieved, and fusion between the gate line and silicon cannot be achieved, thereby failing to improve the conversion efficiency of the HJT battery.

[0064] Therefore, this application transforms the conventional HJT battery structure and uses LECO technology to improve the conversion efficiency of the HJT battery.

[0065] See attached Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a structure of a partial heterojunction solar cell according to an embodiment of the present application. Figure 1 As shown, it mainly includes a substrate 11 , a first intrinsic amorphous silicon layer 21 , a first doping layer 22 , a first dielectric layer 23 , a first anti-reflection layer 24 and a first gate line 25 .

[0066] The substrate 11 may be single crystal silicon, specifically N-type single crystal silicon, and its thickness may be 80 μm-180 μm. The substrate 11 has a first surface 12 and a second surface 13 opposite to the first surface. The first surface 12 is closer to the light-facing surface of the battery, and the second surface 13 is closer to the backlight surface of the battery. Furthermore, the first surface 12 may be a velvet structure, such as a pyramid velvet, an etched pit velvet, etc.; the second surface 13 may be a velvet structure or a polished surface structure.

[0067] The first intrinsic amorphous silicon layer 21 is arranged above the first surface 12, and its thickness can be 4-15nm. The first intrinsic amorphous silicon layer 21 has a good passivation effect on the crystalline silicon surface, which can greatly avoid the recombination of carriers, achieve a higher minority carrier lifetime and open circuit voltage, thereby improving the conversion efficiency of the battery.

[0068] The first doped layer 22 is disposed above the first intrinsic amorphous silicon layer 21. The first doped layer 22 may be a doped amorphous silicon layer, a doped microcrystalline silicon layer or a doped nanocrystalline silicon layer. The doped amorphous silicon layer, the doped microcrystalline silicon layer or the doped nanocrystalline silicon layer may be an N-type doped layer or a P-type doped layer, which may be obtained by doping amorphous silicon, microcrystalline silicon or nanocrystalline silicon with elements such as phosphorus or boron, and may have a thickness of 20-40 nm. The doped amorphous silicon layer, the doped microcrystalline silicon layer or the doped nanocrystalline silicon layer may form a PN junction, thereby reducing optical losses, and improving the fill factor and conversion efficiency of the battery.

[0069] The first dielectric layer 23 is disposed above the first doped layer 22. The first dielectric layer 23 may be any one of a silicon oxide film, a titanium oxide film, a silicon nitride film or an aluminum oxide film, and its thickness may be 1-15 nm. The first dielectric layer 23 enables the first gate line 25 to achieve micro-nano contact with the first doped layer 22 through LECO technology.

[0070] The first anti-reflection layer 24 is disposed above the first dielectric layer 23 and has openings, such as Figure 1 As shown, a plurality of openings may be provided on the first anti-reflection layer 24, and the thickness thereof may be 60nm-150nm.

[0071] Furthermore, in some embodiments, the first anti-reflection layer 24 may be one of a silicon nitride layer, a silicon oxide layer, a magnesium fluoride layer, or a transparent conductive film layer.

[0072] The transparent oxide in the transparent conductive film layer may be a material with high transparency and conductivity, such as tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide or boron-doped zinc oxide.

[0073] Specifically, when the first anti-reflection layer 24 is a silicon nitride layer, a silicon oxide layer or a magnesium fluoride layer, although the resistance between the electrodes is increased and the fill factor is reduced, the short-circuit current is increased, thereby improving the conversion efficiency of the battery.

[0074] When the first anti-reflection layer 24 is a transparent conductive film layer, the short-circuit current will be affected due to absorption of incident light. However, the transparent conductive film layer can improve the conductivity of the battery and increase the fill factor, thereby improving the conversion efficiency of the battery.

[0075] In some other embodiments, the first anti-reflection layer 24 may also be a composite layer formed by one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film.

[0076] When the first anti-reflection layer 24 is a composite layer formed by one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film, the relationship between the fill factor and the short-circuit current can be balanced, thereby improving the conversion efficiency of the battery.

[0077] Specifically, when the first anti-reflection layer 24 is a composite layer formed by one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film, it can be a laminated structure formed by one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film. It can also be a composite layer formed by a mixture of one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film, wherein silicon nitride, silicon oxide or magnesium fluoride and the transparent conductive film can be in any proportion, such as 50% each, which is not limited here.

[0078] The first anti-reflection layer 24 can reduce the reflectivity of light, increase light absorption, and also has protection and passivation effects.

[0079] The above is a further description of the first anti-reflection layer 24 .

[0080] The first grid line 25 is disposed on the first dielectric layer 23 through the opening of the first anti-reflection layer 24 and has a contact point with the first doping layer 22. The first grid line 25 is an important component of the metal electrode of the solar cell, and its main function is to collect and transmit photogenerated carriers, thereby realizing the conversion of solar energy into electrical energy.

[0081] In the present application, the contact point between the first gate line 25 and the first doping layer 22 can reduce the recombination loss between the metal semiconductor, increase the open circuit voltage, and reduce the contact resistance, thereby effectively improving the conversion efficiency of the photovoltaic solar cell.

[0082] In practical applications, the design of the first grid lines 25 has an important influence on the performance of the solar cell, so it is necessary to comprehensively consider factors such as the number, width, height and shape of the first grid lines 25 to achieve the best photoelectric conversion efficiency and output power.

[0083] The above is a description of the first surface 12 of the substrate. The second surface 13 will be described below.

[0084] In some embodiments, the second surface 13 of the substrate can have the same structure as the first surface 12 .

[0085] For details, see the attached Figure 2 , Figure 2 Schematic diagram of the structure of a heterojunction solar cell according to an embodiment of the present application. Figure 2 As shown, in addition to the substrate 11, the first intrinsic amorphous silicon layer 21, the first doped layer 22, the first dielectric layer 23, the first anti-reflection layer 24 and the first gate line 25, it also includes a second intrinsic amorphous silicon layer 31, a second doped layer 32, a second dielectric layer 33, a second anti-reflection layer 34 and a second gate line 35.

[0086] For the convenience and simplicity of description, the relevant description of the second intrinsic amorphous silicon layer 31, the second doped layer 32, the second dielectric layer 33, the second anti-reflection layer 34 and the second gate line 35 on the second surface 13 can refer to the description of the first intrinsic amorphous silicon layer 21, the first doped layer 22, the first dielectric layer 23, the first anti-reflection layer 24 and the first gate line 25 on the above-mentioned first surface 12, and will not be repeated here.

[0087] In other embodiments, the second surface 13 of the substrate may have the same structure as a conventional HJT cell.

[0088] For details, see the attached Figure 3 , Figure 3 is a schematic diagram of the structure of a heterojunction solar cell according to another embodiment of the present application. Figure 3 As shown, in addition to the substrate 11, the first intrinsic amorphous silicon layer 21, the first doped layer 22, the first dielectric layer 23, the first anti-reflection layer 24 and the first gate line 25, it also includes a second intrinsic amorphous silicon layer 31, a second doped layer 32, a transparent conductive film layer 36 and a second gate line 35.

[0089] For the convenience and simplicity of description, the relevant description of the second intrinsic amorphous silicon layer 31 and the second doped layer 32 on the second surface 13 can refer to the description of the first intrinsic amorphous silicon layer 21 and the first doped layer 22 on the first surface 12, and will not be repeated here.

[0090] The transparent conductive film layer 36 is disposed on the second doped layer 32. The transparent oxide in the transparent conductive film layer 36 may be a material with high transparency and conductivity such as tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide or boron-doped zinc oxide, and its thickness may be 50-100 nm. The transparent conductive film layer 36 can collect the current generated by the photovoltaic cell and transmit it to an external circuit.

[0091] The second grid lines 35 are arranged above the transparent conductive film layer 36, and their number can correspond to the first grid lines 25. The second grid lines 35 are an important component of the metal electrode of the solar cell, and their main function is to collect and transmit photogenerated carriers, thereby realizing the conversion of solar energy into electrical energy.

[0092] In practical applications, the design of the second grid lines 35 has an important influence on the performance of the solar cell, so it is necessary to comprehensively consider factors such as the number, width, height and shape of the second grid lines 35 so as to achieve the best photoelectric conversion efficiency and output power.

[0093] It should be noted that the second doping layer 32 on the second surface 13 and the first doping layer 22 on the first surface 12 have opposite doping types, that is, the first doping layer is an N-type doping layer and the second doping layer is a P-type doping layer, or the first doping layer is a P-type doping layer and the second doping layer is an N-type doping layer, so as to form an effective PN junction. Among them, the N-type doping layer is usually phosphorus doped into amorphous silicon, microcrystalline silicon or nanocrystalline silicon, and the P-type doping layer is usually boron doped into amorphous silicon, microcrystalline silicon or nanocrystalline silicon.

[0094] The above is the description of the second surface 13 of the substrate.

[0095] Through the above implementation, the structure of the HJT battery is modified, and the TCO of the conventional HJT battery is changed to a dielectric layer + anti-reflection layer structure, and the anti-reflection layer has an opening, and the gate line can pass through the anti-reflection layer through the opening to be formed on the dielectric layer, forming a contact point with the doping layer. By improving the contact between the gate line and the doping layer, the series resistance of the battery can be improved, thereby improving the fill factor and improving the photoelectric conversion efficiency.

[0096] The above is an explanation of the heterojunction solar cell provided in this application.

[0097] Furthermore, the present application also provides a method for preparing a heterojunction solar cell.

[0098] See attached Figure 4 , Figure 4 FIG. 1 is a schematic flow chart of the main steps of a method for preparing a heterojunction solar cell according to an embodiment of the present application. Figure 4 As shown, the method for preparing a heterojunction solar cell in the embodiment of the present application mainly includes the following steps S401 to S403.

[0099] Step S401: forming a first intrinsic amorphous silicon layer, a first doped layer and a first dielectric layer in sequence on a first surface of a substrate;

[0100] Step S402: forming a first anti-reflection layer having openings on the first dielectric layer, and forming a first gate line on the first dielectric layer through the first anti-reflection layer; or forming a first gate line on the first dielectric layer, and forming a first anti-reflection layer on a region of the first dielectric layer other than the first gate line;

[0101] Step S403: forming a contact point between the first gate line and the first doped layer.

[0102] The above steps S401 to S403 are further explained below.

[0103] In some embodiments, the substrate may be single crystal silicon, specifically N-type single crystal silicon, and its thickness may be 80 μm-180 μm.

[0104] Furthermore, the substrate can be processed. Specifically, the first surface 12 and the second surface 13 of the substrate 11 can be polished to remove the line marks and damage on the original single crystal silicon. Then, the first surface 12 and the second surface 13, or only the first surface 12, can be textured. Specifically, the anisotropic etching principle of alkali on silicon can be used to form a pyramid shape on the surface of the substrate to achieve the purpose of trapping light. Finally, the surface of the silicon wafer can be cleaned using a modified RCA cleaning process to remove organic, metal and other impurity contamination. A substrate with a double-sided velvet structure, or a substrate with a velvet structure on the first surface 12 and a polished surface structure on the second surface 13.

[0105] In some embodiments of the above step S401, chemical vapor deposition (CVD) may be performed on the first surface 12, such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) to form a first intrinsic amorphous silicon layer 21 on the first surface 12, and the thickness of the first intrinsic amorphous silicon layer 21 may be 4-15 nm.

[0106] For example, using PECVD equipment, silane (SiH 4 ), hydrogen (H 2 ) and other process gases are excited into a plasma state and react with each other, and finally a first intrinsic amorphous silicon layer 21 is deposited on the substrate surface in the form of a thin film.

[0107] Furthermore, a first doped layer 22 can be formed on the first intrinsic amorphous silicon layer 21 by using methods such as PECVD or LPCVD. Specifically, it can be a doped amorphous silicon layer, a doped microcrystalline silicon layer or a doped nanocrystalline silicon layer. The doped amorphous silicon layer, the doped microcrystalline silicon layer or the doped nanocrystalline silicon layer can be an N-type doped layer or a P-type doped layer, and its thickness can be 20-40nm.

[0108] For example, silane (SiH 4 ), hydrogen (H 2 ), carbon dioxide (CO 2 ) and diborane doping gas to deposit, to obtain a P-type doped amorphous silicon layer, a doped microcrystalline silicon layer or a doped nanocrystalline silicon layer, or, to introduce silane (SiH 4 ), hydrogen (H 2 ), carbon dioxide (CO 2 ) and phosphine doping gas are deposited to obtain an N-type doped amorphous silicon layer, a doped microcrystalline silicon layer or a doped nanocrystalline silicon layer.

[0109] Furthermore, the first dielectric layer 23 can be formed on the first doping layer 22 by chemical oxidation or PECVD. The first dielectric layer 23 can be any one of silicon oxide film, titanium oxide film, silicon nitride film or aluminum oxide film, and its thickness can be 1-15nm.

[0110] For example, when using chemical oxidation to make silicon oxide films, a suitable oxidant can be selected, such as hydrogen peroxide (H 2 O 2 ), nitric acid (HNO 3 ), sulfuric acid (H 2 SO 4 ) etc. These oxidants can react with silicon wafers to form silicon oxide films.

[0111] See attached Figure 5 , Figure 5 It is a schematic structural diagram of a heterojunction solar cell after forming a first dielectric layer according to an embodiment of the present application.

[0112] The above is a further description of step S401 , and the following is a further description of step S402 .

[0113] In some implementations of the above step S402 , a first anti-reflection layer 24 having openings may be firstly formed on the first dielectric layer 23 , and then the first gate lines 25 may be formed on the first dielectric layer through the openings of the first anti-reflection layer 24 .

[0114] The first anti-reflection layer 24 may be one of a silicon nitride layer, a silicon oxide layer, a magnesium fluoride layer or a transparent conductive film layer, or a composite layer of one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film. The thickness may be 60nm-150nm.

[0115] Specifically, when the first anti-reflection layer 24 is a silicon nitride layer, a silicon oxide layer or a magnesium fluoride layer, the silicon nitride layer, the silicon oxide layer or the magnesium fluoride layer may be deposited on the first dielectric layer 23 by using methods such as CVD or PECVD.

[0116] For example, using a tubular CVD device, ammonia (NH 3 ) and silane (SiH 4 ) is introduced into the reaction chamber for reaction to deposit a silicon nitride layer on the first dielectric layer 23.

[0117] When the first anti-reflection layer 24 is a transparent conductive film layer, physical vapor deposition (PVD) can be used to form the transparent conductive film layer on the first dielectric layer 23, wherein the transparent oxide in the transparent conductive film layer can be a material with high transparency and conductivity such as tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide or boron-doped zinc oxide.

[0118] For example, by using the principle of magnetron sputtering, materials such as tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide or boron-doped zinc oxide are deposited on the first dielectric layer 23 in the form of a thin film.

[0119] When the first anti-reflection layer 24 is a composite layer formed by one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film, it can be a laminated structure formed by one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film. It can also be a composite layer formed by mixing one of silicon nitride, silicon oxide and magnesium fluoride and a transparent conductive film.

[0120] Furthermore, when the first anti-reflection layer 24 is a laminated structure formed by a silicon nitride layer, a silicon oxide layer, and a magnesium fluoride layer and a transparent conductive film, a silicon nitride layer, a silicon oxide layer, or a magnesium fluoride layer may be deposited on the first dielectric layer 23 by a method such as CVD or PECVD, and then a transparent conductive film may be deposited on the silicon nitride layer, the silicon oxide layer, or the magnesium fluoride layer by a PVD method. Alternatively, a transparent conductive film may be deposited on the first dielectric layer 23 by a PVD method, and then a silicon nitride layer, a silicon oxide layer, or a magnesium fluoride layer may be deposited on the transparent conductive film by a method such as CVD or PECVD.

[0121] When the first anti-reflection layer 24 is a composite layer formed by mixing one of silicon nitride, silicon oxide and magnesium fluoride with a transparent conductive film, the functions of a CVD or PECVD device and the functions of a PVD device can be integrated into one device, and the composite layer can be deposited on the first dielectric layer 23 using the integrated device.

[0122] Furthermore, in some embodiments, a first anti-reflection layer 24 of a whole layer may be fabricated on the first dielectric layer 23 , and then the preset opening area of ​​the first anti-reflection layer 24 may be etched to form the first anti-reflection layer 24 with openings.

[0123] Specifically, the preset opening area can be laser-scribed first, such as using an excimer laser or a femtosecond laser system to accurately scribe on the first anti-reflection layer 24 as a guide for subsequent etching. Then, a chemical solution, such as a potassium hydroxide (KOH) solution, can be used to etch the preset area to form an opening. After etching, a cleaning solution can be used to clean the substrate to remove residual chemicals and damage caused by the laser.

[0124] In some other embodiments, a mask method may be used to directly form the first anti-reflection layer 24 having openings on the first dielectric layer 23 .

[0125] Specifically, a baffle may be used to shield the first dielectric layer 23 corresponding to the preset opening area, and then the first anti-reflection layer 24 may be deposited on the first dielectric layer 23 by the method described in the above embodiment to obtain the first anti-reflection layer 24 with openings.

[0126] Furthermore, after the first anti-reflection layer 24 with openings is manufactured, the first gate lines 25 can be manufactured on the first dielectric layer through the openings of the first anti-reflection layer 24 .

[0127] Specifically, the first grid lines 25 can be made by screen printing, that is, silver paste is printed on the first dielectric layer 23 through the openings of the first anti-reflection layer 24 using a fixed screen pattern. After the first grid lines 25 are cured, a circuit can be formed to effectively lead out the current generated by the battery.

[0128] It should be noted that in practical applications, the design of the first grid lines 25 has an important impact on the performance of the solar cell, so it is necessary to comprehensively consider factors such as the number, width, height and shape of the first grid lines 25 to achieve the best photoelectric conversion rate and output power.

[0129] The above is a further description of first forming the first anti-reflection layer 24 with openings on the first dielectric layer 23 , and then forming the first gate line 25 on the first dielectric layer through the openings of the first anti-reflection layer 24 .

[0130] In some other implementations of the above step S402 , the first gate line 25 may be firstly formed on the first dielectric layer 23 , and then the first anti-reflection layer 24 may be formed on the first dielectric layer 23 in the area other than the first gate line 25 .

[0131] Specifically, the first gate line 25 may be formed on the first dielectric layer 23 by screen printing, and then the first anti-reflection layer 24 may be formed on the first dielectric layer 23 except the first gate line 25 by masking.

[0132] For the convenience and simplicity of description, the relevant instructions for making the first gate line 25 on the first dielectric layer 23 by screen printing, and making the first anti-reflection layer 24 in the area other than the first gate line 25 on the first dielectric layer 23 by masking can be referred to the contents described in the above embodiments, and will not be repeated here.

[0133] See attached Figure 6 , Figure 6 It is a schematic structural diagram of a heterojunction solar cell after forming a first anti-reflection layer and a first grid line according to an embodiment of the present application.

[0134] The above is a further description of step S402 , and the following is a further description of step S403 .

[0135] In some implementations of the above step S403 , a laser-assisted sintering process may be performed on the contact region between the first gate line 25 and the first dielectric layer 23 to form a micro-nano contact point between the first gate line 25 and the first doping layer 22 .

[0136] Specifically, the substrate can be placed on a metal carrier in the LECO laser equipment. The front side of the carrier has a probe or a metal strip. The probe or the metal strip is brought into contact with the first gate line 25, and the voltage and power are controlled by a controller. At the same time, the laser is used to perform surface scanning or line scanning on the battery cell, which can generate an instantaneous high temperature (greater than 1000°C) in the contact area between the first gate line 25 and the first dielectric layer 23, thereby achieving partial shuttling of the special slurry of the first gate line 25, and finally achieving micro-nano contact and mutual dissolution between the first gate line 25 and the first doping layer 22.

[0137] The laser device may be an infrared continuous laser, the spot size of the laser scanning may be 120um, the speed may be 50m / s, the power may be 200W, and the voltage may be 11V.

[0138] It should be pointed out that the above examples of laser equipment and laser scanning related parameters are only schematic illustrations. In practical applications, those skilled in the art can make settings according to specific scenarios, and no limitation is made here.

[0139] Through the above steps S401 to S403, it can be obtained Figure 1 The structure of a partial heterojunction solar cell is shown, and the preparation method of the second surface 13 is further described below.

[0140] In some embodiments, when the second surface 13 and the first surface 12 of the substrate 11 have the same structure, the second surface 13 can be manufactured while the first surface 12 is manufactured.

[0141] That is, the first surface 12 and the second surface 13 of the substrate 11 are simultaneously manufactured through the above steps S401 to S403, and the Figure 2 A heterojunction solar cell is shown.

[0142] In some embodiments, when the second surface 13 and the first surface 12 of the substrate 11 have different structures, that is, the second surface 13 is provided with a second intrinsic amorphous silicon layer 31, a second doped layer 32, a transparent conductive film layer 36 and a second gate line 35, the first intrinsic amorphous silicon layer 21 and the first doped layer 22 of the first surface 12 and the first intrinsic amorphous silicon layer 21 and the first doped layer 22 of the second surface 13 can be simultaneously manufactured through the above-mentioned step S401.

[0143] It should be noted that the second doping layer 32 on the second surface 13 and the first doping layer 22 on the first surface 12 have opposite doping types, that is, the first doping layer is an N-type doping layer and the second doping layer is a P-type doping layer, or the first doping layer is a P-type doping layer and the second doping layer is an N-type doping layer, so as to form an effective PN junction. Among them, the N-type doping layer is usually phosphorus doped into amorphous silicon, microcrystalline silicon or nanocrystalline silicon, and the P-type doping layer is usually boron doped into amorphous silicon, microcrystalline silicon or nanocrystalline silicon.

[0144] Furthermore, a transparent conductive film layer 36 can be fabricated on top of the second doping layer 32. The transparent oxide in the transparent conductive film layer 36 can be a material with high transparency and conductivity such as tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide or boron-doped zinc oxide, and its thickness can be 50-100 nm.

[0145] Among them, when the first anti-reflection layer 24 is a transparent conductive film layer, a transparent conductive film layer 36 on the first surface 12 and the second surface 13 can be jointly manufactured through step S402. When the first anti-reflection layer 24 is not a transparent conductive film layer, after the first anti-reflection layer 24 is manufactured, a transparent conductive film layer 36 can be manufactured on the second doped layer 32 by PVD.

[0146] Furthermore, after the transparent conductive film layer 36 is manufactured, the second grid lines 35 can be manufactured by screen printing, and the number of the second grid lines 35 can correspond to the first grid lines 25. The second grid lines 35 are an important component of the metal electrode of the solar cell. In practical applications, the design of the second grid lines 35 has an important influence on the performance of the solar cell. Therefore, it is necessary to comprehensively consider factors such as the number, width, height and shape of the second grid lines 35 so as to achieve the best photoelectric conversion rate and output power.

[0147] Through the above steps, we can get Figure 3 A heterojunction solar cell is shown.

[0148] It should be pointed out that the above examples of preparation methods for each layer structure in the heterojunction solar cell structure are only schematic illustrations. In practical applications, those skilled in the art may select the above or other preparation methods according to specific scenarios, and no limitation is made here.

[0149] The above is an explanation of the method for preparing the heterojunction solar cell provided in the present application.

[0150] The present application transforms the structure of a heterojunction solar cell by changing the TCO of a conventional heterojunction solar cell into a dielectric layer + anti-reflection layer structure, and the anti-reflection layer has openings, and a grid line can pass through the anti-reflection layer through the openings to be formed on the dielectric layer. Furthermore, through the LECO technology, an instantaneous high temperature can be generated in the contact area between the bottom of the grid line and the dielectric layer, partial shuttling of a special slurry can be achieved, and finally a contact point between the grid line and the doping layer is formed, so that the heterojunction solar cell is suitable for the efficiency improvement mechanism of the LECO technology, thereby improving the photoelectric conversion efficiency, while saving the use of TCO and reducing the process cost.

[0151] The preparation method of the heterojunction solar cell provided by the present application is further described below through Examples 1-3:

[0152] Embodiment 1: The first dielectric layer on the first surface is a silicon oxide layer, the first anti-reflection layer is a silicon nitride layer, and the second surface is a conventional transparent conductive film layer.

[0153] (1) Polishing the substrate to remove line marks and damage; using the anisotropic etching principle of alkali on silicon, texturing the first surface to obtain a substrate with a pyramid textured surface structure on the first surface and a polished surface structure on the second surface;

[0154] (2) depositing a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a first doped layer, and a second doped layer on the first surface and the second surface respectively by PECVD to form a PN junction, wherein the first doped layer and the second doped layer have opposite doping types;

[0155] (3) depositing a silicon oxide layer on the first doped layer on the first surface by using PECVD, and depositing a silicon nitride layer on the silicon oxide layer;

[0156] (4) laser scribing the preset opening area on the silicon nitride layer, and etching the preset opening area using a KOH solution to form an opening;

[0157] (5) depositing a transparent conductive thin film layer on the second doped layer on the second surface by using PVD;

[0158] (6) performing screen printing to form a first gate line at the opening of the silicon nitride layer on the first surface and a second gate line on the transparent conductive film layer on the second surface;

[0159] (7) The contact area between the first gate line and the silicon oxide layer is processed by LECO technology to form a micro-nano contact point between the first gate line and the first doped layer.

[0160] Embodiment 2: The first dielectric layer on the first surface is a silicon nitride layer, the first anti-reflection layer is a transparent conductive film layer, and the second surface is a conventional transparent conductive film layer.

[0161] (1) Polishing the substrate to remove line marks and damage; using the anisotropic etching principle of alkali on silicon, texturing the first surface to obtain a substrate with a pyramid textured surface structure on the first surface and a polished surface structure on the second surface;

[0162] (2) depositing a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a first doped layer, and a second doped layer on the first surface and the second surface respectively by PECVD to form a PN junction, wherein the first doped layer and the second doped layer have opposite doping types;

[0163] (3) depositing a silicon nitride layer on the first doped layer on the first surface using PECVD;

[0164] (4) using PVD to deposit a first transparent conductive film layer on the silicon nitride layer on the first surface, and depositing a second transparent conductive film layer on the second doped layer on the second surface;

[0165] (5) laser scribing the preset opening area on the first transparent conductive film layer, and etching the preset opening area using a KOH solution to form an opening;

[0166] (6) performing screen printing to form a first grid line at the opening of the first transparent conductive film layer on the first surface, and forming a second grid line on the second transparent conductive film layer on the second surface;

[0167] (7) The contact area between the first gate line and the silicon nitride layer is processed by LECO technology to form a micro-nano contact point between the first gate line and the first doped layer.

[0168] Embodiment 3: The first surface and the second surface have the same structure, the first dielectric layer and the second dielectric layer are silicon nitride layers, and the first anti-reflection layer and the second anti-reflection layer are composite layers of silicon oxide and a transparent conductive film.

[0169] (1) Polishing the substrate to remove line marks and damage; using the anisotropic etching principle of alkali on silicon, texturing the first surface and the second surface to obtain a substrate with pyramid texture structures on both the first surface and the second surface;

[0170] (2) depositing a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a first doped layer, and a second doped layer on the first surface and the second surface respectively by PECVD to form a PN junction, wherein the first doped layer and the second doped layer have opposite doping types;

[0171] (3) depositing a silicon nitride layer on the first surface and the second surface respectively using PECVD;

[0172] (4) using an integrated device to deposit a combined layer of silicon oxide and a transparent conductive film on the silicon nitride layer on the first surface and the second surface respectively;

[0173] (5) laser scribing the preset opening area on the combined layer of the first surface and the second surface, and etching the preset opening area using a KOH solution to form an opening;

[0174] (6) performing screen printing to form first grid lines and second grid lines at the openings of the composite layer on the first surface and the second surface, respectively;

[0175] (7) The contact area between the first gate line and the combined layer and the contact area between the second gate line and the combined layer are processed by LECO technology to form a micro-nano contact point between the first gate line and the first doped layer and a micro-nano contact point between the second gate line and the second doped layer.

[0176] The above is the description of Examples 1-3.

[0177] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effect of the present application, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present application.

[0178] Furthermore, the present application also provides a photovoltaic module, which includes at least one cell string, and the cell string includes at least two heterojunction solar cells described in the above heterojunction solar cell embodiment.

[0179] The heterojunction solar cells can be connected together by serial welding, so that the electric energy generated by a single heterojunction solar cell can be collected for subsequent transmission. Of course, the heterojunction solar cells can be arranged at intervals or stacked together in a shingled form.

[0180] For example, the photovoltaic module further includes an encapsulation layer and a cover plate, wherein the encapsulation layer is used to cover the surface of the battery string, and the cover plate is used to cover the surface of the encapsulation layer away from the battery string.

[0181] Furthermore, the present application also provides a photovoltaic system, comprising the above-mentioned photovoltaic module.

[0182] Photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0183] So far, the technical solution of the present application has been described in conjunction with the preferred implementation modes shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the various technical features of the above-described embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A heterojunction solar cell, characterized in that: include: a substrate having a first surface and a second surface opposite to the first surface; A first intrinsic amorphous silicon layer, a first doped layer and a first dielectric layer are sequentially disposed on the first surface; A first anti-reflection layer, disposed on the first dielectric layer, and having an opening; The first gate line is disposed on the first dielectric layer through the opening of the first anti-reflection layer, and has a partial contact point with the first doping layer formed by laser assisted sintering technology.

2. The heterojunction solar cell according to claim 1, characterized in that: The first anti-reflection layer is one of a silicon nitride layer, a silicon oxide layer, a magnesium fluoride layer or a transparent conductive film layer; Alternatively, the first anti-reflection layer is a composite layer formed by a transparent conductive film and one of silicon nitride, silicon oxide and magnesium fluoride.

3. The heterojunction solar cell according to claim 1, characterized in that: Also includes: A second intrinsic amorphous silicon layer, a second doped layer and a second dielectric layer are sequentially disposed on the second surface; A second anti-reflection layer, disposed on the second dielectric layer, and having an opening; The second gate line is disposed on the second dielectric layer through the opening of the second anti-reflection layer and has a contact point with the second doping layer.

4. The heterojunction solar cell according to claim 1, characterized in that: Also includes: A second intrinsic amorphous silicon layer, a second doped layer, a transparent conductive film layer and a second gate line are sequentially arranged on the second surface.

5. The heterojunction solar cell according to claim 3 or 4, characterized in that: The first doping layer and the second doping layer have opposite doping types.

6. A method for preparing a heterojunction solar cell, characterized in that: The method comprises: forming a first intrinsic amorphous silicon layer, a first doped layer and a first dielectric layer in sequence on a first surface of the substrate; Forming a first anti-reflection layer having openings on the first dielectric layer, and forming a first gate line on the first dielectric layer through the openings of the first anti-reflection layer; or forming the first gate line on the first dielectric layer, and forming the first anti-reflection layer in a region of the first dielectric layer other than the first gate line; Laser-assisted sintering is performed on the contact area between the first gate line and the first dielectric layer, and the high temperature generated causes the slurry portion of the first gate line to pass through the first dielectric layer, thereby forming a contact point between the first gate line and the first doping layer.

7. The method for preparing a heterojunction solar cell according to claim 6, characterized in that: The first anti-reflection layer is one of a silicon nitride layer, a silicon oxide layer, a magnesium fluoride layer or a transparent conductive film layer; Alternatively, the first anti-reflection layer is a composite layer formed by a transparent conductive film and one of silicon nitride, silicon oxide and magnesium fluoride.

8. The method for preparing a heterojunction solar cell according to claim 6, characterized in that: The forming a contact point between the first gate line and the first doping layer comprises: Laser-assisted sintering is performed on the contact area between the first gate line and the first dielectric layer to form a micro-nano contact point between the first gate line and the first doping layer.

9. The method for preparing a heterojunction solar cell according to claim 6, characterized in that: The method further comprises: forming a second intrinsic amorphous silicon layer, a second doping layer, and a second dielectric layer in sequence on a second surface of the substrate opposite to the first surface; Forming a second anti-reflection layer having openings on the second dielectric layer, and forming a first gate line on the second dielectric layer through the openings of the second anti-reflection layer; or forming a second gate line on the second dielectric layer, and forming the second anti-reflection layer in a region other than the second gate line on the second dielectric layer; A contact point is formed between the second gate line and the second doped layer.

10. The method for preparing a heterojunction solar cell according to claim 9, characterized in that: The forming a contact point between the second gate line and the second doped layer comprises: Laser-assisted sintering is performed on the contact area between the second gate line and the second dielectric layer to form a micro-nano contact point between the second gate line and the second doping layer.

11. The method for preparing a heterojunction solar cell according to claim 6, characterized in that: The method further comprises: A second intrinsic amorphous silicon layer, a second doping layer, a transparent conductive film layer and a second gate line are sequentially formed on a second surface of the substrate opposite to the first surface.

12. The method for preparing a heterojunction solar cell according to claim 9 or 11, characterized in that: The first doping layer and the second doping layer have opposite doping types.

13. The method for preparing a heterojunction solar cell according to claim 9 or 11, characterized in that: The substrate is single crystal silicon; the method further comprises: Processing the first surface to form a suede structure; The second surface is processed to form the suede surface structure or the polished surface structure.

14. A photovoltaic module, characterized in that: The invention comprises at least one cell string, wherein the cell string comprises at least two heterojunction solar cells according to any one of claims 1 to 5.

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