Output tube substrate bias control device for single-inductor three-output power supply

Abstract

The present application relates to the field of power electronics and power supply technology, and discloses an output tube substrate bias control device for a single-inductor three-output power supply, including an output voltage detector, a time slot generator, a substrate bias controller, and a plurality of substrate bias switching switches. The output voltage detector is used to compare the magnitude relationship of the three output voltages and generate a state signal; the time slot generator receives the PWM control signal of the output power tube, generates a time slot signal based on the rising edge of the signal, and indicates the substrate bias adjustment moment; the substrate bias controller generates a control signal according to the state signal and the time slot signal, and controls the substrate bias of the output power tube to dynamically switch between the output tube switching point voltage, the ground voltage, and the corresponding output voltage; the substrate bias switching switch is connected to the output power tube substrate, and responds to the control signal to achieve precise switching. The present application has the advantages of simple structure, small footprint, and no introduction of additional dead time.

Description

Technical Field

[0001] The present application relates to the technical field of power electronics and power supply, and in particular to a substrate bias control technology of a single inductor multiple output (SITO) power supply. Background Art

[0002] Single-inductor triple output (SITO) switching power supply systems are becoming increasingly popular in consumer electronics. Compared to traditional single-output buck or boost switching power supplies, SITO technology not only achieves a smaller footprint, but also significantly reduces material costs. Due to these significant advantages, SITO technology is expected to gradually replace traditional buck technology in the field of consumer electronics.

[0003] In SITO systems, nMOS transistors are usually used as output power tubes because nMOS has higher electron mobility than pMOS, and pMOS cannot work effectively at low output voltages. However, when using nMOS as an output power tube, its substrate bias control faces technical challenges. If the substrate of nMOS is directly grounded, the body effect will increase its on-resistance, thereby reducing power efficiency. To prevent the body diode from turning on and leaking when nMOS is turned off, the substrate bias of nMOS needs to dynamically follow the lower potential between the output tube switching point VX2 and the output voltage Vo.

[0004] In traditional technology, an output power tube is realized by using two nMOS in a "back-to-back" configuration with a common source and a common substrate. This configuration automatically selects the low potential between VX2 and Vo. However, this method increases the chip area of ​​a single output power tube to four times the original. Another technology is to dynamically switch the substrate bias of the output tube, where the substrate bias switching signal is synchronized with the control signal PWM[1:3] of the output power tube. PWM[1:3] needs to wait for the substrate bias switching to be completed before it can be turned on, which increases the dead time between PWM and reduces the conversion efficiency of the power supply.

[0005] Therefore, there is an urgent need for an output tube substrate bias control technology that has a simple structure, occupies a small area, and does not introduce additional dead time. Summary of the invention

[0006] The purpose of the present application is to provide an output tube substrate bias control device for a single-inductor three-output power supply to solve the problems raised in the above background technology.

[0007] The present application discloses an output tube substrate bias control device for a single-inductor three-output power supply, the device comprising:

[0008] An output voltage detector, used to continuously compare the magnitude relationship among the first output voltage, the second output voltage and the third output voltage, and to generate a status signal in real time based on the comparison result;

[0009] A time slot generator, for receiving PWM control signals of three output power tubes and generating a time slot signal based on the rising edge timing of these signals, the time slot signal indicating a suitable switching timing to adjust the substrate bias voltage;

[0010] The substrate bias controller generates multiple groups of control signals according to the state signal and the time slot signal, and each group of signals is responsible for controlling the dynamic switching of the substrate bias of the corresponding output power tube between the output tube switching point voltage, the ground voltage and the corresponding output voltage;

[0011] A plurality of substrate bias switching switches are respectively connected to the substrate of each output power tube and respond to corresponding control signals to achieve accurate switching of substrate bias.

[0012] In a preferred example, the output voltage detector comprises:

[0013] Three comparators, wherein the first comparator is used to compare the first output voltage and the second output voltage, the second comparator is used to compare the second output voltage and the third output voltage, and the third comparator is used to compare the first output voltage and the third output voltage, and each comparator outputs a binary comparison result indicating the magnitude relationship between the corresponding two voltages;

[0014] An encoder is used to encode the output results of the three comparators to generate a state signal, which comprehensively reflects the relative magnitude relationship among the first output voltage, the second output voltage and the third output voltage.

[0015] In a preferred embodiment, the time slot generator includes:

[0016] The first, second, and third delay modules receive the control signals of the first, second, and third output power tubes respectively, and perform predetermined delay processing on these signals to reduce interference between the signals, and then output the corresponding first, second, and third trigger signals;

[0017] three OR gates, respectively performing a logic OR operation on the first and second trigger signals, the second and third trigger signals, and the third and first trigger signals, so as to generate first, second and third reset signals for respective resets;

[0018] The first, second and third D flip-flops respectively receive corresponding trigger signals as clock signals and receive corresponding reset signals as reset signals to control and output first, second and third time slot signals, wherein each time slot signal is used to indicate and control the optimal moment for switching the substrate bias of the corresponding output power tube.

[0019] In a preferred embodiment, the substrate bias controller is used to:

[0020] According to the status signal received from the output voltage detector, the highest voltage, the lowest voltage and the middle voltage among the three output voltages are identified and marked, and the output power tubes connected to these voltages are marked as high voltage tubes, low voltage tubes and middle voltage tubes accordingly;

[0021] Control the substrate bias of the high voltage tube directly connected to the specific output tube switching point voltage to operate at the highest voltage condition;

[0022] Control the substrate bias of the low voltage tube directly to the lowest voltage of the system to optimize power efficiency;

[0023] According to the received time slot signal and status signal, the substrate bias of the medium voltage tube is dynamically adjusted to switch between the intermediate voltage, the output tube switching point voltage and the ground voltage:

[0024] When it is necessary to switch from the lowest voltage to the highest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the intermediate voltage, the output tube switching point voltage and the ground voltage;

[0025] When it is necessary to switch from the highest voltage to the lowest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the intermediate voltage, the ground voltage and the output tube switching point voltage.

[0026] In a preferred embodiment, the substrate bias switching switch comprises:

[0027] A first switch group, comprising three switches, each of which is connected to the substrate of the first output power tube and is used to switch the substrate bias voltage between the first output voltage, the output tube switching point voltage and the ground voltage under the control of the first control signal group;

[0028] A second switch group, comprising three switches, each of which is connected to the substrate of the second output power tube and is used to switch the substrate bias voltage between the second output voltage, the output tube switching point voltage and the ground voltage under the control of the second control signal group;

[0029] A third switch group, comprising three switches, each of which is connected to the substrate of the third output power tube and is used to switch the substrate bias voltage between the third output voltage, the output tube switching point voltage and the ground voltage under the control of the third control signal group;

[0030] In each switch group, three switches are connected in parallel through electronic control logic, ensuring that only one switch is activated at any time, achieved through complementary control signals, thereby accurately controlling the dynamic adjustment of substrate bias to prevent voltage conflicts or short circuits.

[0031] In a preferred example, the working waveform of the time slot generator satisfies the following characteristics: the control signal PWM[1:3] of the output power tubes S1, S2, and S3 respectively generates the time slot signals Slot_1-2, Slot_2-3, and Slot_3-1 related thereto; when the rising edge moment of PWM[1] is delayed by the delay module delay1, the time slot signal Slot_1-2 is triggered, and the time slot signal Slot_3-1 is turned off; when the rising edge moment of PWM[2] is delayed by the delay module delay2, the time slot signal Slot_2-3 is triggered, and the time slot signal Slot_1-2 is turned off; when the rising edge moment of PWM[3] is delayed by the delay module delay3, the time slot signal Slot_3-1 is triggered, and the time slot signal Slot_2-3 is turned off; wherein the start of each time slot signal is triggered by the rising edge delay of the corresponding PWM signal, and the end is controlled by the rising edge of the next related PWM signal through the OR gate logic and the reset operation of the D flip-flop.

[0032] In a preferred example, the substrate bias controller is configured as follows:

[0033] According to the status signal received from the output voltage detector, the highest voltage, the lowest voltage and the middle voltage among the three output voltages are identified, and the three output power tubes connected to these voltages are marked as high voltage tube, low voltage tube and middle voltage tube accordingly;

[0034] Controlling the substrate bias of the high-voltage tube to be directly connected to the output tube switching point voltage so as to operate under the highest voltage condition;

[0035] Controlling the substrate bias of the low voltage tube to be directly connected to the lowest voltage of the system to optimize power efficiency;

[0036] According to the received time slot signal and state signal, the substrate bias of the medium voltage tube is dynamically adjusted to switch between the intermediate voltage, the output tube switching point voltage and the minimum voltage, wherein:

[0037] When switching from the lowest voltage to the highest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the intermediate voltage, the output tube switching point voltage and the lowest voltage;

[0038] When switching from the highest voltage to the lowest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the middle voltage, the lowest voltage and the output tube switching point voltage.

[0039] In a preferred embodiment, when the VX2 level switching sequence is high-medium-low, time slot signals Slot(HM), Slot(ML), Slot(LH) are generated, and the substrate bias VB(M) of the medium voltage tube S(M) is controlled to optimize the power conversion efficiency and avoid body diode conduction, specifically including:

[0040] When Slot(HM) is in the active state, i.e., during the period when VX2 changes from high level to medium level, the substrate bias voltage VB(M) of S(M) is set to its output voltage Vo(M) to ensure that no body diode conduction or body effect is caused during the conduction period of S(H) and when S(M) is subsequently turned on;

[0041] When Slot(ML) is in the active state, i.e., during the period when VX2 changes from the middle level to the low level, the substrate bias voltage VB(M) of S(M) is set to the middle voltage VX2 to ensure that no body effect is caused when S(M) is turned on, and no body diode conduction is caused when S(L) is subsequently turned on;

[0042] When Slot(LH) is in the active state, that is, during the period when VX2 changes from low level to high level, the substrate bias VB(M) of S(M) is set to ground to ensure that the body diode is not turned on when S(L) is turned on and when S(H) is turned on subsequently.

[0043] In a preferred example, the time slot generator generates time slot signals Slot(LM), Slot(MH), Slot(HL) according to the control signals of the output power tubes S(L), S(M) and S(H) and the output voltage state signal, and controls the substrate bias VB(M) of the medium voltage tube S(M) to optimize the power conversion efficiency and avoid body diode conduction when the VX2 level switching sequence is low-medium-high, specifically including:

[0044] When Slot(LM) is in the active state, i.e., during the period when VX2 changes from low level to medium level, the substrate bias voltage VB(M) of S(M) is set to the intermediate voltage VX2 to ensure that no body diode conduction or body effect is caused during the conduction period of S(L) and when S(M) is subsequently turned on;

[0045] When Slot(MH) is in the active state, i.e., during the period when VX2 changes from the middle level to the high level, the substrate bias voltage VB(M) of S(M) is set to its output voltage Vo(M) to ensure that no body effect is caused when S(M) is turned on, and no body diode conduction is caused when S(H) is subsequently turned on;

[0046] When Slot(HL) is in the active state, that is, during the period when VX2 changes from high level to low level, the substrate bias VB(M) of S(M) is set to ground to ensure that the body diode is not turned on when S(H) is turned on and when S(L) is turned on subsequently.

[0047] The implementation of the present application has the following technical differences and technical effects: n-type devices are used as output power tubes, and the substrate switching signal and the output power tube switching signal have a 90° phase difference, rather than synchronization. This design does not require a complex non-overlapping drive signal generator, nor does it introduce additional dead time. At the same time, the structure is simple and compact, effectively reducing the chip area, and will not have a negative impact on power efficiency.

[0048] More specifically, the embodiment of the present application uses an output voltage detector to compare and monitor the magnitude relationship of the three output voltages in real time, and generates a status signal to provide necessary information for subsequent substrate bias control, thereby ensuring the accuracy and real-time performance of the control process.

[0049] Furthermore, a time slot generator is used to receive the PWM control signal of the output power tube, and a time slot signal is generated based on the rising edge of the signal to indicate the appropriate switching time to adjust the substrate bias. This method avoids the problem of increased dead time caused by synchronization of the substrate bias switching signal with the PWM control signal in the traditional technology, and effectively improves the conversion efficiency of the power supply.

[0050] Furthermore, the substrate bias controller flexibly generates multiple groups of control signals according to the state signal and the time slot signal, and controls the substrate bias of each output power tube to dynamically switch between the output tube switching point voltage, the ground voltage and its corresponding output voltage. This targeted control strategy can optimize the performance of each output power tube under different working conditions, reduce the impact of the body effect on the on-resistance, and improve the power supply efficiency.

[0051] Furthermore, multiple substrate bias switching switches are respectively connected to the substrate of each output power tube, and respond to corresponding control signals to achieve accurate substrate bias switching. This distributed switch control structure has the characteristics of modularization and strong scalability, is easy to implement and integrate, and can effectively reduce the chip area.

[0052] Furthermore, in the output voltage detector, through the cooperation of three comparators and an encoder, the relative size relationship of the three output voltages can be comprehensively and accurately determined, laying a good foundation for subsequent state recognition and control decisions.

[0053] Furthermore, the time slot generator adopts a design that combines a delay module, logic operations and a D flip-flop, which can effectively reduce interference between signals and accurately control the optimal moment for switching the substrate bias of each output power tube, ensuring the reliability and stability of the switching process.

[0054] Furthermore, the substrate bias controller can dynamically optimize the substrate bias of the medium voltage tube under different switching scenarios by identifying and marking output power tubes of different voltage levels and implementing targeted substrate bias adjustment strategies according to status signals and time slot signals, thereby maximizing the overall efficiency of the power supply while ensuring functional correctness.

[0055] Furthermore, the substrate bias switching switch adopts a group design and realizes precise control and complementary operation of the switch through electronic control logic, which effectively prevents problems such as voltage conflict or short circuit, improves the reliability and safety of substrate bias switching, and simplifies the control complexity.

[0056] In summary, the output tube substrate bias control device proposed in the present invention realizes a single-inductor three-output power supply system with simple structure, small chip area, precise control, high efficiency and strong reliability through the coordinated work of output voltage detection, time slot generation, substrate bias control and switching switch, overcomes the shortcomings of traditional technology, and has significant technical advantages and application value.

[0057] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of this application are listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a structural schematic diagram of an output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0059] Figure 2 It is a schematic diagram of the structure of an output tube substrate bias switching switch of an output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0060] Figure 3It is a schematic diagram of the layout of an output tube substrate bias switching switch unit of an output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0061] Figure 4 It is a schematic diagram of the top-level layout of an output tube substrate bias switching switch of an output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0062] Figure 5 It is a schematic diagram of the structure of an output voltage detector of an output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0063] Figure 6 It is an output voltage detector state correspondence table of an output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0064] Figure 7 It is a schematic diagram of the structure of a time slot generator of an output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0065] Figure 8 It is a schematic diagram of the working waveform of the time slot generator of the output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0066] Fig. 9 It is a working flow chart of a substrate bias controller of an output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application.

[0067] Fig.10 It is a schematic diagram of the working waveform of the output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application when the VX2 level switching sequence is high-medium-low.

[0068] Fig.11 It is a schematic diagram of the working waveform of the output tube substrate bias control device for a single-inductor three-output power supply according to the first embodiment of the present application when the VX2 level switching sequence is low-medium-high. DETAILED DESCRIPTION

[0069] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0070] Description of some concepts:

[0071] Single-Inductor Triple-Output (SITO) switching power supply: a switching power supply topology that uses a single inductor to achieve three independently controllable outputs.

[0072] Output power tube: A key device responsible for controlling energy transmission and conversion in a switching power supply, usually implemented using a MOS tube.

[0073] Substrate bias: refers to the voltage applied to the substrate end of the MOS tube, which is used to adjust the threshold voltage and conduction characteristics of the device.

[0074] Output tube switching point voltage (VX2): refers to the common source node voltage of the output power tube, which changes with the switching state of the output power tube.

[0075] Body effect: A physical phenomenon in which changes in the substrate voltage of a MOS tube affect its threshold voltage and on-resistance.

[0076] Dead time: In order to avoid short circuit caused by the simultaneous conduction of the upper and lower bridge arm output power tubes, an interlocking delay time is introduced during the switching process of the two output power tubes.

[0077] PWM control signal: Pulse width modulation control signal, which controls the conduction time of the output power tube by adjusting the duty cycle of the signal, thereby adjusting the output voltage.

[0078] Status signal: A digital signal generated by the output voltage detector based on the magnitude relationship of the three output voltages, used to indicate the relative high and low states of each output voltage.

[0079] Time slot signal: A signal generated by the time slot generator according to the rising edge time of the PWM control signal, used to indicate the optimal time for substrate bias switching.

[0080] Substrate bias switching switch: A switching device used to dynamically switch the output power tube substrate bias between different levels, usually implemented using a MOS tube.

[0081] The following is a brief description of some of the innovative features of this application:

[0082] The present invention discloses a technology for controlling substrate bias voltage of output tubes of a single inductor triple output (SITO) power supply. The system includes the following main components:

[0083] Body Bias Switches: These switches are used to switch the body bias of the output power tubes between different voltage levels.

[0084] Body Bias Controller: This controller controls the substrate bias switching according to the state signal generated by the output voltage detector and the time slot signal of the time slot generator.

[0085] Output Voltage Detector (Vo Detector): Responsible for comparing the voltages of the three output channels (Vo[1], Vo[2], Vo[3]) and generating a state signal (State[2:0]) based on the magnitude relationship of these voltages.

[0086] Time Slot Generator: Generates a time slot signal based on the control signal (PWM[1:3]) of the output power tube. This signal determines when to update the substrate bias of the output power tube.

[0087] When the SITO power supply is in steady-state operation, the three output voltages will change in real time due to changes in the load current and the feedback network. The output voltage detector continuously monitors these changes and generates a status signal. The time slot generator responds to the control signals of the output power tubes S1 to S3 and generates a time slot signal to trigger the switching of the substrate bias.

[0088] The substrate bias controller uses the state signal and the time slot signal to generate a corresponding control signal to adjust the substrate bias of each output power tube. Specifically, the control signals φ1a, φ1b and φ1c are used to control the substrate bias switching of the first output power tube S1; the control signals φ2a, φ2b and φ2c are used to control the substrate bias switching of the second output power tube S2; and the control signals φ3a, φ3b and φ3c are used to control the substrate bias switching of the third output power tube S3. The substrate bias switching switch can select the substrate bias option as needed, including the output tube switching point voltage VX2, the ground voltage GND and the corresponding output voltage Vo[1:3].

[0089] Compared with the traditional multi-channel output power supply, a key innovation of the present invention is the 90° phase difference between the output tube substrate switching signal and the output tube switch signal. This unique configuration avoids the introduction of additional dead time, simplifies the circuit structure, and reduces the chip area without sacrificing power efficiency.

[0090] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0091] The first embodiment of the present application relates to an output tube substrate bias control device for a single-inductor three-output power supply. The structure thereof is first described as a whole. Figure 1 As shown, including:

[0092] The output voltage detector is used to continuously compare the magnitude relationship of the three output voltages Vo[1], Vo[2], and Vo[3], and generate a state signal State[2:0] in real time based on the comparison result;

[0093] A time slot generator, for receiving PWM control signals of three output power tubes and generating a time slot signal based on the rising edge timing of these signals, the time slot signal indicating a suitable switching timing to adjust the substrate bias voltage;

[0094] The substrate bias controller generates multiple groups of control signals according to the state signal State[2:0] and the time slot signal, and each group of signals is responsible for controlling the dynamic switching of the substrate bias of the corresponding output power tube between the output tube switching point voltage, the ground voltage and its corresponding output voltage;

[0095] A plurality of substrate bias switching switches are respectively connected to the substrate of each output power tube and respond to corresponding control signals to achieve accurate switching of substrate bias.

[0096] Optionally, the output voltage detector includes:

[0097] three comparators, wherein the first comparator is used to compare the output voltages Vo[1] and Vo[2], the second comparator is used to compare the output voltages Vo[2] and Vo[3], and the third comparator is used to compare the output voltages Vo[1] and Vo[3], and each comparator outputs a binary comparison result indicating the magnitude relationship between the corresponding two voltages;

[0098] An encoder is used to encode the output results of the three comparators to generate a state signal State[2:0], which comprehensively reflects the relative size relationship of the three output voltages Vo[1], Vo[2] and Vo[3].

[0099] Optionally, the time slot generator includes:

[0100] The first, second, and third delay modules receive the control signals of the first, second, and third output power tubes respectively, and perform predetermined delay processing on these signals to reduce interference between the signals, and then output the corresponding first, second, and third trigger signals;

[0101] three OR gates, respectively performing a logic OR operation on the first and second trigger signals, the second and third trigger signals, and the third and first trigger signals, so as to generate first, second and third reset signals for respective resets;

[0102] The first, second and third D flip-flops respectively receive corresponding trigger signals as clock signals and receive corresponding reset signals as reset signals to control and output first, second and third time slot signals, wherein each time slot signal is used to indicate and control the optimal moment for switching the substrate bias of the corresponding output power tube.

[0103] Optionally, the substrate bias controller is used to:

[0104] According to the status signal received from the output voltage detector, the highest voltage, the lowest voltage and the middle voltage among the three output voltages are identified and marked, and the output power tubes connected to these voltages are marked as high voltage tubes, low voltage tubes and middle voltage tubes accordingly;

[0105] Control the substrate bias of the high voltage tube directly connected to the specific output tube switching point voltage to operate at the highest voltage condition;

[0106] Control the substrate bias of the low voltage tube directly to the lowest voltage of the system to optimize power efficiency;

[0107] According to the received time slot signal and status signal, the substrate bias of the medium voltage tube is dynamically adjusted to switch between the intermediate voltage, the output tube switching point voltage and the ground voltage:

[0108] When it is necessary to switch from the lowest voltage to the highest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the intermediate voltage, the output tube switching point voltage and the ground voltage;

[0109] When it is necessary to switch from the highest voltage to the lowest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the intermediate voltage, the ground voltage and the output tube switching point voltage.

[0110] Optionally, the substrate bias switching switch includes:

[0111] A first switch group, comprising three switches, each of which is connected to the substrate of the first output power tube and is used to switch the substrate bias voltage between the first output voltage, the output tube switching point voltage and the ground voltage under the control of the first control signal group;

[0112] A second switch group, comprising three switches, each of which is connected to the substrate of the second output power tube and is used to switch the substrate bias voltage between the second output voltage, the output tube switching point voltage and the ground voltage under the control of the second control signal group;

[0113] A third switch group, comprising three switches, each of which is connected to the substrate of the third output power tube and is used to switch the substrate bias voltage between the third output voltage, the output tube switching point voltage and the ground voltage under the control of the third control signal group;

[0114] In each switch group, three switches are connected in parallel through electronic control logic, ensuring that only one switch is activated at any time, achieved through complementary control signals, thereby accurately controlling the dynamic adjustment of substrate bias to prevent voltage conflicts or short circuits.

[0115] Optionally, the working waveform of the time slot generator satisfies the following characteristics: the control signal PWM[1:3] of the output power tubes S1, S2, and S3 respectively generates the time slot signals Slot_1-2, Slot_2-3, and Slot_3-1 related thereto; when the rising edge moment of PWM[1] is delayed by the delay module delay1, the time slot signal Slot_1-2 is triggered, and the time slot signal Slot_3-1 is turned off at the same time; when the rising edge moment of PWM[2] is delayed by the delay module delay2, the time slot signal Slot_2-3 is triggered, and the time slot signal Slot_1-2 is turned off at the same time; when the rising edge moment of PWM[3] is delayed by the delay module delay3, the time slot signal Slot_3-1 is triggered, and the time slot signal Slot_2-3 is turned off at the same time; wherein the start of each time slot signal is triggered by the rising edge delay of the corresponding PWM signal, and the end is controlled by the rising edge of the next related PWM signal through the OR gate logic and the reset operation of the D flip-flop.

[0116] Optionally, the substrate bias controller is configured as:

[0117] According to the status signal received from the output voltage detector, the highest voltage, the lowest voltage and the middle voltage among the three output voltages are identified, and the three output power tubes connected to these voltages are marked as high voltage tube, low voltage tube and middle voltage tube accordingly;

[0118] Controlling the substrate bias of the high-voltage tube to be directly connected to the output tube switching point voltage so as to operate under the highest voltage condition;

[0119] Controlling the substrate bias of the low voltage tube to be directly connected to the lowest voltage of the system to optimize power efficiency;

[0120] According to the received time slot signal and state signal, the substrate bias of the medium voltage tube is dynamically adjusted to switch between the intermediate voltage, the output tube switching point voltage and the minimum voltage, wherein:

[0121] When switching from the lowest voltage to the highest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the intermediate voltage, the output tube switching point voltage and the lowest voltage;

[0122] When switching from the highest voltage to the lowest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the middle voltage, the lowest voltage and the output tube switching point voltage.

[0123] Optionally, when the VX2 level switching sequence is high-medium-low, time slot signals Slot(HM), Slot(ML), Slot(LH) are generated, and the substrate bias VB(M) of the medium voltage tube S(M) is controlled to optimize the power conversion efficiency and avoid body diode conduction, specifically including:

[0124] When Slot(HM) is in the active state, i.e., during the period when VX2 changes from high level to medium level, the substrate bias voltage VB(M) of S(M) is set to its output voltage Vo(M) to ensure that no body diode conduction or body effect is caused during the conduction period of S(H) and when S(M) is subsequently turned on;

[0125] When Slot(ML) is in the active state, i.e., during the period when VX2 changes from the middle level to the low level, the substrate bias voltage VB(M) of S(M) is set to the middle voltage VX2 to ensure that no body effect is caused when S(M) is turned on, and no body diode conduction is caused when S(L) is subsequently turned on;

[0126] When Slot(LH) is in the active state, that is, during the period when VX2 changes from low level to high level, the substrate bias VB(M) of S(M) is set to ground to ensure that the body diode is not turned on when S(L) is turned on and when S(H) is turned on subsequently.

[0127] Optionally, the time slot generator generates time slot signals Slot(LM), Slot(MH), Slot(HL) according to the control signals of the output power tubes S(L), S(M) and S(H) and the output voltage state signal State[2:0], and controls the substrate bias VB(M) of the medium voltage tube S(M) to optimize the power conversion efficiency and avoid body diode conduction when the VX2 level switching sequence is low-medium-high, specifically including:

[0128] When Slot(LM) is in the active state, i.e., during the period when VX2 changes from low level to medium level, the substrate bias voltage VB(M) of S(M) is set to the intermediate voltage VX2 to ensure that no body diode conduction or body effect is caused during the conduction period of S(L) and when S(M) is subsequently turned on;

[0129] When Slot(MH) is in the active state, i.e., during the period when VX2 changes from the middle level to the high level, the substrate bias voltage VB(M) of S(M) is set to its output voltage Vo(M) to ensure that no body effect is caused when S(M) is turned on, and no body diode conduction is caused when S(H) is subsequently turned on;

[0130] When Slot(HL) is in the active state, that is, during the period when VX2 changes from high level to low level, the substrate bias VB(M) of S(M) is set to ground to ensure that the body diode is not turned on when S(H) is turned on and when S(L) is turned on subsequently.

[0131] The above technical solution is further described below in conjunction with the accompanying drawings.

[0132] Figure 1 The figure shows the overall framework of an output tube substrate bias control device for a single-inductor three-output power supply proposed by the present invention, which mainly consists of the following parts:

[0133] 1. Input voltage (Vin) and voltage sources (VX1, VX2): These are the power input parts of the system, where Vin is the main input voltage source and VX1 and VX2 may be additional voltage points for specific functions.

[0134] 2. PWM switches (PWM[1], PWM[2], PWM[3]) and body bias switches: Each output channel has its own PWM switch and body bias switch, which control the switching behavior and body bias of the corresponding output tube.

[0135] 3. Output load (Load1, Load2, Load3): Each channel output is connected to a load, which is a typical setting in a power management system to provide power to different devices or circuits.

[0136] 4. Output voltage detector (Vo detector): This component is responsible for monitoring and comparing the voltage of each output channel (Vo[1], Vo[2], Vo[3]) and generating state signals State[2:0], which reflect the relative high and low of the output voltage.

[0137] 5. Body bias controller: Based on the status signal and time slot signal obtained from the output voltage detector, the controller adjusts the body bias of each output tube.

[0138] 6. Time slot generator: It generates time slot signals based on the PWM signal. These time slot signals are used to indicate when the substrate bias of the output power tube can be switched.

[0139] More specifically, Figure 1 The output tube substrate bias control device for a single-inductor three-output power supply mainly includes four modules: an output voltage detector, a time slot generator, a substrate bias controller and a substrate bias switching switch.

[0140] The output voltage detector is used to detect the magnitude relationship of the three output voltages Vo[1], Vo[2], and Vo[3] in real time, and generates a 3-bit state signal State[2:0] according to the comparison result.

[0141] The time slot generator receives the PWM control signals of the three output power tubes S1, S2, S3 and generates corresponding time slot signals. The rising edges of these time slot signals are used to trigger the switching moment of the substrate bias of the output power tubes.

[0142] The substrate bias controller takes the state signal State[2:0] and the time slot signal as input and generates 9 control signals φ1a-φ3c. φ1a, φ1b, φ1c are used to control the substrate bias switching of S1; φ2a, φ2b, φ2c are used to control the substrate bias switching of S2; φ3a, φ3b, φ3c are used to control the substrate bias switching of S3.

[0143] The substrate bias switching switch is directly connected to the substrates of the three output power tubes S1, S2, and S3, and can dynamically switch the power tube substrate bias between three levels (VX2, GND, Vo[1:3]) according to the control signal output by the substrate bias controller.

[0144] It can be seen that the device uses the real-time detection results of the output voltage and the time slot signal generated by the PWM signal to achieve adaptive switching control of the output power tube substrate bias. Compared with traditional technologies, this solution can avoid the introduction of additional dead time, and the circuit structure is relatively simple, which helps to improve the efficiency of the power supply and reduce the chip area.

[0145] Figure 2 The structure of the substrate bias switching system of an output tube (S1) in a single-inductor three-output power supply is shown. This system includes the output power tube S1 and three associated n-type MOS switches (SB1a, SB1b, SB1c). These switches dynamically adjust the substrate bias of S1 according to the control signal (ϕ1a, ϕ1b, ϕ1c). The specific composition and functions are as follows:

[0146] Output power tube S1: This element is the main switch tube, used to control the output voltage Vo[1] connected to its drain.

[0147] Substrate bias switches SB1a, SB1b, SB1c:

[0148] SB1a: Active when φ1a is high, connects S1's substrate bias VB1 to VX2, an intermediate voltage node of the power supply, to ensure that during the switch transition, the substrate potential is appropriate to the current voltage state.

[0149] SB1b: Active when φ1b is high, connects the substrate bias VB1 of S1 to the output voltage Vo[1], ensuring that under certain operating conditions, the substrate potential follows the output voltage, reducing leakage current or improving efficiency.

[0150] SB1c: Active when φ1c is high, grounds the substrate bias of S1. This is typically used when ensuring lowest power consumption or minimizing substrate effects.

[0151] This structure allows S1 to dynamically adjust its substrate bias according to voltage output requirements and power efficiency requirements under different operating conditions. This is an effective way to control substrate bias to optimize power device performance, especially for application scenarios where power conversion efficiency is very important.

[0152] More specifically, Figure 2 The specific circuit structure of the substrate bias switching switch of one of the output power tubes (taking S1 as an example) is given.

[0153] In this circuit, three N-type MOS tubes SB1a, SB1b, and SB1c are used to realize the switching function of the substrate bias of S1, and their sources and substrates are connected to the substrate bias terminal VB1 of S1.

[0154] The gate of SB1a is driven by the control signal φ1a, and the drain is connected to the switching node VX2 of the output power tube. When φ1a is at a high level, SB1a is turned on, and the substrate bias VB1 of S1 is connected to the VX2 node.

[0155] The gate of SB1b is driven by the control signal φ1b, and the drain is connected to the output voltage Vo[1] corresponding to S1. When φ1b is high, SB1b is turned on, and the substrate bias VB1 of S1 is connected to the output voltage Vo[1].

[0156] The gate of SB1c is driven by the control signal φ1c, and the drain is grounded GND. When φ1c is at a high level, SB1c is turned on, and the substrate bias voltage VB1 of S1 is connected to the ground.

[0157] In this embodiment, the three control signals φ1a, φ1b, and φ1c are generated by a substrate bias controller, which dynamically adjusts the signal according to the voltage state provided by the output voltage detector and the time slot signal of the time slot generator. These control signals accurately control the substrate bias VB1 of the first output power tube S1, switching between VX2 (intermediate voltage node), output voltage Vo[1], and ground voltage GND. Through this dynamic substrate bias adjustment, unnecessary conduction of the body diode is effectively avoided, because the optimized adjustment of the substrate bias can significantly reduce the internal resistance of the power tube when it is turned on. This not only reduces energy loss, but also improves the conversion efficiency of the overall power supply.

[0158] also, Figure 2 SB1a, SB1b, and SB1c in the circuit use NMOS tubes as substrate bias switches instead of PMOS tubes. This choice is based on the fact that NMOS tubes have lower on-resistance and better low-level transmission capability, making them more suitable for use in substrate bias control applications. The low on-resistance of NMOS tubes helps reduce power loss in the circuit and improve overall energy efficiency, while its good low-level processing capability ensures accurate and reliable voltage switching.

[0159] In short, if Figure 2 The circuit structure shown provides a simple and effective method for controlling the substrate bias voltage of the output stage power tube. Figure 1 Combined with the overall control framework described, this scheme can achieve adaptive substrate bias regulation to optimize the performance and efficiency of a single-inductor triple-output power supply.

[0160] Figure 3 This is a schematic diagram of the layout of the substrate bias switching switch, specifically for the layout of the output power tube S1 of the single-inductor three-output power supply and its related substrate bias switches SB1a and SB1b. This diagram shows the layout design of the integrated circuit in the power management system, as follows:

[0161] Output power tube S1: It occupies the center position in the layout and is used to control the output voltage Vo[1]. S1 controls the voltage connected to it through its gate, source and drain.

[0162] Substrate bias switches SB1a and SB1b:

[0163] SB1a: Located on the left side of the layout, it is used to connect the substrate bias of S1 to the intermediate voltage node VX2. This helps to keep the substrate of S1 at a stable potential under specific operating conditions to optimize performance and reduce power loss.

[0164] SB1b: Located on the right side of the layout, it is responsible for connecting the substrate bias of S1 to the output voltage Vo[1]. This is usually used to keep the substrate bias consistent with the output voltage when the output voltage is stable, thereby improving efficiency and reducing leakage current.

[0165] Connection and layout design:

[0166] The power supply tube S1 and the substrate bias switches SB1a and SB1b are arranged in a linear side-by-side layout. Such a design helps to maximize the utilization of the layout space and reduce the manufacturing cost.

[0167] The black and white stripes in the layout represent different metal layers or conductive pathways, which are the circuit paths used to connect various components.

[0168] This layout design ensures that all relevant power management components are tightly and efficiently integrated on a single chip, which is critical to ensuring the power efficiency and stability of the device. By optimizing the connection between the gate, source and drain, this design aims to reduce resistance and capacitance effects, thereby improving overall power efficiency.

[0169] More specifically, Figure 3 The integrated layout of the output power tube S1 and its substrate bias switching switches SB1a and SB1b is shown. In this layout, S1, SB1a, and SB1b are arranged in the same N-well to form an integrated layout unit. This arrangement places the main power tube S1 in the center of the unit, while the two substrate switches SB1a and SB1b are symmetrically placed on both sides.

[0170] S1 shares a P-substrate with SB1a and SB1b. This shared configuration conveniently connects their substrates together and helps reduce circuit parasitics and simplify wiring complexity. In addition, the gate fingers of S1 and the gate fingers of SB1a and SB1b are arranged in staggered parallel, with a gate width ratio of n, where n is usually between 10 and 20. This design balances the on-resistance and switch duty cycle requirements.

[0171] Inside the cell, S1 and SB1a are connected to the VX2 voltage node through metal connections, while SB1b is connected to the Vo1 voltage node. VX2 and Vo1 voltages are brought out through the top metal layer to optimize wiring flexibility and reduce parasitic inductance. At the same time, the P wells of SB1a and SB1b are also connected to a common P-type substrate ring to control the substrate bias of the entire cell.

[0172] The main advantages of this layout include: more compact substrate connection and smaller parasitic parameters; the main power tube is located in the middle, and the substrate switches are symmetrically distributed, forming good matching and symmetry; the staggered arrangement of gate fingers simplifies the gate connection and helps to reduce the gate resistance; the top metal leads to VX2 and Vo1, making the wiring more flexible and the parasitic inductance smaller.

[0173] Of course, this is just one possible layout implementation method. In actual design, more comprehensive consideration and optimization are required based on process technology, power supply specifications, chip area and other factors. Figure 3 The layout shown provides a reference solution that balances wiring compactness, electrical performance, and layout symmetry.

[0174] Figure 4The top-level layout design is shown, especially for the array arrangement of the output power tube S1 and its substrate bias switch SB1c in the single-inductor three-output power supply system. The layout design of this diagram shows how to organize multiple S1 output power tubes on the chip and how to implement substrate bias control. The specific instructions are as follows:

[0175] S1 array: shows the arrangement of multiple output power tubes S1 on the chip. This arrangement allows multiple output power tubes to be implemented in a smaller space, which helps to improve the overall functional density and performance of the chip.

[0176] Connections to Vo[1] and VX2: Each S1 output power transistor is connected to the output voltage Vo[1] and the intermediate voltage node VX2 through a dedicated path. These connections ensure proper distribution and regulation of the voltage to support a variety of load conditions.

[0177] Substrate bias switch SB1c: Located at the bottom of the layout, connected to all S1 output power tubes. SB1c is mainly used to connect the substrate bias of S1 to ground (ground), which helps to keep the power tube stable and safe under specific working conditions, such as when the power is extremely low.

[0178] VB1 label: represents the connection from SB1c to the S1 array, which is the substrate bias supply line for S1. VB1 is usually dynamically controlled by one or more substrate bias switches to optimize the operating efficiency and power handling capability of S1.

[0179] This top-level layout design takes full advantage of integrated circuit technology to enhance the overall efficiency and performance of the power management system by reducing component spacing and optimizing wiring. This design enables high integration on the chip while providing the necessary electrical performance and thermal management.

[0180] More specifically, Figure 4 The complete layout of the output power tube S1 and its supporting substrate bias switching switches SB1a, SB1b, and SB1c is shown. Figure 3 The basic layout unit in the PCB is to form a neat matrix sub-array by arranging multiple units in a regular manner horizontally and vertically, which effectively improves the utilization rate of the layout area and ensures the consistency and matching between the units.

[0181] IO pins are reserved at the edge of the layout for connection to external circuits. The key voltage nodes VX2 and Vo[1] are brought out through the "finger" structure of the top metal layer. This structure is designed to achieve wider metal paths within the limited edge space, thereby reducing parasitic resistance and improving current transmission capability.

[0182] It is worth noting that the third substrate bias switch SB1c is not included in Figure 3 SB1c is not placed in the basic layout unit, but is arranged separately on one side of the entire S1 array. The drain of SB1c is connected to the P-type substrate ring of the S1 array through metal, and its source and substrate are directly grounded. This layout is mainly based on the consideration of layout area and connection convenience. Since SB1c has a short on-time and low on-resistance requirements, its area size is usually smaller than SB1a and SB1b, and it is more suitable for independent layout.

[0183] Figure 4 The layout scheme shows an optimized power tube array layout structure, whose main features include the use of array layout to improve area utilization and device matching, key nodes are led out through finger-shaped top metal to improve current transmission capability, and the third substrate switch is arranged independently to save area and simplify wiring. The overall layout shows good symmetry and regularity, which is conducive to improving production yield. The entire design takes into account both electrical performance and layout efficiency, and provides an efficient and practical layout reference for the output stage power tube of a single-inductor multi-output power supply.

[0184] It should be pointed out that Figure 4 The layout shown is only one possible implementation. The actual layout design needs to be more carefully optimized and adjusted in combination with specific process, performance, cost and other requirements. This flexibility allows technicians to customize the most suitable solution according to different manufacturing conditions and application scenarios, ensuring that the final product can meet the expected performance standards.

[0185] This design approach not only optimizes the function of the power supply unit, but also takes into account the overall integration and compatibility, ensuring the economy and practicality of the design. In addition, this layout scheme further improves the stability and reliability of the power supply system through fine electrical and physical layout optimization.

[0186] Figure 5 Describes an output voltage detection system for comparing and encoding three different output voltages Vo[1], Vo[2], and Vo[3] in a single-inductor three-output power supply system. This system uses three comparators (CMP1, CMP2, CMP3) and an encoder to generate a state signal State[2:0] that reflects the relative magnitude relationship between these voltages. The specific components and functions are as follows:

[0187] Comparator CMP1: Compares the output voltages Vo[1] and Vo[2]. If Vo[1] is greater than Vo[2], the output of CMP1 is high; otherwise, it is low.

[0188] Comparator CMP2: Compares the output voltages Vo[2] and Vo[3]. Its output reflects the comparison result between Vo[2] and Vo[3], also represented by a high or low level.

[0189] Comparator CMP3: Compares the output voltages Vo[3] and Vo[1]. The output of this comparator provides information about which is higher, Vo[3] or Vo[1].

[0190] Encoder: The outputs of the three comparators (C1, C2, C3) are combined into a three-bit state signal State[2:0]. This state signal encodes the magnitude relationship of the three output voltages and provides a decision basis for the control system, such as adjusting the substrate bias of the output tube or other power management operations.

[0191] For example, if the state signal State[2:0] is "100", this may mean that Vo[1] is the highest, Vo[2] is the lowest, and Vo[3] is in the middle. The specific encoding depends on the design and logic of the encoder. Such a system ensures that the power management system can dynamically adjust its output to cope with different load conditions, thereby optimizing overall power efficiency and performance.

[0192] More specifically, Figure 5 The internal structure diagram of the output voltage detector is shown. The key of this module is to monitor and compare the three output voltages Vo[1], Vo[2], and Vo[3] in real time. The output voltage detector mainly includes three comparators and an encoder:

[0193] Comparator CMP1 is responsible for comparing Vo[1] and Vo[2] and outputting the comparison result C[1].

[0194] Comparator CMP2 is responsible for comparing Vo[2] and Vo[3] and outputting the comparison result C[2].

[0195] Comparator CMP3 is responsible for comparing Vo[3] and Vo[1] and outputting the comparison result C[3].

[0196] These comparison results C[3:1] are then input into a 3-8 encoder. The encoder generates a three-bit state signal State[2:0] based on the combination of C[3:1]. This state signal can represent six possible output voltage magnitude relationships, as shown below:

[0197] 000: Vo[1]>Vo[2]>Vo[3]

[0198] 001: Vo[1]>Vo[3]>Vo[2]

[0199] 010: Vo[2]>Vo[1]>Vo[3]

[0200] 011: Vo[2]>Vo[3]>Vo[1]

[0201] 100: Vo[3]>Vo[1]>Vo[2]

[0202] 101: Vo[3]>Vo[2]>Vo[1]

[0203] The state signal State[2:0] is then used by the substrate bias controller to generate an appropriate substrate bias switching control signal for the current voltage state. This voltage detection scheme based on comparators and encoders is not only simple in structure and easy to implement, but also can quickly and in real time reflect the changes in the magnitude relationship of the three output voltages. By analyzing the state signal, the controller can easily determine which output voltage is the largest, and accordingly select the optimal substrate bias switching strategy, thereby optimizing the efficiency and dynamic responsiveness of the power supply.

[0204] Figure 7 A circuit design of a time slot generator for a single-inductor three-output power system is shown. This design is used to generate control signals to coordinate the switching timing between the output power tubes, reduce power loss and optimize the overall system performance. The following are the main components and working principles of the circuit:

[0205] 1) Delay module (delay1, delay2, delay3):

[0206] These modules receive control signals from the three output power transistors (PWM[1], PWM[2], PWM[3]) respectively.

[0207] Each delay module performs delay processing on its input signal and generates a delay trigger signal (PWM_trig1, PWM_trig2, PWM_trig3) to trigger the corresponding D flip-flop.

[0208] 2) Logic gates OR1, OR2, OR3:

[0209] Each OR logic gate is connected to the corresponding delay block output and another PWM signal to generate the reset signal (RST1, RST2, RST3).

[0210] These reset signals are used to reset the D flip-flops to ensure that the time slot signals are cleared at the appropriate time.

[0211] 3) D flip-flop (D1, D2, D3):

[0212] Each D flip-flop receives the trigger signal from the corresponding delay module as the clock signal (Clk) and receives the reset signal from the OR gate.

[0213] The output of the trigger (Slot_1-2, Slot_2-3, Slot_3-1) is used to indicate the switching time slots between the output power tubes. For example, Slot_1-2 indicates the switching time slot from S1 to S2, and so on.

[0214] Workflow:

[0215] When the rising edge of PWM[1] arrives, a delayed trigger signal PWM_trig1 is generated through delay1, which triggers D1 and generates the Slot_1-2 signal.

[0216] At the same time, OR1 keeps the RST1 signal at a low level until another PWM signal connected to it (such as PWM[3]) becomes high. At this time, the RST1 signal becomes high, resetting D1 and clearing the Slot_1-2 signal.

[0217] Similar logic applies to PWM[2] and PWM[3], which control the remaining two D flip-flops D2 and D3, and generate and manage the Slot_2-3 and Slot_3-1 signals.

[0218] This design effectively controls the substrate bias switching timing of each output power tube. Through precise time slot control, it can optimize the efficiency of the overall power supply, reduce cross interference, and improve the stability and response speed of the system.

[0219] More specifically, Figure 7 The internal logic structure of the substrate bias controller is shown. This module effectively generates the substrate bias switching control signal by integrating the output voltage state signal and the time slot signal. The substrate bias controller consists of three identical submodules, corresponding to the three output power tubes S1, S2, and S3. Taking S1 as an example, the generation of its control signals φ1a, φ1b, and φ1c involves the following steps:

[0220] First, each bit of the state signal State[2:0] and the time slot signal Slot[1] are ANDed through a series of AND gates to synchronize the state signal and the time slot signal, ensuring that the switching of the substrate bias occurs at the correct time point.

[0221] Then, the results of the AND operation are combined through three OR gates to generate three control signals φ1a, φ1b, and φ1c:

[0222] 1) When State[2:0] is 000 or 001, φ1a is high, and the substrate of S1 should be connected to VX2;

[0223] 2) When State[2:0] is 010 or 011, φ1b is high, and the substrate of S1 should be connected to Vo[1];

[0224] 3) When State[2:0] is 100 or 101, φ1c is high, and the substrate of S1 should be connected to ground.

[0225] Similar to S1, the generation process of substrate bias switching control signals φ2a / b / c and φ3a / b / c of ​​S2 and S3 follows the same logic, except that the time slot signals and state bits used are slightly different. This logic structure ensures the effective decoding and mapping of state signals and time slot signals, generates a complete set of switching control signals, and optimizes the timing of substrate bias switching.

[0226] Features of the substrate bias control logic include:

[0227] The state signal and the time slot signal are synchronized by using an AND gate to ensure the correct timing of substrate bias switching.

[0228] The state signal is decoded by using an OR gate, and the corresponding switching control signal is generated according to different state combinations;

[0229] The three submodules in the structure are exactly the same, with only slightly different input signals, which helps to simplify the design and layout and improve production efficiency;

[0230] The polarity of the control signal matches the conduction characteristic of the MOS tube, ensuring that the substrate bias switch can be directly driven, thereby improving the system response speed and reliability.

[0231] This substrate bias control logic takes into account the output voltage state and time slot information, and can dynamically adjust the substrate bias of each power tube, thereby effectively suppressing the body diode effect, reducing conduction loss, and improving the conversion efficiency of the power supply. At the same time, since the control logic circuit structure is simple and easy to integrate, it also helps to reduce chip area and cost.

[0232] This design not only improves the overall performance of the power system, but also enhances the stability of the system by optimizing the layout and reducing parasitic parameters. The simple structure of the controller also promotes the standardization of the design, allowing rapid deployment in different applications and ensuring power management efficiency in various working environments.

[0233] Figure 8 Shows the Figure 7 The waveforms of the control signals PWM[1], PWM[2], PWM[3] and the generated time slot signals Slot_1-2, Slot_2-3, Slot_3-1 related to the time slot generator described in the figure. These waveforms show how to generate the corresponding time slot signals through delay and logic processing based on the input PWM signal to ensure that the substrate bias switching between the output power tubes is carried out at the best time. The following is a detailed explanation of each signal waveform:

[0234] 1) PWM[1], PWM[2], PWM[3]:

[0235] These are the pulse width modulated signals that control the individual output power tubes.

[0236] The rising edge of each PWM signal triggers the corresponding delay module to generate a delay trigger signal for controlling the corresponding D flip-flop.

[0237] 2) Slot_1-2, Slot_2-3, Slot_3-1:

[0238] These time slot signals respectively represent the time window for switching from one output power tube to another output power tube.

[0239] Each time slot signal starts at the rising edge of the delay trigger signal after the rising edge of the corresponding PWM signal, and ends at the rising edge of the next related PWM signal, controlled by the reset operation of the OR logic gate and the D flip-flop.

[0240] Working principle:

[0241] Slot_1-2: After the rising edge of PWM[1], the delay trigger signal PWM_trig1 generated by the delay module delay1 is activated until the next rising edge of PWM[3] is reset through the OR logic gate RST1.

[0242] Slot_2-3: After the rising edge of PWM[2], the delay trigger signal PWM_trig2 generated by the delay module delay2 is activated until the next rising edge of PWM[1] is reset through the OR logic gate RST2.

[0243] Slot_3-1: After the rising edge of PWM[3], the delay trigger signal PWM_trig3 generated by the delay module delay3 is activated until the next rising edge of PWM[2] is reset through the OR logic gate RST3.

[0244] This design ensures that the substrate bias can be correctly switched within the appropriate time slot when switching between output power tubes, optimizing the performance of the power system and reducing power loss and electromagnetic interference.

[0245] More specifically, Figure 8 A schematic diagram of the internal structure of the time slot generator is given. This module is used to generate corresponding time slot signals according to the PWM control signal of the output power tube, which is used to synchronize the switching moment of the substrate bias.

[0246] The core of the time slot generator is three D-flip flops, corresponding to the three output power tubes S1, S2, and S3. The data input terminal D of the D-flip flops is connected to VCC, the enable terminal EN is connected to PWM[1:3], the reset terminal RN is connected to RST_N, and the clock terminal CLK is connected to a common clock signal CLK.

[0247] The working principle of the time slot generator is as follows:

[0248] 1) When RST_N is low, all D flip-flops are reset and the output Slot[1:3] are all low;

[0249] 2) When RST_N is high and PWM[1] is high when the clock rises, Slot[1] is set to high, marking the start of the conduction time slot of S1. Similarly, the high-level rising edges of PWM[2] and PWM[3] trigger Slot[2] and Slot[3] to go high, respectively, marking the start of the conduction time slot of S2 and S3.

[0250] 3) Once set high, Slot[1:3] will remain high until the next low-level reset of RST_N comes.

[0251] In other words, when the output power tube switches from S1 to S2, the time slot generator generates the time slot signal Slot_1-2; when the output power tube switches from S2 to S3, the time slot generator generates the time slot signal Slot_2-3; when the output power tube switches from S3 to S1, the time slot generator generates the time slot signal Slot_3-1. Among them, after the rising edge of PWM[1] is delayed by delay1, the time slot generator turns off Slot_3-1 and turns on Slot_1-2; after the rising edge of PWM[2] is delayed by delay2, the time slot generator turns off Slot_1-2 and turns on Slot_2-3; after the rising edge of PWM[3] is delayed by delay3, the time slot generator turns off Slot_2-3 and turns on Slot_3-1. This way of generating time slot signals can accurately control the optimal time for switching the substrate bias of each output power tube, ensuring the reliability and stability of the switching process.

[0252] It can be seen that the waveform of Slot[1:3] is actually sampling and delaying the rising edge of PWM[1:3], and the flip of the Slot signal is synchronized with the clock CLK. This method of generating time slot signals has the following characteristics:

[0253] 1) The D flip-flop is used to detect and latch the rising edge of the PWM signal, thereby generating a time slot signal;

[0254] 2) The time slot signal is synchronized with the clock, which helps to avoid glitches and metastable states and improves timing reliability;

[0255] 3) Once the time slot signal is set high, it will last for the entire switching cycle until it is reset, which ensures that the switching of the substrate bias matches the conduction time of the power tube;

[0256] 4) The reset signal RST_N provides a flexible mechanism to quickly terminate the time slot signal when needed and restore the substrate bias to its initial state.

[0257] The time slot signal Slot[1:3] will eventually be sent to the substrate bias controller and combined with the output voltage state signal State[2:0] to jointly determine the switching time and switching state of each power tube substrate bias. This time slot generation mechanism can effectively transmit the timing information of the PWM signal to the substrate bias control subsystem, thereby realizing dynamic and adaptive substrate bias adjustment, thereby improving the efficiency and dynamic response capability of the power supply.

[0258] Fig. 9 The substrate bias control process of a single-inductor three-output power supply is described. The main links involved include voltage detection, state determination, substrate bias setting, and the generation and application of time slot signals. This control process is used to optimize the substrate bias of each output channel to improve the efficiency and performance of the power supply.

[0259] Here is a detailed explanation of the steps:

[0260] 1) Start the process:

[0261] When the system starts running, it first determines the order of the three output voltages Vo[1], Vo[2], Vo[3] through the Vo detector and outputs the state code State[2:0].

[0262] 2) Set substrate bias based on status code:

[0263] According to the result of State[2:0], the corresponding substrate bias is set for the output power transistors S1 to S3:

[0264] If the voltage sequence is from high to low (H>M>L), the substrate bias of the output tube with the highest voltage is connected to VX2, the substrate bias of the output tube with the lowest voltage is connected to its output voltage Vo(L), and the output tube with medium voltage is switched within a specific time slot.

[0265] Conversely, if it is from low to high (L>M>H), the connection method of the substrate bias is appropriately adjusted to accommodate this change.

[0266] 3) Generate configuration time slot signal:

[0267] According to the PWM signal and the state code, time slot signals Slot_1-2, Slot_2-3, Slot_3-1 are generated to control the dynamic switching of the substrate bias.

[0268] 4) Time slot signal controls substrate bias:

[0269] Slot (LM), Slot (MH), Slot (HL) control the substrate bias of the intermediate voltage level output tube according to different time slot signals:

[0270] When Slot(LM) = 1, the substrate bias is connected to VX2.

[0271] When Slot(MH) = 1, the substrate bias is connected to its output voltage Vo(M).

[0272] When Slot(HL) = 1, the substrate bias is ground (GND).

[0273] Fig. 9 This paper describes how to dynamically adjust the substrate bias of the output power tube according to the real-time status of the output voltage, thereby ensuring that the power system can maintain optimal performance under various load conditions. In addition, by effectively managing the time slot signal, the substrate bias is ensured to switch correctly between different output tubes to avoid possible efficiency loss or power waste.

[0274] More specifically, Fig. 9 The timing waveforms of the three output voltages and related control signals in a complete switching cycle are shown. These waveforms show the working principle and coordination mechanism of the substrate bias control system in detail, allowing us to more clearly understand the dynamic regulation process of the system.

[0275] First, the switch control signals of the three output power tubes S1, S2, and S3 are provided by PWM[1:3]. These signals are turned on in sequence within a cycle and have a certain time overlap, realizing the quasi-resonant soft switching function. This design reduces the energy loss in the switching process and improves efficiency.

[0276] The time slot signal Slot[1:3] is generated by the rising edge of the PWM signal and is used to mark the conduction time slot of each power tube. The flip of these time slot signals lags slightly behind the PWM signal, mainly due to the delay effect of the D flip-flop in the time slot generator.

[0277] The state signal State[2:0] reflects the real-time magnitude relationship of the three output voltages Vo[1:3]. These signals change at different time periods according to changes in load conditions and switch states, thus providing continuous updates on the output voltage sequence.

[0278] The substrate bias control signal φ[1:3] is generated based on the results of Slot[1:3] and State[2:0]. For example, for S1, the φ1a, φ1b, φ1c signals determine whether its substrate bias should be connected to VX2, Vo[1], or ground, depending on the value of State[2:0]. This dynamic switching mechanism minimizes the body diode effect and conduction loss, thereby improving the efficiency of power conversion.

[0279] By comprehensively considering the output voltage state and time slot information, the substrate bias control system not only improves the conversion efficiency, but also takes into account the switch reliability and dynamic response capability. The timely switching of the control signal avoids the change of substrate bias at the moment of power tube opening, reduces the switching stress and possible current spikes, thereby protecting the power tube and improving the overall stability and reliability of the system.

[0280] Fig. 9 The timing diagram clearly shows the timing coordination and logic relationship of the substrate bias control system. Its main features include:

[0281] 1) The PWM signal accurately controls the switching timing of the power tube, while the Slot signal marks the specific conduction time slot of each power tube, which helps to accurately manage power conversion.

[0282] 2) The State signal reflects the magnitude relationship of the output voltage in real time, ensuring that the substrate bias is adjusted according to the actual voltage conditions, thereby enhancing the responsiveness and efficiency of the power supply.

[0283] 3) Dynamic generation of the φ signal based on a combination of Slot and State allows the system to adjust the substrate bias of each power tube according to real-time conditions and optimize the electrical characteristics during power conversion.

[0284] This adaptive substrate bias control strategy provides a novel approach for the optimization design of single-inductor multi-output power supplies. It not only improves the efficiency of power conversion, but also extends the life and stability of the system by reducing switching stress and current spikes.

[0285] The application of this method can be widely applied to various electronic systems that require efficient and reliable power management, especially in those applications that have strict requirements on power efficiency and response speed, such as mobile devices, computing equipment and industrial automation systems. By continuing to optimize these control strategies, the overall performance and economic benefits of the power system can be further improved, providing users with better power solutions.

[0286] Fig.10A time series diagram is shown, which details the conduction time of the output power tubes S(H), S(M), and S(L) in the single-inductor three-output power supply system, the optional configuration of the substrate bias, and the actual application status of the substrate bias. This figure clearly illustrates how the substrate bias of each power tube is configured in a specific time slot, and how it is dynamically adjusted as time and conditions change.

[0287] The main components and explanations are as follows:

[0288] 1) VX2, Vo(H), Vo(M), Vo(L), GND:

[0289] These lines represent different voltage levels, where VX2 is the middle voltage node, Vo(H), Vo(M), Vo(L) represent high, middle, and low output voltages respectively, and GND represents the ground line.

[0290] 2) S(H), S(M), S(L) on time:

[0291] These bars represent the conduction time of three different power tubes. S(H), S(M), and S(L) represent the output power tubes that control high, medium, and low voltages, respectively.

[0292] 3) Available body biases of S(M):

[0293] This row shows all the optional substrate bias settings for the medium voltage power tube S(M), including ground (GND), connection to its output voltage Vo(M), and connection to VX2.

[0294] 4) Configuration slot of S(M):

[0295] The setting of substrate bias of S(M) in different configuration time slots is described. The three main configuration time slots Slot(HM), Slot(ML) and Slot(LH) are marked in the figure, corresponding to the substrate bias switching from high to medium, from medium to low, and from low to high, respectively.

[0296] 5) VB(M):

[0297] This line shows the actual substrate bias voltage of S(M) during the whole time period. According to the time slot signal and the current voltage status, the substrate bias voltage of S(M) switches between GND, Vo(M) and VX2.

[0298] Working principle:

[0299] During the conduction period of each power tube, the substrate bias is adjusted according to the configuration time slot to minimize conduction losses and optimize performance.

[0300] For example, between t1 and t3, if S(H) is turned on, the substrate bias is usually set to VX2 (assuming that S(M) is in Slot(HM) at this time).

[0301] As the voltage state changes and the slot signal changes, the substrate bias of S(M) is dynamically adjusted in different time slots to adapt to the current power demand and system status.

[0302] Fig.10 An intuitive understanding is provided on how to dynamically adjust the substrate bias according to the conduction states and voltage levels of different power transistors, which is a key strategy to optimize the performance of SIMO power systems.

[0303] More specifically, Fig.10 The overall efficiency curve of the proposed single-inductor triple-output DC-DC converter is shown, and a detailed comparison is made with the traditional fixed substrate bias scheme. In the efficiency curve, the horizontal axis represents the output power, while the vertical axis shows the conversion efficiency, where the curve of the adaptive substrate bias control (AVSBC) scheme is generally higher than that of the traditional fixed substrate bias (FVSBC) scheme.

[0304] It is obvious from the figure that the AVSBC solution shows better efficiency under various output power conditions, especially under light load conditions, where the efficiency improvement is particularly significant. This is mainly because the AVSBC solution can dynamically adjust the substrate bias according to the real-time load, effectively reducing the on-resistance of the power tube, thereby greatly reducing the conduction loss. As the load increases, although the switching loss gradually dominates, the efficiency improvement of the AVSBC solution decreases, but it still maintains a significant advantage.

[0305] In addition, the AVSBC curve is relatively smooth when the output power changes, and there is no obvious sharp drop in efficiency, showing good efficiency stability and consistency, ensuring excellent performance over a wide load range.

[0306] In summary, Fig.10 The efficiency comparison curves intuitively prove that the adaptive substrate bias control scheme not only improves the conversion efficiency, but also takes into account the switch reliability and dynamic response capability. These experimental results fully demonstrate the effectiveness and practical value of the adaptive substrate bias control strategy, and provide new ideas and solutions for the design of high-efficiency single-inductor multi-output DC-DC converters. In practical applications, designers also need to comprehensively consider the circuit complexity, chip area, dynamic response capability and cost factors to balance the relationship between efficiency, cost and performance.

[0307] This adaptive substrate bias control technology is not only suitable for high-efficiency demanding applications such as mobile devices and portable electronics, but can also be extended to industrial and automotive applications that require precise power management and long-term operation stability.

[0308] Fig.11 A detailed timing diagram is provided to show the turn-on time of different power tubes (S(H), S(M), S(L)) in a single-inductor three-output power supply system and the substrate bias setting and adjustment timing of the corresponding power tube S(M). The figure clearly marks how the substrate bias of S(M) is configured and adjusted in different time slots to adapt to the system operation requirements.

[0309] The main features and components are explained as follows:

[0310] 1) Timing Mark:

[0311] t0, t2, t4, t6, t8, etc. mark different time points and are used to show the changes of the signal on the time axis.

[0312] 2) Voltage and signal identification:

[0313] VX2, Vo(H), Vo(M), Vo(L), GND, these horizontal dotted lines represent different voltage levels, where VX2 is the middle voltage node, Vo(H), Vo(M), Vo(L) represent high, middle and low output voltages respectively, and GND represents the ground.

[0314] S(L) on time, S(M) on time, S(H) on time, these bar graphs show the on time of the three power tubes. S(H), S(M) and S(L) control the high, medium and low voltage output respectively.

[0315] 3) Dynamic adjustment of substrate bias:

[0316] Available body biases of S(M) describes the optional configurations of the substrate bias of the medium voltage tube S(M), including ground (GND), connection to its output voltage Vo(M), and connection to VX2.

[0317] Configuration slot of S(M) shows the configuration of substrate bias based on different Slot signal S(M). Four main configuration slots are shown: Slot(HL), Slot(LM), Slot(MH) and Slot(HL). Each slot corresponds to a substrate bias switch from one voltage level to another.

[0318] 4) Slot signal logic:

[0319] The three main slot signals (Slot(HL), Slot(MH), Slot(LM)) define the switching timing of the power tube substrate bias. These signals control whether the substrate bias is connected to VX2, Vo(M) or GND, depending on the current output voltage relationship and the required optimized conduction loss.

[0320] 5) VB(M) substrate bias control:

[0321] This part of the figure shows in detail how the substrate bias of the medium voltage tube S(M) is switched between GND, VX2 and Vo(M) in different time slots to reduce conduction loss and improve efficiency.

[0322] Dynamic adjustment principle:

[0323] During the on-time of each power transistor, the substrate bias is adjusted according to the configured time slot. For example, if S(M) is turned on during Slot(LM), its substrate bias may be switched from GND to VX2 to adapt to the current power demand and system status.

[0324] This dynamic adjustment helps the system optimize performance, reduce power losses, and improve overall efficiency.

[0325] Fig.11 It provides an in-depth understanding of the precise timing and methods of substrate bias control in SIMO power supply systems, especially how to dynamically adjust the substrate bias according to the changes in the conduction and voltage levels of different power tubes to ensure the efficiency and stability of system operation.

[0326] Further, Fig.11 A detailed timing diagram explains how to dynamically adjust the substrate bias of the power tube according to different power requirements and voltage conditions. This strategy can minimize power loss and optimize conversion efficiency under different load conditions. In addition, dynamic substrate bias control helps improve system reliability and stability because it can reduce stress caused by adverse conditions (such as too high voltage or too low voltage) when the power tube is turned on.

[0327] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0328] In this example, a substrate bias control technique for output tubes of a single inductor triple output (SITO) power supply is provided. Figure 1As shown, the system in this example includes: an output voltage detector (Vo detector), which compares the three output voltages Vo[1:3] and generates a state signal State[2:0] based on the size relationship thereof; a time slot generator, which generates a time slot signal based on the control signal PWM[1:3] of the output power tube S1-3, and switches the substrate bias of the output power tube at the rising edge of the time slot signal; a body bias controller, which generates control signals φ1a, φ1b, φ1c, φ2a, φ2b, φ2c, φ3a, φ3b, φ3c based on State[2:0] and the Slot signal, and switches the substrate bias of S1-3 respectively; wherein φ1a, φ1b, φ1c is alternately enabled to control the substrate bias of S1. When φ1a is high, the substrate bias of S1 is connected to VX2. When φ1b is high, the substrate bias of S1 is connected to Vo[1]. When φ1c is high, the substrate bias of S1 is grounded. Among them, φ2a, φ2b, and φ2c are alternately enabled to control the substrate bias of S2. When φ2a is high, the substrate bias of S2 is connected to VX2. When φ2b is high, the substrate bias of S2 is connected to Vo[2]. When φ2c is high, the substrate bias of S2 is grounded. Among them, φ3a, φ3b, φ3c is alternately enabled to control the substrate bias of S3. When φ3a is high, the substrate bias of S3 is connected to VX2. When φ3b is high, the substrate bias of S3 is connected to Vo[3]. When φ3c is high, the substrate bias of S3 is grounded.

[0329] The substrate bias switching switch proposed in this example is as follows Figure 2 As shown (taking the substrate bias switching switch of S1 as an example), its structure includes: an n-type switch SB1a, whose gate is controlled by a switching signal φ1a, whose source and substrate are commonly connected to the substrate bias VB1 of the output power tube S1, and whose drain is connected to the output tube switching point VX2; an n-type switch SB1b, whose gate is controlled by a switching signal φ1b, whose source and substrate are commonly connected to the substrate bias VB1 of the output power tube S1, and whose drain is connected to the output voltage Vo[1]; an n-type switch SB1c, whose gate is controlled by a switching signal φ1c, whose source and substrate are commonly grounded, and whose drain is connected to the substrate bias VB1 of the output power tube S1.

[0330] The layout of the body bias switches proposed in this example is as follows: Figure 3As shown (taking the substrate bias switching switch of S1 as an example), its layout structure includes: the output power tube S1 and the substrate switches SB1a and SB1b share the substrate and form a unit, S1 is placed in the middle of the unit, SB1a and SB1b are arranged on both sides of the unit, the ratio of S1 gate finger to SB1a and SB1b gate fingers is n, where n is 10-20; SB1a and S1 share the source and drain at point VX2, and VX2 is connected through the top metal; SB1b and S1 share the source and drain at point Vo1, and Vo1 is connected through the top metal; the drain of SB1a and SB1b is connected to the substrate p ring to control the substrate bias of the unit.

[0331] The top layout of the body bias switches proposed in this example is as follows Figure 4 As shown (taking the substrate bias switching switch of S1 as an example), the submodule unit composed of the output power tube S1 and the substrate switches SB1a and SB1b is arranged in an array to form the top layout of S1, and the VX2 point and the Vo[1] point are connected through the top metal difference finger; the substrate switch SB1c is located on one side of the S1 array, the drain of SB1c is connected to the common substrate p ring of the S1 array, and the source of SB1c and the substrate are grounded. The substrate bias switching switches of S2 and S3 have the same structure as the substrate bias switching switch of S1, and will not be repeated here.

[0332] The output voltage detector (Vo detector) proposed in this example is as follows Figure 5 As shown, its structure includes: comparator CMP1, whose input is Vo[1] and Vo[2], and whose output is C[1]; comparator CMP2, whose input is Vo[2] and Vo[3], and whose output is C[2]; comparator CMP3, whose input is Vo[3] and Vo[1], and whose output is C[3]; the comparison result C[3:1] is input to the encoder (Encoder) and generates the state signal State[2:0]. State[2:0] represents the size relationship between Vo[1:3], of which there are six cases (such as Figure 6 shown), that is, Vo[1]>Vo[2]>Vo[3], Vo[1]>Vo[3]>Vo[2], Vo[2]>Vo[1]>Vo[3], Vo[2]>Vo[3]>Vo[1], V o[3]>Vo[1]>Vo[2], Vo[3]>Vo[2]>Vo[1]. At this time, the corresponding values ​​of State[2:0] are 000, 001, 010, 011, 100, and 101 respectively.

[0333] The time slot generator proposed in this example is as follows Figure 7As shown, its structure includes: a delay module delay1, whose input end is connected to the control signal PWM[1] of the output power tube S1, and whose output end is the trigger signal PWM_trig1; a delay module delay2, whose input end is connected to the control signal PWM[2] of the output power tube S2, and whose output end is the trigger signal PWM_trig2; a delay module delay3, whose input end is connected to the control signal PWM[3] of the output power tube S3, and whose output end is the trigger signal PWM_trig3; a logic gate OR1, whose input end 1 is connected to PWM[3], whose input end 2 is connected to PWM_trig2, and whose output is RST1; a logic gate OR2, whose input end 1 is connected to PWM[1], whose input end 2 is connected to PWM_trig3, and its output is RST2; logic gate OR1, its input 1 is connected to PWM[2], its input 2 is connected to PWM_trig1, and its output is RST3; D flip-flop D1, its D input is connected to VDD, its Clk input is connected to PWM_trig1, its Rst input is connected to RST1, and its output is Slot_1-2; D flip-flop D2, its D input is connected to VDD, its Clk input is connected to PWM_trig2, its Rst input is connected to RST2, and its output is Slot_2-3; D flip-flop D3, its D input is connected to VDD, its Clk input is connected to PWM_trig3, its Rst input is connected to RST3, and its output is Slot_3-1.

[0334] The working waveform of the time slot generator proposed in this example is as follows Figure 8 As shown: the control signal PWM[1:3] of the output power tube S1-3, the time slot signal Slot_1-2 when S1 switches to S2, the time slot signal Slot_2-3 when S2 switches to S3, and the time slot signal Slot_3-1 when S3 switches to S1; wherein the rising edge of PWM[1] is delayed by delay1, and then Slot_3-1 is turned off and Slot_1-2 is turned on; the rising edge of PWM[2] is delayed by delay2, and then Slot_1-2 is turned off and Slot_2-3 is turned on; the rising edge of PWM[3] is delayed by delay3, and then Slot_2-3 is turned off and Slot_3-1 is turned on.

[0335] The working flow diagram of the body bias controller proposed in this example is as follows: Fig. 9As shown, the working steps include: marking the three outputs based on the State[2:0] signal, wherein the highest output voltage is marked as Vo(H), and its corresponding output power tube is marked as S(H); wherein the lowest output voltage is marked as Vo(L), and its corresponding output power tube is marked as S(L); wherein the middle output voltage is marked as Vo(M), and its corresponding output power tube is marked as S(M); the substrate bias of S(H) is directly connected to VX2, the substrate bias of S(L) is directly connected to Vo(L), and the substrate bias VB(M) of S(M) needs to be switched instantaneously within the time slot signal; when the switching sequence of the VX2 point is low-medium-high (LMH), the time slot signals Slot_1-2, Slot_2-3, Slot_3-1 It can be marked as Slot(LM), Slot(MH), Slot(HL). When Slot(HL)=1, VB(M) is grounded, when Slot(LM)=1, VB(M) is connected to VX2, and when Slot(MH)=1, VB(M) is connected to the output voltage Vo(M). When the switching sequence of the VX2 point is high-middle-low (HML), the time slot signals Slot_1-2, Slot_2-3, Slot_3-1 can be marked as Slot(HM), Slot(ML), Slot(LH). When Slot(HM)=1, VB(M) is connected to the output voltage Vo(M), when Slot(ML)=1, VB(M) is connected to VX2, and when Slot(LH)=1, VB(M) is grounded.

[0336] When the single inductor three output (SITO) power supply enters the steady state, the output switch tubes S1-3 will be turned on in sequence, and the potential of the output tube switching point VX2 will be connected to the three output voltages Vo[1:3] in sequence. The switching sequence of VX2 is Vo[1]- Vo[2]- Vo[3]. If the highest potential in Vo[1:3] is defined as Vo(H), the lowest potential in Vo[1:3] is defined as Vo(L), and the middle potential in Vo[1:3] is defined as Vo(M), the switching sequence of VX2 can be summarized into two cases: Vo(H) - Vo(M) - Vo(L), that is, a high-medium-low level switching sequence; Vo(L) - Vo(M) - Vo(H), that is, a low-medium-high level switching sequence. Define S(H) as the output power tube that controls Vo(H), define S(M) as the output power tube that controls Vo(M), and define S(L) as the output power tube that controls Vo(L). Since the potential of VX2 is always smaller than Vo(H), the substrate bias of S(H) can be always connected to VX2; since the potential of VX2 is always larger than Vo(L), the substrate bias of S(L) can be always connected to Vo(L); the substrate bias of S(M) needs to be switched at any time according to the changes of VX2.

[0337] When the level switching sequence of VX2 is high-medium-low, the waveform of the device in this example is as follows Fig.10 As shown: when S(H) is turned on (t1-t3), the potential of VX2 is Vo(H). At this time, the substrate potential of S(M) can be connected to Vo(M) or grounded, and the body diode of S(M) will not be turned on; when S(M) is turned on (t3-t5), the potential of VX2 is Vo(M). At this time, the substrate potential of S(M) can be connected to Vo(M) or VX2, and the body effect of S(M) will not be caused; when S(L) is turned on (t5-t7), the potential of VX2 is Vo(L). At this time, the substrate potential of S(M) can be connected to VX2 or grounded, and the body diode will not be turned on; in this example, the time slot generator (timeslot The generator) generates the time slot signals Slot(HM), Slot(ML), Slot(LH) based on the control signals S(H), S(M), S(L) and State[2:0], wherein the Slot(HM) signal includes the switching edge of the VX2 high level to the middle level, the Slot(ML) signal includes the switching edge of the VX2 middle level to the low level, and the Slot(LH) signal includes the switching edge of the VX2 low level to the high level.

[0338] When Slot(HM) is 1 (t2-t4), the substrate bias voltage VB(M) of S(M) is set to Vo(M). This potential will neither cause the body diode of S(M) to conduct when S(H) is turned on (t1-t3), nor will it cause the body effect of S(M) when S(M) is turned on (t3-t5).

[0339] When Slot(ML) is 1 (t4-t6), the substrate bias voltage VB(M) of S(M) is set to VX2. This potential will neither cause the body effect of S(M) when S(M) is turned on (t3-t5), nor cause the body diode of S(M) to turn on when S(L) is turned on (t5-t7).

[0340] When Slot(LH) is 1 (t6-t8), the substrate bias VB(M) of S(M) is set to ground. This potential will neither cause the body diode of S(M) to conduct when S(L) is turned on (t5-t7) nor cause the body diode of S(M) to conduct when S(H) is turned on.

[0341] When the level switching sequence of VX2 is low-medium-high, the waveform of the device in this example is as follows Fig.11As shown: when S(L) is turned on (t1-t3), the potential of VX2 is Vo(L). At this time, the substrate potential of S(M) can be connected to VX2 or grounded without causing the body diode of S(M) to be turned on; when S(M) is turned on (t3-t5), the potential of VX2 is Vo(M). At this time, the substrate potential of S(M) can be connected to Vo(M) or VX2 without causing the body effect of S(M); when S(H) is turned on (t5-t7), the potential of VX2 is Vo(H). At this time, the substrate potential of S(M) can be connected to Vo(M) or grounded without causing the body diode to be turned on; in this example, the time slot generator (timeslot generator) generates time slot signals Slot(LM), Slot(MH), Slot(HL) based on the control signals S(H), S(M), S(L) and State[2:0], wherein the Slot(LM) signal includes a switching edge from a low level to a middle level of VX2, the Slot(MH) signal includes a switching edge from a middle level to a high level of VX2, and the Slot(HL) signal includes a switching edge from a high level to a low level of VX2.

[0342] When Slot(LM) is 1 (t2-t4), the substrate bias voltage VB(M) of S(M) is set to VX2. This potential will neither cause the body diode of S(M) to turn on when S(L) is turned on (t1-t3), nor cause the body effect of S(M) when S(M) is turned on (t3-t5);

[0343] When Slot(MH) is 1 (t4-t6), the substrate bias voltage VB(M) of S(M) is set to Vo(M). This potential will neither cause the body effect of S(M) when S(M) is turned on (t3-t5), nor cause the body diode of S(M) to conduct when S(H) is turned on (t5-t7).

[0344] When Slot(HL) is 1 (t6-t8), the substrate bias VB(M) of S(M) is set to ground. This potential will neither cause the body diode of S(M) to conduct when S(H) is turned on (t5-t7) nor cause the body diode of S(M) to conduct when S(L) is turned on.

[0345] Compared with the prior art, the beneficial effects of this example are as follows:

[0346] In this example, an n-type output power tube is used, and its substrate switching signal is not synchronized with the output power tube switching signal, but has a phase difference of 90°. There is no need to design a complex non-overlapping drive signal generator, and no additional dead time is introduced. Moreover, the structure is simple, the chip area is reduced, and the power supply efficiency is not affected.

[0347] The contents not described in detail in the specification of this example belong to the common knowledge of those skilled in the art.

[0348] It should be understood that the above embodiments are merely illustrative of the present invention rather than limiting the present invention, and any inventions that do not exceed the essential spirit of the present invention shall fall within the protection scope of the present invention.

[0349] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0350] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A device for controlling substrate bias voltage of an output tube of a single-inductor three-output power supply, characterized in that: include: An output voltage detector, used to continuously compare the magnitude relationship among the first output voltage, the second output voltage and the third output voltage, and to generate a status signal in real time based on the comparison result; A time slot generator, for receiving PWM control signals of three output power tubes and generating a time slot signal based on the rising edge timing of these signals, the time slot signal indicating a suitable switching timing to adjust the substrate bias voltage; The substrate bias controller generates multiple groups of control signals according to the state signal and the time slot signal, and each group of signals is responsible for controlling the dynamic switching of the substrate bias of the corresponding output power tube between the output tube switching point voltage, the ground voltage and the corresponding output voltage; Multiple substrate bias switching switches are connected to the substrate of each output power tube respectively, and respond to corresponding control signals to achieve accurate switching of substrate bias; wherein, The substrate bias controller is used to: According to the status signal received from the output voltage detector, the highest voltage, the lowest voltage and the middle voltage among the three output voltages are identified and marked, and the output power tubes connected to these voltages are marked as high voltage tubes, low voltage tubes and middle voltage tubes accordingly; Control the substrate bias of the high voltage tube directly connected to the specific output tube switching point voltage to operate at the highest voltage condition; Control the substrate bias of the low voltage tube directly to the lowest voltage of the system to optimize power efficiency; According to the received time slot signal and status signal, the substrate bias of the medium voltage tube is dynamically adjusted to switch between the intermediate voltage, the output tube switching point voltage and the ground voltage: When it is necessary to switch from the lowest voltage to the highest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the output tube switching point voltage, the intermediate voltage and the ground voltage; When it is necessary to switch from the highest voltage to the lowest voltage, the substrate bias of the medium voltage tube is adjusted in the order of the intermediate voltage, the output tube switching point voltage and the ground voltage.

2. The output tube substrate bias control device according to claim 1, characterized in that: The output voltage detector comprises: Three comparators, wherein the first comparator is used to compare the first output voltage and the second output voltage, the second comparator is used to compare the second output voltage and the third output voltage, and the third comparator is used to compare the first output voltage and the third output voltage, and each comparator outputs a binary comparison result indicating the magnitude relationship between the corresponding two voltages; An encoder is used to encode the output results of the three comparators to generate a state signal, which comprehensively reflects the relative magnitude relationship among the first output voltage, the second output voltage and the third output voltage.

3. The output tube substrate bias control device according to claim 1, characterized in that: The time slot generator comprises: The first, second, and third delay modules receive the control signals of the first, second, and third output power tubes respectively, and perform predetermined delay processing on these signals to reduce interference between the signals, and then output the corresponding first, second, and third trigger signals; three OR gates, respectively performing a logic OR operation on the first and second trigger signals, the second and third trigger signals, and the third and first trigger signals, so as to generate first, second and third reset signals for respective resets; The first, second and third D flip-flops respectively receive corresponding trigger signals as clock signals and receive corresponding reset signals as reset signals to control and output first, second and third time slot signals, wherein each time slot signal is used to indicate and control the optimal moment for switching the substrate bias of the corresponding output power tube.

4. The output tube substrate bias control device according to claim 1, characterized in that: The substrate bias switching switch comprises: A first switch group, comprising three switches, each of which is connected to the substrate of the first output power tube and is used to switch the substrate bias voltage between the first output voltage, the output tube switching point voltage and the ground voltage under the control of the first control signal group; A second switch group, comprising three switches, each of which is connected to the substrate of the second output power tube and is used to switch the substrate bias voltage between the second output voltage, the output tube switching point voltage and the ground voltage under the control of the second control signal group; A third switch group, comprising three switches, each of which is connected to the substrate of the third output power tube and is used to switch the substrate bias voltage between the third output voltage, the output tube switching point voltage and the ground voltage under the control of the third control signal group; In each switch group, three switches are connected in parallel through electronic control logic, ensuring that only one switch is activated at any time, achieved through complementary control signals, thereby accurately controlling the dynamic adjustment of substrate bias to prevent voltage conflicts or short circuits.

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