A clock synchronization device for a tip timing acquisition system

Abstract

The application discloses a clock synchronization device, and relates to the field of signal collection, which comprises an external clock module, a clock distribution module and a collection array module; the clock distribution module receives a first external clock signal source from the external clock module, and is divided into multiple groups of synchronized second clock signal sources through the clock distribution module, and is transmitted to the collection array module; the collection array module outputs multiple groups of digital signals. The clock distribution module comprises a first internal clock signal source, an external clock signal interface, a first selector, a time division array module and an interface array of an output clock signal source. The device can realize synchronous signal collection of multiple sets of tip timing collection systems and the tip timing collection system and other various collection systems through an expansion access mode.

Description

A clock synchronization device for a leaf tip timing acquisition system Technical Field

[0001] This invention relates to the field of rotating blade measurement, and more particularly to a clock synchronization device for a blade tip timing acquisition system. Background Technology

[0002] Tip timing technology utilizes multiple sensors mounted on the casing to measure the arrival time of the blade tips, obtaining operating parameters such as blade frequency and amplitude, thereby enabling the monitoring of turbomachinery operation. As a non-contact measurement technology, tip timing is an important means to ensure the safe operation of turbomachinery and has broad application prospects.

[0003] To obtain operating parameters such as blade frequency and amplitude, and to reconstruct blade vibration information, blade tip timing technology requires acquiring multiple blade tip timing signals from different stages of the turbomachinery, necessitating a massive number of sensor channels. However, the number of channels in a single blade tip timing acquisition system is limited. When the required sensor signals exceed the upper limit of a single device's channel count, existing blade tip timing acquisition systems struggle to meet measurement demands. An ideal solution is to use multiple blade tip timing acquisition systems for joint acquisition. However, the master clock frequencies and phases differ between these systems, resulting in different timestamp counters. This leads to a lack of a unified time reference for the blade tip arrival times acquired by different systems, hindering joint analysis. Furthermore, current technologies have not solved the problem of synchronous acquisition across multiple blade tip timing acquisition systems, making it difficult to synchronously acquire a large number of sensor signals. This, to some extent, impedes the application of blade tip timing technology in turbomachinery health monitoring. Furthermore, when studying the overall turbomachinery system and comparing parameters such as stress, temperature, and pressure, the lack of a unified time reference frame between the data acquired by the tip-timed acquisition system and other systems prevents joint analysis. This asynchronous data acquisition hinders the application of joint analysis between the tip-timed acquisition system and other systems, impeding the application and development of tip-timed measurement technology in turbomachinery health monitoring. Figure 1 shows the clock signal source used in the tip-timed acquisition system, including a trigger signal and a clock signal. The trigger signal is a single pulse signal, and the clock signal is a periodic pulse signal.

[0004] The lack of clock synchronization devices and methods for a unified time reference system has hindered the application and development of tip timing acquisition systems in turbomachinery health monitoring. Therefore, developing a device and method for synchronizing acquisition between multiple tip timing acquisition systems and other systems, enabling each independent system to operate under a unified time reference system, acquire synchronized measurement data, and achieve joint signal analysis, is of great significance for ensuring the application and development of tip timing technology in turbomachinery.

[0005] Existing clock synchronization solutions suffer from problems such as complex implementation, slow adjustment speed, and inapplicability to existing leaf tip timing acquisition systems. For example, some devices and methods are suitable for multi-board clock synchronization calibration. By controlling the trace length of the clock modules on the main board and daughter boards, and using clock signals obtained from the first and second calibration interfaces, they determine whether there is a phase difference between the daughter clock signal and the main clock signal. For daughter clocks with different phases, they adjust the delay module to achieve clock synchronization between the daughter clock signal and the main clock signal. Other solutions do not control the trace length of the main board and daughter boards. Instead, they directly calculate the phase difference between the real-time external clock pulse and the real-time control clock pulse through a time difference conversion module, and adjust the real-time control clock pulse based on the phase difference to finally achieve synchronization between the real-time external pulse and the real-time control clock pulse.

[0006] The above methods all adjust the internal clock signal by calculating the phase difference between the external clock and the internal clock. Essentially, they use negative feedback to achieve clock synchronization. However, they have problems such as complex processing methods, high requirements for processor performance, unsuitability for synchronous acquisition in existing leaf tip timing acquisition systems, and incompatibility with synchronous acquisition of multiple acquisition devices.

[0007] In summary, existing leaf tip timed data acquisition schemes have the following drawbacks:

[0008] 1. Existing blade tip timing acquisition systems can only acquire a fixed number of sensor signals, limiting the number of acquisition channels and making it difficult to meet the measurement needs of actual environments. To achieve high-precision monitoring of blade operating parameters and synchronous monitoring of multiple blade stages, a large number of sensor signals often need to be acquired synchronously. When the number of required sensor signals exceeds the upper limit of the blade tip timing system's acquisition channels, existing single-system blade tip timing acquisition systems struggle to achieve synchronous acquisition of all sensor signals. Furthermore, since blade tip timing acquisition systems operate independently, the clock reference systems are not consistent, making it impossible to synchronously acquire sensor signals across multiple systems, hindering joint analysis.

[0009] 2. Existing clock synchronization schemes do not involve the synchronous triggering of counters, but the leaf tip timing acquisition system requires synchronous triggering of counters to ensure that the timestamps acquired by the system are consistent at time zero. Therefore, existing clock synchronization schemes are not suitable for the synchronous acquisition requirements of the leaf tip timing acquisition system. Furthermore, existing clock synchronization schemes all adjust the clock signal by calculating the phase difference, requiring separate phase difference calculation modules and delay correction modules for different sub-clock signals. However, existing leaf tip timing acquisition systems do not have these modules. Therefore, adopting these clock synchronization schemes requires discarding existing equipment and redesigning, which is costly. Adding these modules would also increase system size, power consumption, and processor performance requirements, contradicting the miniaturization, low power consumption, and high performance requirements of the leaf tip timing acquisition system.

[0010] 3. In the process of monitoring the operating status of turbomachinery, it is often necessary to collect signals from different types of sensors simultaneously. However, different types of sensor signals are often collected by independent acquisition systems with independent internal clocks, making it impossible to achieve synchronous acquisition of different types of signals while maintaining compatibility with existing acquisition systems. This results in the inability of the blade tip timing acquisition system and other acquisition systems to perform synchronous acquisition.

[0011] Therefore, those skilled in the art are dedicated to developing a clock synchronization device for a leaf tip timing acquisition system to achieve clock synchronization, so that different leaf tip timing acquisition systems or other acquisition systems can achieve synchronous acquisition under a synchronized clock signal source through extended access. Summary of the Invention

[0012] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by the present invention includes:

[0013] 1. Solve the problem that existing technologies cannot use multiple leaf tip timing acquisition systems for synchronous acquisition.

[0014] 2. To address the problems of increased size, decreased performance, higher processor requirements, and higher cost caused by the need to add phase difference calculation and delay modules to existing clock synchronization solutions.

[0015] 3. To address the issues of limited acquisition channels and poor scalability in existing leaf tip timing acquisition systems.

[0016] 4. Solve the problem that the existing leaf tip timing acquisition system cannot synchronize with other acquisition systems.

[0017] To achieve the above objectives, the present invention provides a clock synchronization device for a leaf tip timing acquisition system, comprising:

[0018] An external clock module is configured to provide a first external clock signal source;

[0019] A clock distribution module, communicatively connected to the external clock module, configured to receive signals from a first external clock signal source of the external clock module, and to divide the first external clock signal source into at least two synchronized second clock signal sources; and

[0020] The acquisition array module is communicatively connected to the clock distribution module and is configured to receive at least two sets of the second clock signal sources from the clock distribution module and output corresponding multiple sets of digital signals based on the at least two sets of the second clock signal sources.

[0021] Furthermore, the clock allocation module includes:

[0022] An external clock signal interface is communicatively connected to the external clock module and is configured to receive the first external clock signal source from the external clock module.

[0023] The first internal clock signal source is configured to include a first internal clock signal and a first internal trigger signal;

[0024] A first selector, which is communicatively connected to both the external clock signal interface and the first internal clock signal source, is configured to selectively output received signals; the first selector is also configured to be triggered by a button or network command.

[0025] The time-division array module, communicatively connected to the first selector, is configured to receive the first external clock signal source or the first internal clock signal source output by the first selector as input, and output at least two sets of synchronized second clock signal sources; and

[0026] An interface array, which is communicatively connected to the time-division array module, is configured to receive at least two sets of the second clock signal sources from the time-division array module.

[0027] Furthermore, the time-division array module includes at least two time-division modules, each of which is communicatively connected to the interface array, and each of the time-division modules is configured to output a set of the second clock signal sources.

[0028] Furthermore, the first external clock signal source is configured to include a first external trigger signal and a first external clock signal.

[0029] Furthermore, the interface array is configured to output a second clock signal source containing at least two sets of synchronized signals.

[0030] Furthermore, the acquisition array module includes one or more signal acquisition units; the signal acquisition unit includes:

[0031] A signal conditioning module, configured to receive external sensor signals;

[0032] The second selector is communicatively connected to the interface array and the acquisition board respectively; the second selector is configured to selectively access the second clock signal source or the second internal clock signal source, and selectively output the received signal from the second clock signal source or the second internal clock signal source.

[0033] The acquisition board is configured to receive the clock signal source output by the second selector and operate using the clock signal and trigger signal of the clock signal source.

[0034] Furthermore, the signal acquisition unit is communicatively connected to the switch and is configured to output digital signals to the switch, and the switch is communicatively connected to the host computer and is configured to output data packets to the host computer.

[0035] Furthermore, the signal acquisition unit is configured to access the second clock signal source; the second clock signal source includes a second clock signal and a second trigger signal.

[0036] The second internal clock signal source is configured as a clock signal source including a second internal clock signal and a second internal trigger signal.

[0037] Furthermore, the acquisition board is configured such that when the second selector selects the second internal clock signal source, the clock interface of the acquisition board receives the second internal clock signal, the counter of the acquisition board receives the second internal trigger signal, and the signal acquisition unit operates with the second internal clock signal source to acquire multiple sensor signals.

[0038] Furthermore, the counter is configured to return to zero or reset to a specific value when the second internal trigger signal is received.

[0039] Furthermore, the acquisition board is configured such that when the second selector selects the second clock signal source, the clock interface of the acquisition board receives the second clock signal, the counter of the acquisition board receives the second trigger signal, and the signal acquisition unit operates with the second clock signal source to acquire multiple sensor signals.

[0040] Furthermore, the counter is configured to return to zero or reset to a specific value when the second trigger signal is received.

[0041] Furthermore, the acquisition array module is a single set of leaf tip timing acquisition units; and

[0042] The external clock module and the clock distribution module are configured to be in a closed state. The second selector in the leaf tip timing acquisition unit is configured to receive the second internal clock signal and the second internal trigger signal and transmit them to the acquisition board to realize independent leaf tip timing acquisition system signal acquisition.

[0043] Furthermore, the acquisition array module includes at least two acquisition array units; and

[0044] The clock distribution module is configured to start after at least two of the acquisition array units are turned on, so as to achieve synchronous acquisition of the signal acquisition units.

[0045] Furthermore, the second clock signal source obtained by each of the signal acquisition units is synchronized.

[0046] Furthermore, the time-sharing module includes one of the following chips: ARM, FPGA, MCU.

[0047] Furthermore, the acquisition board includes an FPGA acquisition board.

[0048] Furthermore, the clock distribution module and the acquisition array module are also configured to be integrated into a single acquisition board. When the clock distribution module and the acquisition array module are integrated into a single acquisition board, the acquisition board receives the input signal from the first external clock signal source through an interface and is capable of outputting multiple sets of synchronized second clock signal sources. The acquisition board is also configured to be expanded through the interface.

[0049] Furthermore, the acquisition array module is configured to transmit the output digital signal to the host computer via a network signal.

[0050] Compared with the prior art, the beneficial technical effects of the present invention include:

[0051] 1. The clock distribution module of the present invention can be stacked to output an unlimited number of synchronous clock signal sources, thereby meeting the clock synchronization acquisition requirements under different conditions.

[0052] 2. The acquisition array module of the present invention can increase the number of acquisition channels by expanding the signal acquisition unit, so that there is no upper limit to the number of channels that the system can work at the same time, and can meet the synchronous acquisition requirements of the leaf tip timing acquisition system and other acquisition systems.

[0053] 3. This invention directly replaces the internal clock with an external clock to achieve clock synchronization, which has the advantages of low cost, fast adjustment speed, reduced requirements on processor performance, and compatibility with existing leaf tip timing acquisition systems and other acquisition systems.

[0054] 4. This invention uses an array method to achieve synchronous acquisition of signals from various sensors, which solves the problems of limited functionality and poor scalability of existing leaf tip timing acquisition systems. It improves the compatibility, scalability, and ease of use of the device, and also makes the number of channels that can work simultaneously unlimited, adapting to various synchronous acquisition scenarios.

[0055] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description

[0056] Figure 1 is a schematic diagram of the clock signal source;

[0057] Figure 2 is a schematic diagram of the overall structure and workflow of a preferred embodiment of the present invention;

[0058] Figure 3 is a schematic diagram of the clock distribution module structure;

[0059] Figure 4 is a schematic diagram of the acquisition array module structure;

[0060] Figure 5 is a schematic diagram of the acquisition array unit as a leaf tip timing acquisition unit;

[0061] Figure 6 is a schematic diagram of the structure for synchronous signal acquisition using a single leaf tip timing acquisition unit;

[0062] Figure 7 is a schematic diagram of the structure for synchronous signal acquisition using multiple leaf tip timing acquisition units;

[0063] Figure 8 is a schematic diagram of a structure for synchronous signal acquisition using multiple different acquisition units;

[0064] Figure 9 is a schematic diagram of the structure for synchronous acquisition using other measurement units as an external clock;

[0065] The components are as follows: 1-External clock module, 2-Clock distribution module, 3-Acquisition array module, 4-Switch, 5-Host computer, 8-Digital signal, 9-Data packet, 16-First external trigger signal, 17-First external clock signal, 26-Second trigger signal, 27-Second clock signal, 101-First external clock signal source, 201-First internal clock signal source, 202-External clock signal interface, 203-First selector, 204-Time-division array module, 205-Interface array for output clock signal source, 206-Clock signal source array, 2061-Second clock signal source, 2011-First internal clock signal, 2012-First internal trigger signal, 2041-Time-division module, 301-Signal acquisition unit, 302-Multi-channel sensor signal, 303-Digital signal, 3010-Second internal clock signal source, 3011-Second internal clock signal, 3012-Second internal trigger signal. 3013 - Signal conditioning module, 3014 - Second selector, 3015 - Clock interface, 3016 - Counter, 3017 - FPGA acquisition board. Detailed Implementation

[0066] The following description, with reference to the accompanying drawings, illustrates several preferred embodiments of the present invention to make its technical content clearer and easier to understand. The present invention can be embodied in many different forms, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0067] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of some components has been appropriately exaggerated in the drawings.

[0068] As shown in Figure 2, the clock synchronization device includes an external clock module 1, a clock distribution module 2, and a data acquisition array module 3. The clock distribution module 2 receives a first external trigger signal 16 and a first external clock signal 17 from the external clock module 1. It then divides the signals into several groups of second trigger signals 26 and second clock signals 27, and transmits these synchronized groups to the data acquisition array module 3. The module acquires multiple sets of digital signals 8 through synchronous acquisition, and encodes these digital signals 8 into data packets 9 via a switch 4. Finally, the data packets 9 are sent to a host computer 5 for processing. In this embodiment, the digital signals output by the data acquisition array module are converted into data packets by a switch and transmitted to the host computer, which is a network signal transmission. In other embodiments, wires can also be used to transmit the signals to the host computer. The external clock module and the clock distribution module can be integrated into a circuit board.

[0069] As shown in Figure 3, the clock distribution module 2 includes a first internal clock signal source 201, an external clock signal interface 202, a first selector 203 for the clock signal source, a time-division array module 204, and an interface array 205 for output clock signal sources. The external clock module 1 transmits the first external clock signal source 101 to the external clock signal interface 202. The external clock signal source 101 includes a first external trigger signal 17 and a first external clock signal 16. The first internal clock signal source 201 includes a first internal clock signal 2011 and a first internal trigger signal 2012. The first internal clock signal 2011 is a stable and independently periodic pulse clock signal generated by the crystal oscillator of the internal clock. The first internal clock signal source 201 can provide a standard clock signal source to meet the clock signal source requirements of the blade tip timing acquisition unit. However, when the internal clock signal source 201 does not meet the measurement requirements, such as when connecting temperature or pressure acquisition modules, or when the acquisition frequencies of these modules are inconsistent with the blade tip timing acquisition system, a suitable external clock signal source 101 can be connected through the external clock signal interface 202.

[0070] The first selector 203 can be triggered by a button or network command. The first selector 203 can select to connect to either the first external clock signal source 101 or the first internal clock signal source 201, and output the selected signal source to the time-division array module 204. The time-division modules 2041 in the time-division array module 204 can be expanded as needed. The time-division array module 204 transmits multiple identical second clock signal sources output by multiple time-division modules 2041 to the interface array 205 of the output clock signal source. The interface array 205 of the output clock signal source outputs a clock signal source array 206 containing multiple sets of synchronous clock signal sources. By expanding the time-division array module 204 and the interface array 205, the clock distribution module 2 can output an unlimited number of second clock signal sources as needed. The time-division module 2041 uses existing mature chips, achieves signal synchronization by aligning signal edges, and expands the time-division module 2041 through stacking, allowing the signal interface array 205 to output multiple sets of clock signal sources with consistent frequency and phase.

[0071] As shown in Figure 4, the acquisition array module 3 includes a signal acquisition unit array 304 composed of multiple signal acquisition units 301. Each signal acquisition unit 301 can receive a second clock signal source 2061 from the clock signal source array 206. The second clock signal source 2061 includes a second trigger signal 26 and a second clock signal 27.

[0072] The internal clock of the signal acquisition unit 301 generates a second internal clock signal 3011, and its internal trigger generates a second internal trigger signal 3012. The second internal clock signal 3011 and the second internal trigger signal 3012 together form a second internal clock signal source 3010. When the second selector 3014 selects the second internal clock signal source 3010 inside the signal acquisition unit 301 or the second clock signal source 2061 output by the clock signal source array 206, the signal acquisition unit 301 operates with the corresponding second internal clock signal source 3010 or second clock signal source 2061, receives multiple sensor signals 302, processes them accordingly, outputs a digital signal 303, and finally outputs the digital signal 303 to the corresponding switch 4. The switch 4 then outputs a data packet 9 to the host computer 5, completing the synchronous acquisition of signals.

[0073] The signal acquisition unit 301 can be a single-set leaf tip timing acquisition system (i.e., a leaf tip timing acquisition unit) or other signal acquisition systems. When only the signal acquisition unit is available or when asynchronous data needs to be acquired, the second internal clock signal source 3010 inside the signal acquisition unit can be used. If synchronous acquisition is required, an external clock signal source, i.e., a second clock signal source 2061, needs to be connected. As shown in Figure 5, the signal acquisition unit 301 is a leaf tip timing acquisition unit, including a signal conditioning module 3013, an FPGA acquisition board 3017, and a second selector 3014. After the multiple sensor signals 302 are input to the signal conditioning module 3013 for signal conditioning, they are input to the FPGA acquisition board 3017 for signal acquisition, and finally, a digital signal 303 is output. When the second selector 3014 selects the second internal clock signal source 3010 inside the signal acquisition unit 301 and outputs it to the FPGA acquisition board 3017, the second internal trigger signal 3012 contained in the second internal clock signal source 3010 is input to the counter 3016 in the FPGA acquisition board, and the second internal clock signal 3011 contained in the second internal clock signal source 3010 is input to the clock interface 3015 in the FPGA acquisition board. When the counter 3016 receives the second internal clock signal 3012, the counter returns to zero or is reset to a specific value, and the FPGA acquisition board 3017 operates with the input second internal clock signal 3011. Similarly, when the second selector 3014 selects the second clock signal source 2061 output by the clock signal source array 206 and outputs it to the FPGA acquisition board 3017, the second trigger signal 26 contained in the second clock signal source 2061 is input to the counter 3016 in the FPGA acquisition board, and the second clock signal 27 contained in the second clock signal source 2061 is input to the clock interface 3015 in the FPGA acquisition board. When the counter 3016 receives the second trigger signal 26, the counter is reset to zero or to a specific value, and the FPGA acquisition board 3017 operates with the input second clock signal 27.

[0074] For other acquisition systems using the acquisition array module as signal acquisition unit 301, synchronous acquisition can be achieved by referring to the working principle of the leaf tip timing acquisition unit described above. The digital signal 8 acquired and processed by the acquisition array module 3 is transmitted to the switch 4 via a wire, and then the data packet 9 is transmitted to the host computer 5 via the network. As an alternative, the data packet 9 output by the switch 4 can also be directly transmitted to the host computer 5 via a wire for processing, without the need for data transmission via the network.

[0075] To achieve synchronous acquisition by each signal acquisition unit 301, after all signal acquisition units 301 are turned on, the clock distribution module 2 can be activated. The time-division module 2041 uses the alignment signal edges to synchronize the external clock signals obtained by each signal acquisition unit 301, i.e., the second clock signal source 2061 in the clock signal source array 206, thereby ensuring consistency of the time reference system of each signal acquisition unit 301. The number of output clock signal sources can be changed by stacking different numbers of time-division modules 2041 to adapt to measurement requirements. The clock signal source array 206 output from the interface array 205 of the output clock signal source is transmitted to the signal acquisition unit 301 for signal acquisition via wires. Finally, each signal acquisition unit acquires multiple sensor signals 302 and outputs the digital signals 303 to the corresponding switch 4. The switch 4 then outputs data packets 9 to the host computer 5, completing the synchronous acquisition of signals.

[0076] As shown in Figure 6, when signal acquisition can be completed using only a single leaf tip timing acquisition system, the external clock module 1 and clock distribution module 2 can be turned off. The second internal clock signal 3011 and the second internal trigger signal 3012 are input to the FPGA acquisition board through the second selector 3014 in the leaf tip timing acquisition unit, so that signal acquisition can be achieved in the form of an independent leaf tip timing acquisition system.

[0077] As shown in Figure 7, when multiple leaf tip timing acquisition systems are needed for synchronous acquisition, a suitable number of time-division modules 2041 and signal acquisition units 301 can be stacked first to meet the signal channel requirements for synchronous acquisition. Then, the first selector 203 can select to connect to the first external clock signal source 101 or the first internal clock signal source 201, turn on the clock distribution module 2, the acquisition array module 3, the switch 4 and the host computer 5, and turn on the start switch on the clock signal source to achieve synchronous acquisition of multiple leaf tip timing acquisition systems.

[0078] As shown in Figure 8, when different acquisition systems need to be used for synchronous acquisition, different acquisition systems can be directly connected to the signal acquisition unit 301. At this time, the signal acquisition unit 301 can be a blade tip timing acquisition unit, aerodynamic measurement unit, temperature measurement module unit, etc. The synchronous acquisition scheme of multiple blade tip timing acquisition systems shown in Figure 7 can realize the synchronous acquisition of signals from different acquisition systems.

[0079] As shown in Figure 9, when other acquisition systems have the ability to output clock signal sources, the clock signal sources output by other acquisition systems can be directly input into the external clock module 1 as the first external clock signal source 101, so that the internal leaf tip timing acquisition unit 301 can work with the clock signal and trigger signal of the input first external clock signal source 101.

[0080] In other embodiments of the present invention, the clock distribution module and the acquisition array module can be integrated into a single integrated circuit board, such as an FPGA board. This board receives the input signal from a first external clock signal source via an interface and can output multiple sets of synchronized second clock signal sources via the same interface. This integrated circuit board, which integrates the clock distribution module and the acquisition array module, can also be expanded via an interface, making the acquisition system scalable.

[0081] In summary, due to the large number of sensor channels required for data acquisition in BTT technology, the high precision requirements for data analysis, and the high acquisition frequency, existing leaf tip timing acquisition devices are insufficient. Existing leaf tip timing acquisition systems cannot meet the measurement requirements of actual operating environments. By utilizing clock synchronization technology to synchronize the acquisition of multiple leaf tip timing acquisition devices, the requirements of subsequent actual working environments and data processing can be met. This invention is based on this need and proposes a clock synchronization device for leaf tip timing acquisition systems to solve the problem that existing leaf tip timing systems cannot synchronously acquire a large number of channel data, achieving beneficial technical effects: The leaf tip timing acquisition system or other acquisition systems can be connected to a time-division array module in a scalable manner, enabling each acquisition system to obtain a synchronized clock signal source, thus realizing the measurement requirement of synchronous acquisition by each acquisition system under a synchronized clock signal source.

[0082] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A clock synchronization device for a leaf tip timing acquisition system, characterized in that, include: An external clock module is configured to provide a first external clock signal source; A clock distribution module, comprising: an external clock signal interface communicatively connected to an external clock module and configured to receive a first external clock signal source from the external clock module; a first internal clock signal source configured to include a first internal clock signal and a first internal trigger signal; a first selector communicatively connected to both the external clock signal interface and the first internal clock signal source and configured to selectively output the received signals; the first selector is further configured to be triggered by a button or network command; and a time-division array module. The system comprises: a first selector, configured to receive the first external clock signal source or the first internal clock signal source output by the first selector as input, and output at least two sets of synchronized second clock signal sources; an interface array, configured to receive at least two sets of second clock signal sources from the time-division array module; a clock distribution module, configured to receive the first external clock signal source from the external clock module and divide the first external clock signal source into at least two sets of synchronized second clock signal sources; and a data acquisition array module, configured to receive at least two sets of second clock signal sources from the clock distribution module and output corresponding multiple sets of digital signals based on the at least two sets of second clock signal sources; the data acquisition array module includes one or more signal acquisition units; the signal acquisition unit includes: a signal modulation... The system comprises: a signal conditioning module configured to receive external sensor signals; a second selector communicatively connected to the interface array and the acquisition board; the second selector configured to selectively access the second clock signal source or the second internal clock signal source, and selectively output the received signals from the second clock signal source or the second internal clock signal source; the second internal clock signal source configured to include a second internal clock signal and a second internal trigger signal; an acquisition board configured to receive the clock signal source output by the second selector and operate using the clock signal and trigger signal of the clock signal source; the acquisition array module being a single-set leaf tip timing acquisition unit; the external clock module and the clock distribution module being configured to be in a closed state; and the second selector in the leaf tip timing acquisition unit configured to receive the second internal clock signal and the second internal trigger signal and transmit them to the acquisition board to achieve independent leaf tip timing acquisition system signal acquisition.

2. The clock synchronization device for a leaf tip timing acquisition system as described in claim 1, characterized in that, The time-division array module includes at least two time-division modules, each of which is communicatively connected to the interface array, and each of which is configured to output a set of second clock signal sources.

3. The clock synchronization device for a leaf tip timing acquisition system as described in claim 1, characterized in that, The first external clock signal source is configured to include a first external trigger signal and a first external clock signal.

4. The clock synchronization device for a leaf tip timing acquisition system as described in claim 2, characterized in that, The interface array is configured to output a second clock signal source containing at least two sets of synchronized signals.

5. The clock synchronization device for a leaf tip timing acquisition system as described in claim 1, characterized in that, The signal acquisition unit is communicatively connected to the switch and is configured to output digital signals to the switch. The switch is communicatively connected to the host computer and is configured to output data packets to the host computer.

6. The clock synchronization device for a leaf tip timing acquisition system as described in claim 1, characterized in that, The signal acquisition unit is configured to access the second clock signal source; the second clock signal source includes a second clock signal and a second trigger signal.

7. The clock synchronization device for a leaf tip timing acquisition system as described in claim 6, characterized in that, The acquisition board is configured such that when the second selector selects the second internal clock signal source, the clock interface of the acquisition board receives the second internal clock signal, the counter of the acquisition board receives the second internal trigger signal, and the signal acquisition unit operates with the second internal clock signal source to acquire multiple sensor signals.

8. The clock synchronization device for a leaf tip timing acquisition system as described in claim 7, characterized in that, The counter is configured to return to zero or reset to a specific value when the second internal trigger signal is received.

9. The clock synchronization device for a leaf tip timing acquisition system as described in claim 6, characterized in that, The acquisition board is configured such that when the second selector selects the second clock signal source, the clock interface of the acquisition board receives the second clock signal, the counter of the acquisition board receives the second trigger signal, and the signal acquisition unit operates with the second clock signal source to acquire multiple sensor signals.

10. The clock synchronization device for a leaf tip timing acquisition system as described in claim 9, characterized in that, The counter is configured to return to zero or reset to a specific value when the second trigger signal is received.

11. The clock synchronization device for a leaf tip timing acquisition system as described in claim 1, characterized in that, The acquisition array module includes at least two acquisition array units; and the clock distribution module is configured to start after all at least two acquisition array units are turned on, so as to realize synchronous acquisition of the signal acquisition units.

12. The clock synchronization device for a leaf tip timing acquisition system as described in claim 6, characterized in that, The second clock signal source obtained by each of the signal acquisition units is synchronized.

13. The clock synchronization device for a leaf tip timing acquisition system as described in claim 2, characterized in that, The time-sharing module includes one of the following chips: ARM, FPGA, MCU.

14. The clock synchronization device for a leaf tip timing acquisition system as described in claim 1, characterized in that, The acquisition board includes an FPGA acquisition board.

15. The clock synchronization device for a leaf tip timing acquisition system as described in claim 1, characterized in that, The clock distribution module and the acquisition array module are further configured to be integrated into a single integrated circuit board. When the clock distribution module and the acquisition array module are integrated into the integrated circuit board, the integrated circuit board receives the input signal of the first external clock signal source through an interface and is capable of outputting multiple sets of synchronized second clock signal sources. The integrated circuit board is also configured to be expanded through the interface.

16. The clock synchronization device for a leaf tip timing acquisition system as described in claim 5, characterized in that, The acquisition array module is configured to transmit the output digital signal to the host computer via a network signal.

17. The clock synchronization device for a leaf tip timing acquisition system as described in claim 5, characterized in that, The acquisition array module is configured to transmit the output digital signal to the host computer via wires.

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