A VCSEL array chip and a manufacturing method thereof

Abstract

The present invention relates to the technical field of vertical cavity surface emitting lasers, and specifically to a VCSEL array chip and a manufacturing method thereof, wherein the VCSEL array chip comprises, from bottom to top, a back electrode, a GaAs substrate, a GaAs buffer layer, an N-DBR, an N-limiting layer, a multi-quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, a P+GaAs, a TaN thin film layer, a contact electrode, and a front electrode; the light exit holes of the VCSEL array chip are arranged in an array; the front electrode is a separated front electrode, which is respectively located in the welding wire area and the contact electrode area of ​​the light exit hole, and is connected through the TaN thin film layer. The present invention optimizes the chip structure, arranges the light exit holes in an array, separates the front electrodes, and connects through the TaN thin film layer, thereby reducing the consumption of the electrode material Au while ensuring conductivity, greatly reducing costs, improving reliability, and facilitating processing.

Description

Technical Field

[0001] The present invention relates to the technical field of vertical cavity surface emitting lasers, and in particular to a VCSEL array chip and a manufacturing method thereof. Background Art

[0002] VCSEL (Vertical Cavity Surface Emitting Laser) chip is a new type of semiconductor laser with the advantages of small size, low threshold current, good temperature characteristics, and easy two-dimensional integration. It is widely used in optical communication, optical interconnection, optical sensing and other fields. With the development of science and technology, the market demand for VCSEL is increasing, especially in occasions requiring high power output, such as laser radar, optical communication, etc. At the same time, the reliability of the chip is also an important factor affecting its application. Therefore, improving the reliability of VCSEL is one of the current research hotspots.

[0003] In the process of VCSEL chip manufacturing, in order to improve the output power and reliability of VCSEL, it is mainly achieved by improving device structure, optimizing material quality, optimizing process, etc. However, while improving power and reliability, the size and cost of the chip will often increase, which is not conducive to the miniaturization and cost reduction of the chip; secondly, the device stability design often cannot effectively cope with the impact of environmental changes and long-term work. Therefore, the cost and reliability of the chip still need to be improved. Summary of the invention

[0004] In view of the problem that the reliability and cost of VCSEL chips in the prior art cannot be taken into account at the same time, the present invention provides a VCSEL array chip and a manufacturing method thereof. The VCSEL array chip device has high reliability, a simple processing process and low cost.

[0005] The present invention provides a VCSEL array chip, which comprises, from bottom to top, a back electrode, a GaAs substrate, a GaAs buffer layer, an N-DBR, an N-limiting layer, a multi-quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, a P+GaAs, a TaN thin film layer, a contact electrode, and a front electrode;

[0006] The light exit holes of the VCSEL array chip are arranged in an array;

[0007] The front electrode is a separated front electrode, which is respectively located in the welding line area and the contact electrode area of ​​the light exit hole, and is connected through the TaN thin film layer.

[0008] The present invention optimizes the structure of the VCSEL chip, arranges the light output holes in an array, and separates the front electrodes in the light output hole area from the front electrodes in the wire bonding area, which are then connected through a TaN film layer, thereby effectively reducing the consumption of the electrode material Au while ensuring conductivity, thereby greatly reducing the cost. At the same time, TaN, as an important transition metal nitride, has the characteristics of high melting point, high hardness, high density, high thermal conductivity, etc., and is suitable for high temperature environments. In addition, TaN has strong chemical inertness, is not easily corroded in corrosive gases and liquids, and has good oxidation resistance at high temperatures. The introduction of the TaN film layer can improve the reliability of the chip.

[0009] Furthermore, in the above technical solution, the TaN thin film layer is an insulating layer, a transition layer, and a conductive layer from bottom to top, wherein the thickness of the insulating layer is 3000±20 angstroms, the thickness of the transition layer is 1000±10 angstroms, and the thickness of the conductive layer is 4000±30 angstroms. The TaN thin film layer in this technical solution is a multi-layer TaN structure, which is a film layer with different functions obtained by a single magnetron sputtering process, wherein the bottom insulating layer plays the role of insulating protection, and the surface conductive layer is a metal-like structure that can conduct electricity and play the role of connecting the front electrode.

[0010] Furthermore, in the above technical solution, the contact electrode is located at the top of the step of the light-emitting hole and is in a circular ring shape, with a thickness of 3000±20 angstroms, and the materials are Ti / Pt / Au in sequence.

[0011] Furthermore, in the above technical solution, an oxidation restriction ring is formed in a region on the oxide layer corresponding to the light exit hole, and the inner diameter of the oxidation restriction ring is ≤ the inner diameter of the contact electrode.

[0012] Furthermore, in the above technical solution, the thickness of the front electrode is 20000±100 angstroms, and the materials are Ti / Ni / Pd / Au in sequence.

[0013] Furthermore, in the above technical solution, the thickness of the back electrode is 5000±50 angstroms, and the materials are AuGe / Au respectively.

[0014] The present invention also provides a method for manufacturing a VCSEL array chip, comprising the following steps:

[0015] S1. On a GaAs substrate, an AlGaAs laser epitaxial wafer is grown by MOCVD (metal organic chemical vapor deposition), wherein the epitaxial wafer sequentially grows a GaAs buffer layer, an N-DBR, an N-limiting layer, a multi-quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, and a P+GaAs on the GaAs substrate; wherein the number of pairs of the N-DBR is 45 pairs to 50 pairs, and the number of pairs of the P-DBR is 16 pairs to 22 pairs;

[0016] S2. Using organic solution cleaning, negative resist overprinting, electron beam evaporation and negative resist stripping to make contact electrodes on the surface of the epitaxial wafer;

[0017] S3. Using positive resist overlay to produce an oxidation channel pattern, etching an oxidation channel pattern with a certain width by ICP (inductively coupled plasma) etching, etching to a depth of N-DBR layer to form a light output hole step, and removing the surface photoresist by using a stripping solution;

[0018] S4. Wet oxidation is performed on the oxide layer corresponding to the contact electrode by a wet oxidation furnace to form an oxidation restriction ring;

[0019] S5. Clean the wafer with a weak alkaline ammonia solution, magnetron sputter a TaN thin film layer using a negative resist overlay method, and cooperate with negative resist stripping to form a patterned TaN thin film pattern on the surface;

[0020] S6. Using organic solution cleaning, negative resist overprinting, electron beam evaporation and negative resist stripping to make a separate front electrode on the surface of the epitaxial wafer;

[0021] S7. Thinning the GaAs substrate by mechanical grinding and performing CMP polishing (chemical mechanical polishing), cleaning the back surface with an acid solution, and evaporating the back electrode by electron beam evaporation;

[0022] S8. Finally, the chips are cut and separated at a fixed interval to form VCESL single chips and then AOI sorting is performed.

[0023] In the chip preparation process, the present invention preferentially manufactures the annular contact electrode of the array light output hole, and then manufactures an oxide restriction ring less than or equal to the inner diameter of the contact electrode ring on the corresponding oxide layer to constrain the current and improve the light output power. Then, by controlling the sputtering conditions, especially the flow rate of nitrogen, by magnetron sputtering, the manufacture of TaN thin film layers with different film layer functions is realized at one time. There are three layers in total, wherein the bottom layer plays an insulating protection role and effectively ensures the reliability of the chip, and the surface layer plays a conductive role to connect the separated front electrodes, which greatly reduces the consumption of materials such as Au. The manufacturing method is easy to process, low in cost, and good in reliability. At the same time, the light output efficiency can be improved, and the overall performance is excellent.

[0024] Furthermore, in the above technical solution S3, the ICP etching power is 500W, the pressure is 30mTorr, the BCl3 flow rate is 25sccm, the Cl2 flow rate is 8sccm, the N2 flow rate is 30sccm, the SF6 flow rate is 50sccm, and the step slope of the light output hole is 90°.

[0025] Furthermore, in the above technical solution S5, the process of magnetron sputtering TaN thin film layer is: vacuum degree is 1Torr-10Torr, purity of tantalum target is 99.99%, temperature of substrate is 25°C, and a mixed gas of argon and nitrogen is introduced, wherein, in the first stage, the flow rate of argon is 20sccm, the flow rate of nitrogen is 30sccm-40sccm, the sputtering power is set to 200W, and the sputtering time is 30min, to obtain an insulating layer; in the second stage, the flow rate of argon is 20sccm, the flow rate of nitrogen is 5sccm-10sccm, the sputtering power is set to 200W, and the sputtering time is 10min, to obtain a transition layer; in the third stage, the flow rate of argon is 20sccm, the flow rate of nitrogen is 0.5sccm-1sccm, the sputtering power is set to 200W, and the sputtering time is 40min, to obtain a conductive layer. In the present technical solution, the TaN thin film layer adopts the magnetron sputtering process. By adjusting the nitrogen flow rate, TaN thin film layers with different characteristics can be obtained. For example, when the first layer adopts a high nitrogen flow rate, the thin film layer exhibits insulating properties, and when the second layer adopts a conventional nitrogen flow rate, the thin film layer exhibits semiconductor properties. When the third layer adopts a low nitrogen flow rate, the thin film has properties close to those of metal and has good conductivity.

[0026] Furthermore, in the above technical solution S7, the acidic solution is a mixture of hydrochloric acid and water in a volume ratio of 1:20.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. The present invention optimizes the chip structure, arranges the light output holes in an array, and separates the front electrodes in each light output hole area from the front electrodes in the wire bonding area, which are then connected through a TaN thin film layer. This effectively reduces the consumption of electrode material Au while ensuring conductivity, thereby greatly reducing costs. At the same time, the introduction of a high-performance TaN thin film layer can improve the reliability of the chip.

[0029] 2. The chip of the present invention preferentially manufactures annular contact electrodes for array light output holes, and then manufactures an oxide restriction ring on the corresponding oxide layer that is less than or equal to the inner diameter of the contact electrode ring to constrain the current and increase the light output power. Then, by controlling the sputtering conditions by magnetron sputtering, the manufacture of different film layers is achieved at one time. The obtained TaN thin film layer has three layers, of which the bottom layer serves as an insulating protection to effectively ensure the reliability of the chip, and the surface layer serves as a conductor to connect the separated front electrodes, greatly reducing the consumption of materials such as Au. The manufacturing method is easy to process, low in cost, and has good reliability. At the same time, it can also ensure light output efficiency and has excellent overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of the epitaxial wafer structure of the VCSEL array chip of the present invention;

[0031] Figure 2 It is a schematic diagram of the structure of the VCSEL array chip of the present invention.

[0032] Explanation of the numbers in the schematic diagram:

[0033] 1. GaAs substrate; 2. GaAs buffer layer; 3. N-DBR; 4. N-limiting layer; 5. Multi-quantum well active layer; 6. P-limiting layer; 7. Oxide layer; 8. P-DBR; 9. P+GaAs; 10. Contact electrode; 11. Oxide limiting ring; 12. TaN thin film layer; 12-1. Insulating layer; 12-2. Transition layer; 12-3. Conductive layer; 13. Front electrode; 14. Back electrode. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] In the description of the present application, it should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present application.

[0036] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0037] See also Figure 1 to Figure 2It should be noted that the diagrams provided in this embodiment are only schematic illustrations of the basic concept of the present invention, and the diagrams only show the components related to the present invention rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complicated. The organic solution used for cleaning is a commonly used organic solvent such as acetone and isopropyl alcohol.

[0038] Some embodiments of the present invention provide a VCSEL array chip, the structural schematic diagram of which is as follows Figure 1 As shown, the VCSEL array chip is composed of a back electrode 14, a GaAs substrate 1, a GaAs buffer layer 2, an N-DBR 3, an N-limiting layer 4, a multi-quantum well active layer 5, a P-limiting layer 6, an oxide layer 7, a P-DBR 8, a P+GaAs 9, a TaN thin film layer 12, a contact electrode 10, and a front electrode 13 from bottom to top;

[0039] Specifically, the light exit holes of the VCSEL array chip are arranged in an array. Figure 1 This is only a specific embodiment and is not limited to three rows, but can be any array;

[0040] The front electrode is a separated front electrode, which is located in the wire bonding area and the contact electrode area of ​​the light exit hole, and is connected through the TaN thin film layer, more specifically, through the surface conductive layer. In this way, only the front electrode material needs to be used in the wire bonding area and the contact electrode area, which greatly saves the consumption of materials such as Au and reduces costs.

[0041] Specifically, the TaN thin film layer is an insulating layer, a transition layer, and a conductive layer from bottom to top, wherein the thickness of the insulating layer is 3000±20 angstroms, the thickness of the transition layer is 1000±10 angstroms, and the thickness of the conductive layer is 4000±30 angstroms. The TaN thin film layer has three layers, wherein the bottom layer is an insulating layer with an insulating protection function to improve the reliability of the chip, the middle layer is a transition layer, and the surface layer is a conductive layer with conductivity that can connect the front electrode, ensuring the conductivity of the chip while reducing material costs.

[0042] Specifically, the contact electrode is located at the top of the step of the light-emitting hole and is in a circular ring shape with a thickness of 3000±20 angstroms. The materials are Ti / Pt / Au in sequence.

[0043] Specifically, an oxidation restriction ring 11 is formed in a region on the oxidation layer corresponding to the light exit hole, and the inner diameter of the oxidation restriction ring is less than or equal to the inner diameter of the contact electrode, thereby ensuring light extraction efficiency.

[0044] Some other embodiments of the present invention further provide a method for manufacturing a VCSEL array chip, comprising the following steps:

[0045] S1. Schematic diagram of the structure of AlGaAs laser epitaxial wafer grown on GaAs substrate using MOCVD Figure 1 As shown, the epitaxial wafer sequentially grows a GaAs buffer layer 2, an N-DBR 3, an N-limiting layer 4, a multi-quantum well active layer 5, a P-limiting layer 6, an oxide layer 7, a P-DBR 8, and a P+GaAs 9 on a GaAs substrate 1; wherein the number of pairs of N-DBRs is 45 pairs to 50 pairs, and the number of pairs of P-DBRs is 16 pairs to 22 pairs.

[0046] S2. Use organic solution cleaning, negative resist overprinting, electron beam evaporation and negative resist stripping to make contact electrodes on the surface of the epitaxial wafer; specifically, use organic solution cleaning, negative resist overprinting, electron beam evaporation and negative resist stripping to make circular contact electrodes on the surface of the epitaxial wafer, wherein the thickness of the contact electrode is 3000±20 angstroms, and includes Ti / Pt / Au metal materials in sequence; the contact electrode ring is located on the step of the light output hole.

[0047] S3. Use positive resist lithography to produce an oxidation channel pattern, and use ICP etching to etch an oxidation channel pattern with a certain width, and etch to a depth of N-DBR layer to form a light-emitting hole step, and use a stripping solution to remove the surface photoresist; specifically, the etching process is monitored by OES (spark photoelectric direct reading spectroscopy), and the etching depth is stopped when it exceeds 2 pairs to 4 pairs of N-DBRs. The ICP etching power is 500W, the pressure is 30mTorr, the BCl3 flow rate is 25sccm, the Cl2 flow rate is 8sccm, the N2 flow rate is 30sccm, the SF6 flow rate is 50sccm, the slope of the light-emitting hole step is 90°, and the surface photoresist is removed by a stripping solution.

[0048] S4. The oxide layer corresponding to the contact electrode is wet oxidized in a wet oxidation furnace to form an oxidation restriction ring. Specifically, the inner diameter of the oxidation restriction ring is less than or equal to the inner diameter of the contact electrode ring, which can constrain the current and improve the light output power.

[0049] S5. Clean the wafer with a weak alkaline ammonia solution, use a negative resist overlay method, magnetron sputter a TaN film layer, and cooperate with negative resist stripping to form a patterned TaN film pattern on the surface; specifically, the TaN film layer has three layers, and the magnetron sputtering process is: the vacuum degree is 1Torr-10Torr, the purity of the tantalum target is 99.99%, the temperature of the substrate is 25°C, and a mixed gas of argon and nitrogen is introduced, wherein the flow rate of argon in the first stage is 20sccm, the flow rate of nitrogen is 30sccm-40sccm, the sputtering power is set to 200W, and the sputtering time is The first step is to obtain an insulating layer 12-1 with a thickness of 3000±20 angstroms; the second step is to obtain an argon gas flow rate of 20sccm, a nitrogen gas flow rate of 5sccm-10sccm, a sputtering power of 200W, a sputtering time of 10min, and a transition layer 12-2 with a thickness of 1000±10 angstroms; the third step is to obtain an argon gas flow rate of 20sccm, a nitrogen gas flow rate of 0.5sccm-1sccm, a sputtering power of 200W, a sputtering time of 40min, and a conductive layer 12-3 with a thickness of 4000±30 angstroms. By adjusting the nitrogen gas flow rate, TaN thin film layers with different characteristics can be obtained, wherein the first layer adopts a high nitrogen gas flow rate, the thin film layer exhibits insulation, and improves the reliability of the chip; the second layer adopts a conventional nitrogen gas flow rate, the thin film layer exhibits semiconductor properties; when the third layer adopts a low nitrogen gas flow rate, the thin film has properties close to metal, good conductivity, and is used to connect the front electrode to reduce costs.

[0050] S6. Use organic solution cleaning, negative resist etching, electron beam evaporation and negative resist stripping to make a separate front electrode on the surface of the epitaxial wafer; specifically, the thickness of the front electrode is 20000±100 angstroms, and includes Ti / Ni / Pd / Au metal materials in sequence, one part of which is located on the light output hole table and connected to the base electrode, and the other part is located in the welding wire area for packaging and wiring. The total area of ​​the separate front electrode is greatly reduced, which can reduce the production cost.

[0051] S7. Thin the GaAs substrate by mechanical grinding and perform CMP polishing. Clean the back side with an acidic solution and evaporate the back electrode by electron beam evaporation. Specifically, the acidic solution is a mixture of hydrochloric acid and water in a volume ratio of 1:20. The thickness of the back electrode is 5000±50 angstroms. The materials are AuGe / Au in turn, and high-temperature fusion is performed at 360°C.

[0052] S8. Finally, the chips are cut and separated at a fixed interval to form VCESL single chips and then AOI sorting is performed.

[0053] In summary, the present invention optimizes the chip structure, arranges the light output holes in an array, and separates the front electrodes in each light output hole area from the front electrodes in the welding wire area, and then connects them through a TaN thin film layer, thereby effectively reducing the consumption of electrode material Au while ensuring conductivity, thereby greatly reducing costs; at the same time, the introduction of a high-performance TaN thin film layer can also improve the reliability of the chip; by controlling the magnetron sputtering conditions, the manufacture of different film layers is achieved at one time, and the obtained TaN thin film layer has a total of three layers, wherein the bottom layer plays an insulating and protective role, effectively ensuring the reliability of the chip, and the surface layer plays a conductive role to connect the separated front electrodes, thereby greatly reducing the consumption of materials such as Au. The manufacturing method is easy to process, low in cost, good in reliability, and excellent in overall performance, and effectively solves the problem in the prior art that the reliability and cost of VCSEL chips cannot be taken into account at the same time.

[0054] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A VCSEL array chip, characterized in that: The VCSEL array chip is composed of a back electrode, a GaAs substrate, a GaAs buffer layer, an N-DBR, an N-limiting layer, a multi-quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, a P+GaAs, a TaN thin film layer, a contact electrode, and a front electrode from bottom to top; The light exit holes of the VCSEL array chip are arranged in an array; The front electrode is a separated front electrode, which is respectively located in the welding line area and the contact electrode area of ​​the light exit hole, and is connected through the TaN thin film layer; The TaN thin film layer is a multi-layer TaN structure, which includes an insulating layer, a transition layer, and a conductive layer from bottom to top, wherein the thickness of the insulating layer is 3000±20 angstroms, the thickness of the transition layer is 1000±10 angstroms, and the thickness of the conductive layer is 4000±30 angstroms; the insulating layer, the transition layer, and the conductive layer are obtained by controlling different magnetron sputtering conditions using a magnetron sputtering process.

2. A VCSEL array chip according to claim 1, characterized in that: The contact electrode is located at the top of the step of the light-emitting hole and is in a circular ring shape, with a thickness of 3000±20 angstroms, and the materials are Ti / Pt / Au in sequence.

3. A VCSEL array chip according to claim 2, characterized in that: An oxidation restriction ring is formed in a region of the oxidation layer corresponding to the light exit hole, and the inner diameter of the oxidation restriction ring is less than or equal to the inner diameter of the contact electrode.

4. A VCSEL array chip according to claim 1, characterized in that: The thickness of the front electrode is 20000±100 angstroms, and the materials are Ti / Ni / Pd / Au in sequence.

5. A VCSEL array chip according to claim 1, characterized in that: The thickness of the back electrode is 5000±50 angstroms, and the materials are AuGe / Au respectively.

6. A method for manufacturing a VCSEL array chip according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1. On a GaAs substrate, an AlGaAs laser epitaxial wafer is grown by MOCVD, wherein a GaAs buffer layer, an N-DBR, an N-limiting layer, a multi-quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, and a P+GaAs are sequentially grown on the GaAs substrate; S2. Using organic solution cleaning, negative resist overprinting, electron beam evaporation and negative resist stripping to make contact electrodes on the surface of the epitaxial wafer; S3. An oxidation channel pattern is produced by positive photolithography, and an oxidation channel pattern having a certain width is etched by ICP etching, the etching depth reaches the N-DBR layer, and the surface photoresist is removed by a stripping solution; S4. Wet oxidation is performed on the oxide layer corresponding to the contact electrode by a wet oxidation furnace to form an oxidation restriction ring; S5. Clean the wafer with a weak alkaline ammonia solution, magnetron sputter a TaN thin film layer using a negative resist overlay method, and cooperate with negative resist stripping to form a patterned TaN thin film pattern on the surface; S6. Using organic solution cleaning, negative resist overprinting, electron beam evaporation and negative resist stripping to make a separate front electrode on the surface of the epitaxial wafer; S7. Thinning the GaAs substrate by mechanical grinding and performing CMP polishing, cleaning the back surface with an acid solution, and depositing a back electrode by electron beam evaporation; S8. Finally, the chips are cut and separated at a fixed interval to form VCESL single chips and then AOI sorting is performed.

7. The method for manufacturing a VCSEL array chip according to claim 6, characterized in that: In S3, the ICP etching power is 500 W, the pressure is 30 mTorr, the BCl3 flow rate is 25 sccm, the Cl2 flow rate is 8 sccm, the N2 flow rate is 30 sccm, and the SF6 flow rate is 50 sccm.

8. The method for manufacturing a VCSEL array chip according to claim 6, characterized in that: In S5, the process of magnetron sputtering TaN thin film layer is as follows: vacuum degree is 1Torr-10Torr, purity of tantalum target is 99.99%, temperature of substrate is 25°C, and mixed gas of argon and nitrogen is introduced, wherein, in the first stage, the flow rate of argon is 20sccm, the flow rate of nitrogen is 30sccm-40sccm, the sputtering power is set to 200W, and the sputtering time is 30min, to obtain an insulating layer; in the second stage, the flow rate of argon is 20sccm, the flow rate of nitrogen is 5sccm-10sccm, the sputtering power is set to 200W, and the sputtering time is 10min, to obtain a transition layer; in the third stage, the flow rate of argon is 20sccm, the flow rate of nitrogen is 0.5sccm-1sccm, the sputtering power is set to 200W, and the sputtering time is 40min, to obtain a conductive layer.

9. The method for manufacturing a VCSEL array chip according to claim 6, characterized in that: In S7, the acidic solution is a mixture of hydrochloric acid and water in a volume ratio of 1:20.

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