A radio frequency switch circuit, chip and electronic device for realizing harmonic compensation

Abstract

The present invention discloses a radio frequency switch circuit, chip and electronic device for realizing harmonic compensation. The radio frequency switch circuit comprises a switch unit, a gate end bias unit, a body end bias unit, a source drain end bias unit, a harmonic compensation unit and a compensation bias unit; wherein the gate end bias unit, the body end bias unit and the source drain end bias unit are respectively connected to the switch unit to provide bias voltages for the switch unit; the harmonic compensation unit is connected to the switch unit to compensate for the harmonic components generated by the switch unit; the compensation bias unit is connected to the harmonic compensation unit to provide a compensation bias voltage for the harmonic compensation unit. When the radio frequency switch circuit is in the off state, the harmonic components generated by the harmonic compensation unit compensate and offset the harmonic components generated by the switch unit to improve the harmonic performance of the radio frequency switch circuit.

Description

Technical Field

[0001] The present invention relates to a radio frequency switch circuit for realizing harmonic compensation, and also relates to an integrated circuit chip including the radio frequency switch circuit and corresponding electronic equipment, belonging to the technical field of radio frequency integrated circuits. Background Art

[0002] In wireless communication systems, the RF switch circuit is an important component of the RF front-end module. Its function is to accurately switch the transmission path of the RF signal and select the corresponding RF path. In the case of a shared antenna in the wireless communication system, the reception and transmission of RF signals can be realized. The RF transceiver is usually located at the front end of the wireless communication device, and the harmonic processing capability of the RF switch circuit will directly affect the signal processing capability of the RF transceiver. Therefore, improving the harmonic performance of the RF switch circuit is very necessary for high-performance RF transceivers.

[0003] In the prior art, a typical RF switch circuit is as follows: Figure 1 As shown, in order to improve the voltage resistance of the RF switch circuit, the RF switch circuit usually adopts a stacked structure consisting of multiple switching transistors M1 to M N The gate terminal of each switching transistor is connected to a bias resistor R G The gate bias network is formed, and the bias resistor R B The bias resistor R connected to the source and drain of each switching transistor forms a body bias network. ds The RF switch circuit adjusts the gate bias voltage V GC and the body bias voltage V BC The size of the switch transistor is used to control the conduction and shutdown of the switch transistor. When used for antenna impedance tuning, the RF switch circuit is usually in the off state. When in the off state, due to the inherent nonlinear characteristics of the stacked switch transistors, as the antenna input power increases, the stacked switch transistors will generate a large number of undesirable harmonics, which are transmitted from the RF switch circuit to the receiver circuit, thereby deteriorating the receiver noise or antenna efficiency.

[0004] In the Chinese patent application with application number 202211093483.5, a radio frequency switch circuit for optimizing the third harmonic is disclosed. The radio frequency switch circuit includes a harmonic compensation circuit and a power detection bias circuit; the harmonic compensation circuit consists of a bias diode compensation branch and two series switch branches, a total of three sub-modules connected in series; the series switch branch is composed of a gate common terminal resistor and M-level switch units, and each level of switch unit includes a switching transistor, a bias transistor, a source-drain resistor, and a gate bias resistor; the power detection bias circuit provides different bias voltage values ​​according to the power of the input signal of the radio frequency switch circuit to obtain corresponding harmonic compensation. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a radio frequency switching circuit for achieving harmonic compensation.

[0006] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the radio frequency switch circuit and a corresponding electronic device.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, there is provided a radio frequency switch circuit for implementing harmonic compensation, comprising a switch unit, a gate end bias unit, a body end bias unit, a source-drain end bias unit, a harmonic compensation unit and a compensation bias unit; wherein,

[0009] The switch unit is used to connect or disconnect the transmission path of the radio frequency signal;

[0010] The gate bias unit, the body bias unit, and the source-drain bias unit are respectively connected to the switch unit to provide the switch unit with a gate bias voltage, a body bias voltage, and a bias voltage between the source and drain terminals;

[0011] The harmonic compensation unit is connected to the switch unit and is used to compensate for the harmonic components generated by the switch unit;

[0012] The compensation bias unit is connected to the harmonic compensation unit to provide a compensation bias voltage for the harmonic compensation unit;

[0013] When the radio frequency switch circuit is in an off state, the harmonic component generated by the harmonic compensation unit compensates and cancels the harmonic component generated by the switch unit.

[0014] Preferably, the switch unit is composed of N switch transistors stacked in sequence with source and drain connected, the source end of the first switch transistor is connected to the RF signal input end, and the drain end of the Nth switch transistor is connected to the RF signal output end; wherein N is a positive integer greater than or equal to 2.

[0015] Preferably, the harmonic compensation unit is composed of N compensation modules connected in series in sequence, the first end and the second end of each compensation module are respectively connected to the source end and the drain end of a corresponding switching transistor in the switching unit, and the bias end of each compensation module is respectively connected to the compensation bias unit.

[0016] Preferably, the compensation module includes a first NMOS transistor, a second NMOS transistor and a diode branch consisting of X diodes connected in series in positive and negative directions; wherein,

[0017] The gate end of the first NMOS tube is used as the first end, and the gate end of the second NMOS tube is used as the second end, respectively connected to the source end and the drain end of a corresponding switching transistor in the switching unit; the body ends of the first NMOS tube and the second NMOS tube are respectively connected in parallel with their own source ends and then connected to the negative electrode of the diode branch; the drain ends of the first NMOS tube and the second NMOS tube are both connected to the positive electrode of the diode branch and then connected to the first end of the corresponding compensation bias resistor in the compensation bias unit as a bias end; wherein X is a positive integer.

[0018] Preferably, when the RF switch circuit is in an on state, the compensation module is equivalent to a tiny parasitic capacitor.

[0019] Preferably, when the size of the first NMOS tube and the second NMOS tube in the compensation module is 1 / 20 of the size of the switching transistor, the equivalent micro parasitic capacitance of the compensation module is 1 / 40 of the parasitic capacitance between the source and drain of the switching transistor itself.

[0020] Preferably, when the RF switch circuit is in the off state, the first NMOS tube and the second NMOS tube in the compensation module generate harmonic components alternately in the positive half cycle and the negative half cycle to compensate for the harmonic components generated by the switching transistor.

[0021] Preferably, the size of the compensated harmonic component is adjusted by adjusting the on or off working state of the diode branch in the compensation module in combination with adjusting the number of diodes and / or the size of the compensation bias voltage.

[0022] Preferably, the compensation bias unit is composed of N compensation bias resistors connected in series in sequence, and the first ends of the N compensation bias resistors are respectively connected to the bias end of a corresponding compensation module in the harmonic compensation unit in sequence, and the second end of the Nth compensation bias resistor is connected to the compensation bias voltage end.

[0023] Preferably, the gate bias unit is composed of N gate bias resistors connected in series in sequence, and the first ends of the N gate bias resistors are respectively connected to the gate end of a corresponding switching transistor in the switch unit in sequence, and the second end of the Nth gate bias resistor is connected to the gate bias voltage end.

[0024] Preferably, the body-end bias unit is composed of N individual-end bias resistors connected in series in sequence, and the first ends of the N individual-end bias resistors are respectively connected to the body end of a corresponding switching transistor in the switch unit in sequence, and the second end of the Nth individual-end bias resistor is connected to the body-end bias voltage terminal.

[0025] Preferably, the source-drain bias unit is composed of N source-drain bias resistors connected in series in sequence, and both ends of each source-drain bias resistor are respectively connected to the source and drain of a corresponding switching transistor in the switching unit.

[0026] According to a second aspect of an embodiment of the present invention, there is provided an integrated circuit chip, wherein the integrated circuit chip includes the above-mentioned radio frequency switch circuit for realizing harmonic compensation.

[0027] According to a third aspect of an embodiment of the present invention, an electronic device is provided, wherein the electronic device includes the above-mentioned radio frequency switch circuit for realizing harmonic compensation.

[0028] Compared with the prior art, the RF switch circuit for implementing harmonic compensation provided by the present invention adopts a technical solution in which the compensation module in the harmonic compensation unit and the switch transistor in the switch unit are connected to each other in a corresponding manner, so that the harmonic component generated by the harmonic compensation unit compensates or offsets the undesirable harmonic component generated by the switch unit, so as to improve the harmonic performance of the RF switch circuit. Therefore, the RF switch circuit for implementing harmonic compensation provided by the present invention has the beneficial effects of ingenious and reasonable circuit design, low cost, and excellent harmonic performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A circuit schematic diagram of a typical radio frequency switch circuit in the prior art;

[0030] Figure 2 This is a principle wiring diagram of a radio frequency switch circuit for achieving harmonic compensation in an embodiment of the present invention;

[0031] Figure 3 A curve diagram showing changes in the source terminal voltage and the drain terminal voltage of the first switch transistor when the radio frequency switch circuit is in the off state in an embodiment of the present invention;

[0032] Figure 4 This is a curve diagram of the change of the drain terminal voltage of the first NMOS tube and the second NMOS tube in the compensation module when the RF switch circuit is in the off state in the embodiment of the present invention;

[0033] Figure 5 This is a curve diagram showing the change of the gate-drain voltage of the first NMOS tube and the second NMOS tube in the compensation module when the radio frequency switch circuit is in the off state in an embodiment of the present invention;

[0034] Figure 6 This is a curve diagram showing the change of the gate-source voltage of the first NMOS tube and the second NMOS tube in the compensation module when the RF switch circuit is in the off state in an embodiment of the present invention;

[0035] Figure 7This is a comparison diagram of simulation measurements on third-order harmonics between the prior art solution and the technical solution provided by the embodiment of the present invention;

[0036] Figure 8 The diagram is a schematic diagram of an electronic device using the radio frequency switch circuit provided by the present invention. DETAILED DESCRIPTION

[0037] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 2 As shown, an RF switch circuit for implementing harmonic compensation provided by an embodiment of the present invention includes a switch unit 100, a gate bias unit 200, a body bias unit 300, a source-drain bias unit 400, a harmonic compensation unit 500, and a compensation bias unit 600. Among them, the gate bias unit, the body bias unit, and the source-drain bias unit are respectively connected to the switch unit to provide the switch unit with a gate bias voltage, a body bias voltage, and a bias voltage between the source and drain terminals; the harmonic compensation unit is connected to the switch unit to compensate for the harmonic components generated by the switch unit; and the compensation bias unit is connected to the harmonic compensation unit to provide a compensation bias voltage for the harmonic compensation unit.

[0039] The switch unit 100 is used to connect or disconnect the transmission path of the radio frequency signal; the switch unit is composed of N switch transistors M1 to M2. N The source and drain are connected in sequence and stacked, the source end of the first switch transistor M1 is connected to the radio frequency signal input end RFin, and the Nth switch transistor M N The drain end is connected to the RF signal output end RFout; wherein N is a positive integer greater than or equal to 2.

[0040] When the radio frequency switch circuit is in the off state, the harmonic components generated by the harmonic compensation unit compensate and offset the harmonic components generated by the switch unit.

[0041] like Figure 2 As shown, in one embodiment of the present invention, the gate bias unit 200 is composed of N gate bias resistors R G The N gate bias resistors R G The first ends of the Nth gate bias resistor R G The second end of the gate bias voltage (V GC ) terminal GC is connected to provide a gate bias voltage for the N switching transistors in the switching unit.

[0042] The body end bias unit 300 is composed of N body end bias resistors R B In series, the N-terminal bias resistor RB The first end of each of the Nth body end bias resistor R B The second end of the body bias voltage (V BC ) terminal BC is connected to provide a body-terminal bias voltage for the N switching transistors in the switching unit.

[0043] The source-drain bias unit 400 is composed of N source-drain bias resistors Rds connected in series in sequence, and both ends of each source-drain bias resistor Rds are respectively connected to the source and drain of a corresponding switching transistor in the switching unit, so as to provide a bias voltage between the source and drain ends for the N switching transistors in the switching unit.

[0044] The harmonic compensation unit 500 is composed of N compensation modules connected in series in sequence, and the first end and the second end of each compensation module are respectively connected to the source end and the drain end of a corresponding switching transistor in the switching unit, so as to compensate for the harmonic components generated by the N switching transistors in the switching unit; the bias end of each compensation module is respectively connected to the compensation bias unit.

[0045] Each compensation module includes a first NMOS tube, a second NMOS tube, and a diode branch formed by positive and negative series connection of X diodes, X is a positive integer, and X≥1. Among them, the gate end of the first NMOS tube is used as the first end, and the gate end of the second NMOS tube is used as the second end, respectively connected to the source end and the drain end of a switch transistor in the switch unit; the body ends of the first NMOS tube and the second NMOS tube are respectively connected in parallel with their own source ends and then connected to the negative electrode of the diode branch; the drain ends of the first NMOS tube and the second NMOS tube are both connected to the positive electrode of the diode branch and then connected to the first end of the corresponding compensation bias resistor in the compensation bias unit as the bias end.

[0046] The compensation bias unit 600 is composed of N compensation bias resistors R N Connected in series in sequence, and N compensation bias resistors R N The first ends of the compensation resistors R N The second end of the compensation bias voltage (V NC ) terminal is NC connected to provide compensation bias voltage for N compensation modules in the harmonic compensation unit.

[0047] In one embodiment of the present invention, when the RF switch circuit is in the on state, the gate bias voltage V GC is 3V, the body bias voltage V BC is 0V, the compensation bias voltage V NC The N switching transistors M1 to M2 in the switch unit areN After all are turned on, the transmission path of the RF signal from the input end RFin to the output end RFout is connected. At this time, each of the N compensation modules in the harmonic compensation unit can be equivalent to a trace parasitic capacitor. Among them, by adjusting the size of the transistor, the size of these trace parasitic capacitors can be effectively controlled. For example, when the size of the NMOS tube (the first NMOS tube and the second NMOS tube) used in the compensation module is reduced to 1 / 20 of the size of the switching transistor, the equivalent trace parasitic capacitance of the compensation module will be reduced to 1 / 40 of the parasitic capacitance between the source and drain of the switching transistor. This means that there is the following relationship between the size of the transistor and its equivalent trace parasitic capacitance: reducing the size of the transistor can significantly reduce the value of its equivalent trace parasitic capacitance. It can be understood that if the relative size of the NMOS tube is further reduced, the equivalent trace parasitic capacitance of the compensation module will continue to decrease; on the contrary, if the relative size of the NMOS tube is increased, the equivalent trace parasitic capacitance of the compensation module will also increase accordingly.

[0048] The following is an analysis and explanation of the compensation module corresponding to the first switch transistor M1. Since the DC (direct current) potentials of the source terminal S1 and the drain terminal D1 of the first switch transistor M1 are both 0V, the first NMOS transistor M1 in the compensation module 11 , the second NMOS tube M 12 The DC potential of the gate terminal of the first NMOS tube M is 0V. 11 , the second NMOS tube M 12 The drain terminal D 11 , D 12 The DC potential is compensated by the bias voltage V NC Therefore, the diode branch is in the cut-off state, and the first NMOS transistor M 11 , the second NMOS tube M 12 The first NMOS tube M 11 , the second NMOS tube M 12 The gate-drain voltage V GD is 1V, the gate and drain terminals are equivalent to a reverse bias parasitic capacitor, and the gate-source voltage V GS is 0V, and there is no equivalent reverse bias parasitic capacitance between the gate terminal and the source terminal. Further, by designing the first NMOS transistor M in the compensation module 11 , the second NMOS tube M 12 The size of is 1 / 20 or less than the size of the first switch transistor M1, so that the equivalent micro parasitic capacitance of each compensation module is 1 / 40 or less of the parasitic capacitance between the source and drain of the switch transistor itself. In this case, its influence on the on-resistance of the switch transistor can be ignored. Therefore, the harmonic compensation method in this embodiment will not introduce negative impact on the on-state of the RF switch circuit.

[0049] In one embodiment of the present invention, when the RF switch circuit is in the off state, the gate bias voltage V GC is -3V, the body bias voltage V BC is -3V, the compensation bias voltage V NC =-1V. Assuming that the RF switch circuit is used for antenna impedance tuning, the signal at the antenna end is usually a sine wave signal. The first NMOS tube and the second NMOS tube in the compensation module generate harmonic components alternately in the positive half cycle and the negative half cycle, which are used to compensate for the harmonic components generated by the switching transistor, which is described in detail below.

[0050] In this embodiment, it is assumed that N=20, X=1, that is, the switch unit consists of 20 switch transistors M1-M 20 The source and drain are connected in sequence and stacked, and the diode branch in the compensation module includes only one diode. Assuming that the voltage of the 20 stacked switch transistors is evenly distributed, the maximum withstand voltage of each switch transistor is 4V. When the first switch transistor M1 reaches the maximum withstand voltage, its source voltage V S1 and drain voltage V D1 The change curve of Figure 3 As shown, the source voltage V S1 The swing is 80V, and the drain voltage V D1 The swing is 76V and the DC potential is 0V.

[0051] At this time, in the harmonic compensation unit, the compensation module corresponding to the first switch transistor M1 is taken as an example for analysis and explanation. 11 , the second NMOS tube M 12 The sizes of the first NMOS tube M are equal. 11 The gate-drain parasitic capacitance Cgd11 and the second NMOS tube M 12 The gate-drain parasitic capacitance Cgd12 of the first NMOS tube M is equal. 11 , the second NMOS tube M 12 Drain D 11 , D 12 The AC voltage of the first NMOS transistor M1 is 1 / 2 of the sum of the AC voltage at the source terminal and the AC voltage at the drain terminal. 11 , the second NMOS tube M 12 Drain D 11 , D 12 The DC voltage is the compensation bias voltage V NC , i.e. -1V. Drain terminal D 11 and D 12 The voltage satisfies the following formula:

[0052] (1)

[0053] in, , The first NMOS tube M 11 , the second NMOS tube M 12 The voltage at the drain terminal, , are the source terminal AC voltage and the drain terminal AC voltage of the first switch transistor M1 respectively, To compensate for the bias voltage.

[0054] The first NMOS tube M 11 , the second NMOS tube M 12 The change curve of drain voltage is as follows: Figure 4 As shown in the figure, from formula (1), we can see that its voltage swing is 78V and the DC voltage is -1V.

[0055] The first NMOS tube M 11 The gate-drain voltage It can be expressed as:

[0056] (2)

[0057] in, The first NMOS tube M 11 The gate voltage.

[0058] Substituting formula (1) into formula (2) we get:

[0059] (3)

[0060] From formula (3), we can know that the first NMOS tube M 11 The gate-drain voltage swing is 2V, and the DC voltage is 1V. Similarly, the second NMOS transistor M 12 The gate-drain voltage for:

[0061] (4)

[0062] (5)

[0063] in, The second NMOS tube M 12 The gate voltage.

[0064] From formula (5), we can know that the second NMOS tube M 12 The gate-drain voltage swing is 2V and the DC voltage is 1V. Figure 5 As shown, the first NMOS tube M 11 The gate-drain voltage With the second NMOS tube M 12 The gate-drain voltage The phases are opposite.

[0065] Assuming that the diode branch is not considered, the first NMOS transistor M 11 The gate-source voltage It can be expressed as:

[0066] (6)

[0067] in, The first NMOS tube M 11 The source voltage.

[0068] Will Substituting into formula (6) and sorting out, we get:

[0069] (7)

[0070] Similarly, the second NMOS tube M can be obtained 12 The gate-source voltage for:

[0071] (8)

[0072] From formula (7) and formula (8), we can know that the first NMOS tube M 11 The gate-source voltage and the second NMOS tube M 12 The gate-source voltage The AC voltage swing is 2V, and the DC voltage is 0V. Figure 6 As shown, the two are in opposite phases.

[0073] Through the above analysis and Figure 5 , Figure 6 As shown in the figure, the first NMOS tube M 11 The gate-drain voltage Always higher than the gate-source voltage , the voltage difference is 1V; the second NMOS tube M 12 The gate-drain voltage Always higher than the gate-source voltage , the voltage difference is 1V; this voltage difference is the compensation bias voltage V NC The absolute value of 1V is greater than the conduction threshold voltage of the diode branch. Therefore, the diode branch in the compensation module is turned on, so that the first NMOS tube M 11 , the second NMOS tube M 12 The source voltage changes with the drain voltage.

[0074] When the RF switch circuit is in the off state, the sine wave RF signal at the input terminal RFin swings between the source and drain of the N switch transistors in the switch unit. The N switch transistors generate a large number of undesirable harmonics due to the parasitic capacitance between their own source and drain, causing the nonlinearity of the RF switch circuit and deteriorating the performance indicators such as the noise or antenna efficiency of the receiver in the system. At this time, the N compensation modules in the harmonic compensation unit, when the diode branch is turned on, the first NMOS tube M 11 , the second NMOS tube M 12 The source voltage changes with the drain voltage. 11 , the second NMOS tube M 12 The phase of the harmonic component generated by the parasitic capacitance between the source and drain terminals is opposite to the phase of the harmonic component generated by the switching transistor. Therefore, the undesired harmonic component generated by the switching unit can be compensated, and part of the harmonic is offset.

[0075] Specifically, when the swinging AC voltage difference between the source terminal and the drain terminal of each switch transistor of the switch unit is larger, the parasitic capacitance of each switch transistor itself introduces more undesirable harmonics. 11 , the second NMOS tube M 12 The larger the gate-drain voltage and gate-source voltage, the larger the gate-drain parasitic capacitance Cgd11, Cgd12 and the gate-source parasitic capacitance Cgs11, Cgs12, and the larger the compensation harmonic component generated. Figure 3 and Figure 5 As shown, at the peak of the positive half cycle of the sine wave, that is, when t = 0.25us, the voltage swing between the source and drain of the switching transistor reaches a maximum value of 4V, the absolute value of the AC voltage at the source end of the switching transistor is 80V, and the absolute value of the AC voltage at the drain end is 76V, and the undesirable harmonics generated by the switching transistor are relatively large. At this time, in the compensation module, the first NMOS tube M 11 The gate-drain voltage is 3V, the second NMOS tube M 12 The gate-drain voltage is -1V. At the same time, due to the first NMOS tube M 11 , the second NMOS tube M 12 The source voltage changes with the drain voltage, so the first NMOS tube M 11 The gate-source voltage Also 3V, the second NMOS tube M 12 The gate-source voltage is also -1V, so the first NMOS tube M 11 At this time, more harmonic components are generated, and the second NMOS tube M 12At this time, basically no harmonics are generated. At the peak of the negative half cycle of the sine wave, that is, when t = 0.75us, the voltage swing between the source and drain of the switching transistor also reaches the maximum value of 4V, the absolute value of the AC voltage at the source end of the switching transistor is 80V, and the absolute value of the AC voltage at the drain end is 76V. The undesirable harmonic components generated by the switching transistor are the same as those at the peak of the positive half cycle. At this time, in the compensation module, the first NMOS tube M 11 The gate-drain voltage is -1V, the second NMOS tube M 12 The gate-drain voltage is 3V. At the same time, due to the first NMOS tube M 11 , the second NMOS tube M 12 The source voltage changes with the drain voltage, so the first NMOS tube M 11 The gate-source voltage Also -1V, the second NMOS tube M 12 The gate-source voltage is also 3V, so the second NMOS tube M 12 At this time, more harmonic components are generated, and the first NMOS tube M 11 Basically, no harmonics are generated at this time. That is, the harmonics generated by the N compensation modules in the harmonic compensation unit in the negative half cycle of the sine wave are the same as those generated in the positive half cycle, and are both used to offset the undesirable harmonic components generated by the switching transistor.

[0076] In other embodiments of the present invention, it is assumed that in the above parameter settings, the compensation bias voltage V NC If it is not set to -1V, the number of diodes X included in the diode branch of the compensation module is not 1. NC When the absolute value of does not reach the conduction threshold voltage of the diode branch in the compensation module, the diode branch is in the cut-off state, and the first NMOS transistor M in the compensation module is turned off. 11 , the second NMOS tube M 12 The source voltage of the first NMOS transistor M no longer changes with the change of the drain voltage, and the source DC voltage is 0V. 11 The gate-source voltage and the second NMOS tube M 12 The gate-source voltage like Figure 6 At the peak of the positive half cycle of the sine wave, i.e., at t = 0.25us, the first NMOS tube M 11 The gate-drain voltage is 3V, the second NMOS tube M 12 The gate-drain voltage is -1V, and at the same time, the first NMOS tube M 11 The gate-source voltage is 2V, the second NMOS tube M 12 The gate-source voltage is -2V, therefore, compared to the diode conduction state, the first NMOS tube M 11 At this time, the harmonic components generated are reduced, and the second NMOS tube M 12 At this time, harmonics are still basically not generated. Similarly, at the peak of the negative half cycle of the sine wave, that is, at t = 0.75us, the first NMOS tube M 11 The gate-drain voltage is -1V, the second NMOS tube M 12 The gate-drain voltage is 3V, and at the same time, the first NMOS tube M 11 The gate-drain voltage is -2V, the second NMOS tube M 12 The gate-drain voltage is 2V, therefore, compared to the diode conduction state, the second NMOS tube M 12 At this time, the harmonic components generated are reduced, and the first NMOS tube M 11 At this time, harmonics are basically not generated. From the above analysis, it can be seen that by adjusting the working state of the diode branch in the compensation module, including adjusting the number of diodes and / or the compensation bias voltage V NC The size of the harmonic component can be adjusted by adjusting the size of the compensation harmonic component.

[0077] The specific structure and working principle of a radio frequency switch circuit for realizing harmonic compensation provided by an embodiment of the present invention are described in detail above. In order to verify the superiority of the radio frequency switch circuit provided by an embodiment of the present invention in terms of harmonic performance, the inventors have described the technical solution in this embodiment and Figure 1 The prior art solutions shown in the figure were subjected to simulation comparison tests of third-order harmonics. The simulation test results are shown in Figure 7 shown.

[0078] exist Figure 7 In the figure, the X-axis is the input power of the RF circuit, and the Y-axis is the third-order harmonic component, both in dBm. Figure 7 It can be seen that when the input power of the RF signal increases to 48dBm, the third-order harmonic generated by the RF switch circuit of the prior art solution is -28dBm, while the third-order harmonic generated by the RF switch circuit provided in the embodiment of the present invention is -42dBm. Compared with the prior art solution, in the technical solution provided in the embodiment of the present invention, the third harmonic achieves 14dB compensation optimization, and the harmonic compensation effect is very obvious, which can significantly improve the efficiency of the antenna under high-power working conditions, thereby enhancing the performance and reliability of the wireless communication system.

[0079] It should be noted that the above embodiments are only examples. In other embodiments of the present invention, the circuit structures of the gate bias unit 200, the body bias unit 300, the source-drain bias unit 400 and the compensation bias unit 600 can be implemented in other ways to achieve the corresponding biasing effect, and the present invention is not limited to this.

[0080] Based on the above-mentioned RF switch circuit, an embodiment of the present invention further provides an integrated circuit chip, which includes the above-mentioned RF switch circuit for realizing harmonic compensation, and is used as an important component of the RF front-end module in a wireless communication system. Its function is to accurately switch the transmission path of the RF signal and select the corresponding RF path. In the case of a shared antenna in the wireless communication system, the reception and transmission of RF signals can be realized; it can also be applied to antenna impedance tuning to improve antenna efficiency. The specific structure of the RF switch circuit for realizing harmonic compensation in the integrated circuit chip will not be described in detail here.

[0081] In addition, the RF switch circuit for implementing harmonic compensation provided by the present invention can be used in electronic devices as an important component of communication components. The electronic equipment mentioned here refers to computer equipment that can be used in a mobile environment and supports multiple communication formats such as GSM, EDGE, CDMA, TD_SCDMA, WCDMA, TDD_LTE, FDD_LTE, NR, etc., including mobile phones, laptops, tablet computers, car computers, etc. In addition, the technical solution provided by the present invention is also applicable to other occasions where RF integrated circuits are applied, such as communication base stations, smart connected cars, etc.

[0082] In one embodiment of the present invention, Figure 8 As shown, the electronic device includes at least a processor, a memory and a communication component, and may further include a sensor component, a power component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, communication component, sensor component, power component, multimedia component and input / output interface are all connected to the processor. The memory may be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor may be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. can all be implemented using general components, which will not be described in detail here.

[0083] In summary, compared with the prior art, the RF switch circuit for implementing harmonic compensation provided by the present invention adopts a technical solution in which the compensation module in the harmonic compensation unit and the switch transistor in the switch unit are connected to each other in a corresponding manner, so that the harmonic component generated by the harmonic compensation unit compensates or offsets the undesirable harmonic component generated by the switch unit, so as to improve the harmonic performance of the RF switch circuit. Therefore, the RF switch circuit for implementing harmonic compensation provided by the present invention has the beneficial effects of ingenious and reasonable circuit design, low cost, and excellent harmonic performance.

[0084] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0085] The above is a detailed description of the RF switch circuit, chip and electronic device for implementing harmonic compensation provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A radio frequency switching circuit for achieving harmonic compensation, characterized in that It includes a switch unit, a gate bias unit, a body bias unit, a source-drain bias unit, a harmonic compensation unit and a compensation bias unit; wherein, The switch unit is used to connect or disconnect the transmission path of the radio frequency signal; The gate bias unit, the body bias unit, and the source-drain bias unit are respectively connected to the switch unit to provide the switch unit with a gate bias voltage, a body bias voltage, and a bias voltage between the source and drain terminals; The harmonic compensation unit is connected to the switch unit and is used to compensate for the harmonic components generated by the switch unit; the harmonic compensation unit is composed of N compensation modules connected in series in sequence, each of which includes a first NMOS tube, a second NMOS tube and a diode branch composed of X diodes connected in series in positive and negative directions; wherein the gate end of the first NMOS tube is used as the first end, and the gate end of the second NMOS tube is used as the second end, respectively connected to the source end and the drain end of a corresponding switch transistor in the switch unit; the body ends of the first NMOS tube and the second NMOS tube are respectively connected in parallel with their own source ends and then connected to the negative electrode of the diode branch; the drain ends of the first NMOS tube and the second NMOS tube are both connected to the positive electrode of the diode branch and then connected to the first end of the corresponding compensation bias resistor in the compensation bias unit as a bias end; wherein N is a positive integer greater than or equal to 2, and X is a positive integer; The compensation bias unit is connected to the harmonic compensation unit to provide a compensation bias voltage for the harmonic compensation unit; When the radio frequency switch circuit is in an off state, the harmonic component generated by the harmonic compensation unit compensates and cancels the harmonic component generated by the switch unit.

2. The radio frequency switch circuit for realizing harmonic compensation according to claim 1, characterized in that: The switch unit is composed of N switch transistors which are stacked in sequence with their sources and drains connected. The source end of the first switch transistor is connected to the RF signal input end, and the drain end of the Nth switch transistor is connected to the RF signal output end.

3. The radio frequency switch circuit for realizing harmonic compensation according to claim 1, characterized in that: The first end and the second end of each compensation module are respectively connected to the source end and the drain end of a corresponding switching transistor in the switching unit, and the bias end of each compensation module is respectively connected to the compensation bias unit.

4. The radio frequency switch circuit for realizing harmonic compensation according to claim 1, characterized in that: When the radio frequency switch circuit is in an on state, the compensation module is equivalent to a tiny parasitic capacitor.

5. The radio frequency switch circuit for achieving harmonic compensation according to claim 4, characterized in that: When the size of the first NMOS tube and the second NMOS tube in the compensation module is 1 / 20 of the size of the switch transistor, the equivalent micro parasitic capacitance of the compensation module is 1 / 40 of the parasitic capacitance between the source and drain of the switch transistor itself.

6. The radio frequency switch circuit for achieving harmonic compensation according to claim 1, characterized in that: When the RF switch circuit is in the off state, the first NMOS tube and the second NMOS tube in the compensation module generate harmonic components alternately in the positive half cycle and the negative half cycle to compensate for the harmonic components generated by the switch transistor.

7. The radio frequency switch circuit for achieving harmonic compensation according to claim 1, characterized in that: The magnitude of the compensated harmonic component can be adjusted by adjusting the on or off working state of the diode branch in the compensation module in combination with adjusting the number of diodes and / or the magnitude of the compensation bias voltage.

8. The radio frequency switch circuit for implementing harmonic compensation according to claim 1, characterized in that: The compensation bias unit is composed of N compensation bias resistors connected in series in sequence, and the first ends of the N compensation bias resistors are respectively connected to the bias end of a corresponding compensation module in the harmonic compensation unit in sequence, and the second end of the Nth compensation bias resistor is connected to the compensation bias voltage end.

9. The radio frequency switch circuit for achieving harmonic compensation according to claim 1, characterized in that: The gate bias unit is composed of N gate bias resistors connected in series in sequence, and the first ends of the N gate bias resistors are respectively connected to the gate end of a corresponding switching transistor in the switch unit in sequence, and the second end of the Nth gate bias resistor is connected to the gate bias voltage end.

10. The radio frequency switch circuit for implementing harmonic compensation according to claim 1, characterized in that: The body-end bias unit is composed of N body-end bias resistors connected in series in sequence, and the first ends of the N body-end bias resistors are respectively connected to the body end of a corresponding switching transistor in the switch unit in sequence, and the second end of the Nth body-end bias resistor is connected to the body-end bias voltage terminal.

11. The radio frequency switch circuit for implementing harmonic compensation according to claim 1, characterized in that: The source-drain bias unit is composed of N source-drain bias resistors connected in series in sequence, and both ends of each source-drain bias resistor are respectively connected to the source and drain of a corresponding switch transistor in the switch unit.

12. An integrated circuit chip, characterized in that A radio frequency switch circuit for achieving harmonic compensation comprising any one of claims 1 to 11.

13. An electronic device, characterized in that A radio frequency switch circuit for achieving harmonic compensation comprising any one of claims 1 to 11.

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