A chip configuration upgrade method and system based on DP interface auxiliary channel

Abstract

The present invention discloses a chip configuration upgrade method and system based on a DP interface auxiliary channel. The method includes a main control chip writing register operation information into a DP interface configuration data register of a controlled chip through an auxiliary channel of the DP interface; after the controlled chip receives the register operation information, it determines whether the register operation information is a firmware upgrade instruction, and if so, it detects the current firmware version and program running area of ​​the controlled chip, selects a non-program running area as a receiving buffer, and the main control chip reads the upgrade data sending command packaged to the designated space of the buffer through the auxiliary channel, and then continuously packages and sends the upgrade data to the buffer; after receiving the receiving completion instruction, the controlled chip verifies the received upgrade data, and then completes the upgrade operation. For board-level hardware design, the present invention reduces the occupation of communication interfaces such as I2C and SPI of the main control chip, and for system-level hardware design, long-distance transmission across boards can be performed.

Description

Technical Field

[0001] The present invention relates to the technical field of chip configuration upgrade, and in particular to a chip configuration upgrade method and system based on a DP interface auxiliary channel. Background Art

[0002] Today, the integration of electronic design and chip design is getting higher and higher, and the demand for miniaturization is getting stronger and stronger, which has led to increasingly tight interface resources for highly integrated chips. The chips where DP Source and DP Sink are located are configured or upgraded separately through their respective devices or SOC chips on the single board or external MCU chips. Generally, the configuration or upgrade interface is a separate I2C or SPI configuration interface; the disadvantage of this solution is that the chip where DP Sink is located needs to be connected to the SOC chip or external MCU chip, which increases the cost of the single board. When the chip where DP Sink is located does not have a SOC chip or an external MCU chip, it is impossible to configure and upgrade the chip separately. It is necessary to remotely configure or upgrade through the device where the chip where DP Source is located or the SOC chip on the single board or the external MCU chip. Specifically, it is necessary to remotely configure or upgrade through an independent I2C or SPI configuration interface. The disadvantage of this solution is that the I2C or SPI configuration interface cannot achieve long-distance configuration or upgrade. In addition, the use of the I2C or SPI configuration interface occupies the few available interfaces of the master control, which brings difficult-to-solve resource allocation restrictions to the overall design. Summary of the invention

[0003] The purpose of the present invention is to provide a chip configuration upgrade method and system based on a DP interface auxiliary channel in view of the deficiencies in the prior art.

[0004] To achieve the above object, in a first aspect, the present invention provides a chip configuration upgrade method based on a DP interface auxiliary channel, which is applied to upgrade a controlled chip connected to a main control chip through a DP interface, comprising:

[0005] The master control chip writes the register operation information into the DP interface configuration data register of the controlled chip through the auxiliary channel of the DP interface;

[0006] After receiving the register operation information, the controlled chip uses its internal processor to parse the register operation information and determine whether the register operation information is a firmware upgrade instruction. If the register operation information is a firmware upgrade instruction, the processor detects the current firmware version and program running area of ​​the controlled chip, and then selects the non-program running area as the receiving buffer, and performs an erase operation on the receiving buffer. After the erasing is completed, the controlled chip packs the upgrade data sending command to the specified space of the DP interface configuration data register, and then sends an interrupt request signal to the main control chip through the hot plug detection signal channel of the DP interface;

[0007] After receiving the interrupt request signal, the main control chip reads the upgrade data sending command packaged to the designated space of the buffer through the auxiliary channel, and then continuously packages and sends the upgrade data to the buffer until the sending is completed and writes the sending completion instruction;

[0008] After receiving the receiving completion instruction, the controlled chip verifies the received upgrade data. After the verification passes, the processor inside the controlled chip is controlled to restart, and the program running area is selected as the cache area of ​​the upgrade data.

[0009] Furthermore, if the processor inside the controlled chip determines that the register operation information is a register operation instruction, it performs read and write operations on the DP interface configuration data register according to the information of the custom space in the DP interface configuration data. If the relevant register information needs to be replied, the controlled chip will pack the relevant information into the designated space of the DP interface configuration data register after the register operation is completed, and then send an interrupt request signal to the main control chip through the hot plug detection signal channel. After the main control chip receives the interrupt request signal, it performs a read operation on the controlled chip through the auxiliary channel. After receiving the read command, the controlled chip starts to send data corresponding to the read command.

[0010] Furthermore, the main control chip sends data to the controlled chip based on the Native AUX protocol.

[0011] Further, whether it is a firmware upgrade instruction is determined based on the address information of the register operation information.

[0012] Furthermore, the controlled chip verifies the received upgrade data based on a CRC verification algorithm.

[0013] In a second aspect, the present invention provides a chip configuration upgrade system based on a DP interface auxiliary channel, comprising a main control chip and a controlled chip connected to the main control chip via a DP interface;

[0014] The master control chip is used to write register operation information into the DP interface configuration data register of the controlled chip through the auxiliary channel of the DP interface;

[0015] After receiving the register operation information, the controlled chip uses its internal processor to parse the register operation information and determine whether the register operation information is a firmware upgrade instruction. If the register operation information is a firmware upgrade instruction, the processor detects the current firmware version and program running area of ​​the controlled chip, and then selects the non-program running area as the receiving buffer, and performs an erase operation on the receiving buffer. After the erasing is completed, the controlled chip packs the upgrade data sending command to the specified space of the DP interface configuration data register, and then sends an interrupt request signal to the main control chip through the hot plug detection signal channel of the DP interface;

[0016] After receiving the interrupt request signal, the main control chip reads the upgrade data sending command packaged to the designated space of the buffer through the auxiliary channel, and then continuously packages and sends the upgrade data to the buffer until the sending is completed and writes the sending completion instruction;

[0017] After receiving the receiving completion instruction, the controlled chip verifies the received upgrade data. After the verification passes, the processor inside the controlled chip is controlled to restart, and the program running area is selected as the cache area of ​​the upgrade data.

[0018] Furthermore, if the processor inside the controlled chip determines that the register operation information is a register operation instruction, a read and write operation is performed on the DP interface configuration data register according to the information of the custom space in the DP interface configuration data.

[0019] Furthermore, the main control chip sends data to the controlled chip based on the Native AUX protocol.

[0020] Further, whether it is a firmware upgrade instruction is determined based on the address information of the register operation information.

[0021] Furthermore, the controlled chip verifies the received upgrade data based on a CRC verification algorithm.

[0022] Beneficial effect: The present invention borrows reserved or unused DPCD addresses and customizes them as configuration or upgrade fields, thereby determining whether they are firmware upgrade instructions or register operation instructions through the address information of the register operation information, and realizing chip configuration and system upgrade based on the DP interface auxiliary channel. For board-level hardware design, it reduces the occupation of communication interfaces such as I2C and SPI of the main control chip. For system-level hardware design, it overcomes the short-distance transmission disadvantages of interfaces such as I2C and SPI, and can use the characteristics of the auxiliary channel of the DP interface for long-distance transmission across boards. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural diagram of a chip configuration upgrade system based on a DP interface auxiliary channel according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The embodiments are implemented based on the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0025] The embodiment of the present invention provides a chip configuration upgrade method based on a DP interface auxiliary channel, which is applied to upgrade a controlled chip (DP Sink end) connected to a main control chip (DP Source end) through a DP interface, and includes:

[0026] The master chip writes the register operation information into the DP interface configuration data (DPCP) register of the controlled chip through the auxiliary channel (DP_AUX) of the DP interface.

[0027] After receiving the register operation information sent by the master chip, the controlled chip uses its internal processor to parse the register operation information and determine whether the register operation information is a firmware upgrade instruction. If the register operation information is a firmware upgrade instruction, the processor inside the controlled chip detects the current firmware version and program running area of ​​the controlled chip, and then selects the non-program running area as the receiving buffer, and performs an erase operation on the receiving buffer. After the erasure is completed, the controlled chip packages the upgrade data sending command to the specified space of the DP interface configuration data register, and then sends an interrupt request signal (IRQ) to the master chip through the hot plug detection signal channel (HPD) of the DP interface. Specifically, the data for remote configuration or remote upgrade can be distinguished by address allocation. For example: i) Customize 64 bytes from the reserved or unused DPCD address for remote configuration of the chip, and this segment address is called the remote configuration field; ii) Customize 128 bytes from the reserved or unused DPCD address for remote upgrade of the chip, and this segment address is called the remote upgrade field. When the controlled chip receives the register operation information sent by the master chip, it determines whether the address is in the remote configuration field or the remote upgrade field by judging the address information of the register operation information, and then determines whether the register operation information is a register operation instruction or a firmware upgrade instruction. If the address is not in the remote configuration field or the remote upgrade field, it continues to be processed according to the normal DP process.

[0028] After receiving the interrupt request signal through the hot-plug detection signal channel, the main control chip reads the upgrade data sending command packaged into the buffer through the auxiliary channel, and then continues to package and send the upgrade data to the above buffer until the sending is completed and writes the sending completion instruction. During the packaging period, it is preferred to write to the remote upgrade field incrementally according to the address, and write every 128 bytes as a unit. If it exceeds 1 byte and is less than 128 bytes, it is written as 128 bytes of data. In addition, in addition to triggering the reading of the upgrade data sending command packaged into the buffer by feeding back the interrupt request signal to the main control chip, the controlled chip can also read it by the active polling method of the main control chip.

[0029] After receiving the receiving completion instruction, the controlled chip verifies the received upgrade data. After the verification is passed, the processor inside the controlled chip is controlled to restart, and the program running area is selected as the cache area of ​​the upgrade data. Specifically, after all the upgrade data are transmitted, the main control chip configures the special register located in the remote configuration field - the remote upgrade data CRC check enable register. At this time, the controlled chip starts to calculate the received upgrade data packet and checks it according to the CRC algorithm, and stores the check result in the special register located in the remote configuration field - the remote upgrade data CRC check result register. After the main control chip confirms that the remote upgrade data CRC check result is correct, it configures the special register located in the remote configuration field - the remote upgrade enable register. At this time, the controlled chip starts to use the received upgrade data packet for upgrading, and after the upgrade is completed, the upgrade result is stored in the special register located in the remote configuration field - the remote upgrade result register.

[0030] In addition, if it is determined that the register operation information is a register operation instruction, the processor inside the controlled chip will perform read and write operations on the DP interface configuration data register according to the information of the custom space in the DP interface configuration data.

[0031] The existing DP interface auxiliary channel has two transmission modes, namely Native AUX protocol and I2C over AUX protocol, as follows:

[0032] 1) Native AUX:

[0033] Definition: Native AUX is a native AUX channel transmission mode in the DisplayPort protocol, which is used to exchange configuration and status information on the main link.

[0034] Function: Native AUX is mainly responsible for some basic configurations, such as the transmission of information such as resolution, refresh rate, connection status, etc. It can also be used to implement some advanced functions, such as direct management of the DisplayPort link.

[0035] Bandwidth: The bandwidth of Native AUX is limited, so it may take a long time to process large amounts of data.

[0036] 2) I2C over AUX:

[0037] Definition: I2C over AUX is a way to transmit auxiliary data by using the I2C protocol on the AUX channel.

[0038] Function: I2C over AUX is usually used to transmit the display's EDID (Extended Display Identification Data) information, which is data about the display's supported resolutions, refresh rates, and other detailed information. With I2C over AUX, this information can be transmitted when the connection is established.

[0039] Bandwidth: I2C over AUX has a slower data transfer rate than Native AUX because I2C is a serial communication protocol, while Native AUX can transmit large amounts of configuration information more efficiently.

[0040] In general, the main difference between the two lies in the communication protocol used and the type of data transmitted. Native AUX is part of the DisplayPort protocol and is used for basic configuration and status information transmission, while I2C over AUX is an auxiliary channel transmission method based on the I2C protocol, which is mainly used to transmit detailed information of the display. They play a role in different scenarios and jointly build the comprehensive functions of the DisplayPort protocol. The master control chip of the embodiment of the present invention preferably sends data to the controlled chip based on the Native AUX protocol, and the data transmission efficiency is higher.

[0041] See also Figure 1 Based on the above embodiments, those skilled in the art can easily understand that the present invention provides a chip configuration upgrade system based on the DP interface auxiliary channel, including a main control chip 1 and a controlled chip 2 connected to the main control chip 1 through the DP interface.

[0042] The master chip 1 is used to write register operation information into the DP interface configuration data (DPCP) register of the controlled chip 2 through the auxiliary channel (DP_AUX) of the DP interface.

[0043] After receiving the register operation information sent by the main control chip 1, the controlled chip 2 uses its internal processor to parse the register operation information and determine whether the register operation information is a firmware upgrade instruction. If the register operation information is a firmware upgrade instruction, the processor inside the controlled chip 2 detects the current firmware version and program running area of ​​the controlled chip 2, and then selects the non-program running area as the receiving buffer, and performs an erase operation on the receiving buffer. After the erasure is completed, the controlled chip 2 packs the upgrade data sending command to the specified space of the DP interface configuration data register, and then sends an interrupt request signal (IRQ) to the main control chip 1 through the hot plug detection signal channel (HPD) of the DP interface. Specifically, the data for remote configuration or remote upgrade can be distinguished by address allocation. For example: i) Customize 64 bytes from the reserved or unused DPCD address for remote configuration of the chip, and this segment address is called the remote configuration field; ii) Customize 128 bytes from the reserved or unused DPCD address for remote upgrade of the chip, and this segment address is called the remote upgrade field. When the controlled chip 2 receives the register operation information sent by the master chip 1, it determines whether the address is in the remote configuration field or the remote upgrade field by judging the address information of the register operation information, and then determines whether the register operation information is a register operation instruction or a firmware upgrade instruction. If the address is not in the remote configuration field or the remote upgrade field, it continues to be processed according to the normal DP process.

[0044] After receiving the interrupt request signal through the hot-plug detection signal channel, the main control chip 1 reads the upgrade data sending command packaged into the buffer through the auxiliary channel, and then continues to package and send the upgrade data to the above buffer until the sending is completed and writes the sending completion instruction. During the packaging period, it is preferred to write to the remote upgrade field incrementally according to the address, and write every 128 bytes as a unit. If it exceeds 1 byte and is less than 128 bytes, it is written as 128 bytes of data. In addition, in addition to triggering the reading of the upgrade data sending command packaged into the buffer by feeding back the interrupt request signal to the main control chip 1, the controlled chip 2 can also be read by the main control chip 1 in an active polling manner.

[0045] After receiving the receiving completion instruction, the controlled chip 2 verifies the received upgrade data. After the verification is passed, the processor inside the controlled chip 2 is controlled to restart, and the program running area is selected as the cache area of ​​the upgrade data. Specifically, after all the upgrade data are transmitted, the main control chip 1 configures the dedicated register located in the remote configuration field - the remote upgrade data CRC check enable register. At this time, the controlled chip 2 starts to calculate the received upgrade data packet and verifies it according to the CRC algorithm, and stores the verification result in the dedicated register located in the remote configuration field - the remote upgrade data CRC check result register. After the main control chip 1 confirms that the remote upgrade data CRC check result is correct, it configures the dedicated register located in the remote configuration field - the remote upgrade enable register. At this time, the controlled chip 2 starts to use the received upgrade data packet for upgrading, and after the upgrade is completed, the upgrade result is stored in the dedicated register located in the remote configuration field - the remote upgrade result register.

[0046] In addition, if it is determined that the register operation information is a register operation instruction, the processor inside the controlled chip 2 will perform read and write operations on the DP interface configuration data register according to the information of the custom space in the DP interface configuration data.

[0047] The existing DP interface auxiliary channel has two transmission modes, namely Native AUX protocol and I2C over AUX protocol, as follows:

[0048] 1) Native AUX:

[0049] Definition: Native AUX is a native AUX channel transmission mode in the DisplayPort protocol, which is used to exchange configuration and status information on the main link.

[0050] Function: Native AUX is mainly responsible for some basic configurations, such as the transmission of information such as resolution, refresh rate, connection status, etc. It can also be used to implement some advanced functions, such as direct management of the DisplayPort link.

[0051] Bandwidth: The bandwidth of Native AUX is limited, so it may take a long time to process large amounts of data.

[0052] 2) I2C over AUX:

[0053] Definition: I2C over AUX is a way to transmit auxiliary data by using the I2C protocol on the AUX channel.

[0054] Function: I2C over AUX is usually used to transmit the display's EDID (Extended Display Identification Data) information, which is data about the display's supported resolutions, refresh rates, and other detailed information. With I2C over AUX, this information can be transmitted when the connection is established.

[0055] Bandwidth: I2C over AUX has a slower data transfer rate than Native AUX because I2C is a serial communication protocol, while Native AUX can transmit large amounts of configuration information more efficiently.

[0056] In general, the main difference between the two lies in the communication protocol used and the type of data transmitted. Native AUX is part of the DisplayPort protocol and is used for basic configuration and status information transmission, while I2C over AUX is an auxiliary channel transmission method based on the I2C protocol, which is mainly used to transmit detailed information of the display. They play a role in different scenarios and jointly build the comprehensive functions of the DisplayPort protocol. The master control chip 1 of the embodiment of the present invention preferably sends data to the controlled chip 2 based on the Native AUX protocol, and the data transmission efficiency is higher.

[0057] The above is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, other parts not specifically described belong to the prior art or common knowledge. Several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A chip configuration upgrade method based on the DP interface auxiliary channel is applied to upgrade a controlled chip connected to a main control chip via a DP interface, characterized in that: include: The master control chip writes the register operation information into the DP interface configuration data register of the controlled chip through the auxiliary channel of the DP interface; After receiving the register operation information, the controlled chip uses its internal processor to parse the register operation information and determine whether the register operation information is a firmware upgrade instruction. If the register operation information is a firmware upgrade instruction, the processor detects the current firmware version and program running area of ​​the controlled chip, and then selects the non-program running area as the receiving buffer, and performs an erase operation on the receiving buffer. After the erasing is completed, the controlled chip packs the upgrade data sending command to the specified space of the DP interface configuration data register, and then sends an interrupt request signal to the main control chip through the hot plug detection signal channel of the DP interface; After receiving the interrupt request signal, the main control chip reads the upgrade data sending command packaged to the designated space of the buffer through the auxiliary channel, and then continuously packages and sends the upgrade data to the buffer until the sending is completed and writes the sending completion instruction; After receiving the receiving completion instruction, the controlled chip verifies the received upgrade data. After the verification passes, the processor inside the controlled chip is controlled to restart, and the program running area is selected as the cache area of ​​the upgrade data.

2. A chip configuration upgrade method based on the DP interface auxiliary channel according to claim 1, characterized in that: If the processor inside the controlled chip determines that the register operation information is a register operation instruction, a read and write operation is performed on the DP interface configuration data register according to the information of the custom space in the DP interface configuration data.

3. A chip configuration upgrade method based on DP interface auxiliary channel according to claim 1, characterized in that: The master control chip sends data to the controlled chip based on the Native AUX protocol.

4. The chip configuration upgrade method based on the DP interface auxiliary channel according to claim 1, characterized in that: Whether it is a firmware upgrade instruction is determined based on the address information of the register operation information.

5. The chip configuration upgrade method based on the DP interface auxiliary channel according to claim 1, characterized in that: The controlled chip verifies the received upgrade data based on a CRC verification algorithm.

6. A chip configuration upgrade system based on a DP interface auxiliary channel, comprising a main control chip and a controlled chip connected to the main control chip via a DP interface, characterized in that: The master control chip is used to write register operation information into the DP interface configuration data register of the controlled chip through the auxiliary channel of the DP interface; After receiving the register operation information, the controlled chip uses its internal processor to parse the register operation information and determine whether the register operation information is a firmware upgrade instruction. If the register operation information is a firmware upgrade instruction, the processor detects the current firmware version and program running area of ​​the controlled chip, and then selects the non-program running area as the receiving buffer, and performs an erase operation on the receiving buffer. After the erasing is completed, the controlled chip packs the upgrade data sending command to the specified space of the DP interface configuration data register, and then sends an interrupt request signal to the main control chip through the hot plug detection signal channel of the DP interface; After receiving the interrupt request signal, the main control chip reads the upgrade data sending command packaged to the designated space of the buffer through the auxiliary channel, and then continuously packages and sends the upgrade data to the buffer until the sending is completed and writes the sending completion instruction; After receiving the receiving completion instruction, the controlled chip verifies the received upgrade data. After the verification passes, the processor inside the controlled chip is controlled to restart, and the program running area is selected as the cache area of ​​the upgrade data.

7. A chip configuration upgrade system based on DP interface auxiliary channel according to claim 6, characterized in that: If the processor inside the controlled chip determines that the register operation information is a register operation instruction, a read and write operation is performed on the DP interface configuration data register according to the information of the custom space in the DP interface configuration data.

8. The chip configuration upgrade system based on the DP interface auxiliary channel according to claim 6, characterized in that: The master control chip sends data to the controlled chip based on the Native AUX protocol.

9. The chip configuration upgrade system based on the DP interface auxiliary channel according to claim 6, characterized in that: Whether it is a firmware upgrade instruction is determined based on the address information of the register operation information.

10. The chip configuration upgrade system based on the DP interface auxiliary channel according to claim 6, characterized in that: The controlled chip verifies the received upgrade data based on a CRC verification algorithm.

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