A gallium nitride-based high electron mobility transistor and a method for preparing the same

Abstract

The invention discloses a gallium nitride-based high electron mobility transistor and a preparation method thereof, and relates to the field of semiconductor technology. The transistor includes a substrate, and a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer stacked on the substrate in sequence; wherein the first composite insertion layer and the second composite insertion layer each include at least two sublayers, and the two sublayers are an AlN sublayer and an AlInGaN sublayer, respectively; the barrier layer is an AlInN layer with an Al component and an In component ratio of 4:1-6:1, and the channel layer is a GaN layer. Through this arrangement, the lattice mismatch between the barrier layer and the channel layer is within 0.5%, and the lattice of the barrier layer and the channel layer is basically matched, thereby significantly improving the crystal quality of the barrier layer, and because the Al component and the In component ratio are within the range of 4:1-6:1, the band gap difference between the barrier layer and the channel layer is extremely large, thereby realizing the preparation of a relatively thin barrier layer, and at the same time, a higher two-dimensional electron gas concentration can be obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride-based high electron mobility transistor and a preparation method thereof. Background Art

[0002] A high electron mobility transistor (HEMT), also known as a heterostructure FET (HFET) or modulation doped field effect transistor (MODFET), is a field effect transistor that contains a junction between two materials with different band gaps (i.e. hetero) as the channel instead of a doped region (as is usually the case with MOSFETs).

[0003] Conventional gallium nitride-based high electron mobility transistors (HEMTs) use AlGaN as the barrier layer and GaN as the channel layer to form an AlGaN / GaN heterojunction. Due to the strong polarization effect of the heterojunction, a high-density two-dimensional electron gas can be formed on the GaN channel layer. The electron mobility of the two-dimensional electron gas is a key factor affecting device performance.

[0004] However, in order to achieve a high concentration of two-dimensional electron gas to ensure the high-power characteristics of the device, it is usually necessary to ensure that the AlGaN barrier layer has sufficient thickness. However, an overly thick AlGaN barrier layer will cause the device to have a short channel effect, and the high concentration of two-dimensional electron gas can easily enter the buffer layer in the transistor and be captured by traps in the buffer layer, thereby causing a current collapse effect and affecting the output characteristics of the device. Summary of the invention

[0005] Based on this, the purpose of the present invention is to provide a gallium nitride-based high electron mobility transistor and a preparation method thereof, so as to solve the technical problems in the background technology that the heterojunction in the existing gallium nitride-based high electron mobility transistor (HEMT) will have a short channel effect, and the two-dimensional electron gas formed by the heterojunction can easily enter the buffer layer in the transistor, thereby causing a current collapse effect and affecting the output characteristics of the device.

[0006] The present invention provides a gallium nitride-based high electron mobility transistor, comprising a substrate, and a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer stacked in sequence on the substrate;

[0007] Wherein, the first composite insertion layer and the second composite insertion layer each include at least two sublayers, and the two sublayers are an AlN sublayer and an AlInGaN sublayer respectively;

[0008] The barrier layer is an AlInN layer with a ratio of Al component to In component of 4:1-6:1, and the channel layer is a GaN layer.

[0009] Further, the first composite insertion layer includes a first AlN sublayer and a first AlInGaN sublayer sequentially stacked on the buffer layer;

[0010] The second composite insertion layer includes a second AlN sublayer and a second AlInGaN sublayer sequentially stacked on the channel layer.

[0011] Furthermore, the Al component in the first AlInGaN sublayer gradually decreases toward the channel layer, and the In component and the Ga component in the first AlInGaN sublayer gradually increase toward the channel layer.

[0012] Furthermore, the Al component in the second AlInGaN sublayer gradually increases toward the barrier layer, and the In component and the Ga component in the second AlInGaN sublayer gradually decrease toward the barrier layer.

[0013] Furthermore, the bandgap width of the first AlInGaN sublayer is smaller than the bandgap width of the second AlInGaN sublayer.

[0014] Furthermore, the first AlInGaN sublayer is carbon doped, and the carbon doping concentration is 4.0×10 12 atoms / cm 3 -1.0×10 20 atoms / cm 3 .

[0015] Further, the Al component in the first AlInGaN sublayer is 0.15-1, the In component in the first AlInGaN sublayer is 0-0.05, and the Ga component in the first AlInGaN sublayer is 0-0.8;

[0016] The Al component of the second AlInGaN sublayer is 0.6-1, the In component of the second AlInGaN sublayer is 0-0.1, and the Ga component of the second AlInGaN sublayer is 0-0.3.

[0017] Further, the thickness of the first AlN sublayer and the thickness of the second AlN sublayer are both 0.5nm-2nm, the thickness of the first AlInGaN sublayer and the thickness of the second AlInGaN sublayer are both 1nm-10nm, and the thickness of AlInN in the barrier layer is 10nm-100nm.

[0018] Another aspect of the present invention is to provide a method for preparing a gallium nitride-based high electron mobility transistor, comprising: providing a substrate;

[0019] Depositing a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer in sequence on the substrate;

[0020] Wherein, in the step of depositing the first composite insertion layer, the first composite insertion layer is grown on the buffer layer at a first preset temperature, a first preset pressure and a first preset mixed gas;

[0021] In the step of depositing the second composite insertion layer, the second composite insertion layer is grown on the channel layer at a second preset temperature, a second preset pressure and a second preset mixed gas.

[0022] Further, the first preset temperature is 700° C.-1000° C., the first preset pressure is 100 torr-250 torr, and the first preset mixed gas includes an Al source, an In source, a Ga source, and a N source;

[0023] The second preset temperature is 700° C.-1000° C., the second preset pressure is 100 torr-250 torr, and the second preset mixed gas includes an Al source, an In source, a Ga source, and a N source.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. In a gallium nitride-based high electron mobility transistor provided by the present invention, the barrier layer in the transistor is an InAlN layer, and the ratio of the Al component to the In component in the InAlN layer is controlled within the range of 4:1-6:1, so that the lattice mismatch between the barrier layer and the channel layer is within 0.5%, and the lattice of the barrier layer and the channel layer is basically matched, thereby significantly improving the crystal quality of the barrier layer and improving the reliability of the device. In addition, since the ratio of the Al component to the In component is within the range of 4:1-6:1, the band gap difference between the barrier layer and the channel layer is extremely large, thereby realizing the preparation of a relatively thin barrier layer, and at the same time, a higher two-dimensional electron gas concentration can be obtained. While ensuring the high-power characteristics of the device, the short channel effect can be effectively limited, solving the technical problems in the prior art that the heterojunction will have a short channel effect, and the two-dimensional electron gas formed by the heterojunction easily enters the buffer layer in the transistor, thereby causing a current collapse effect and affecting the output characteristics of the device.

[0026] 2. In combination with the first composite insertion layer and the second composite insertion layer in the transistor of the present invention, and the first composite insertion layer and the second composite insertion layer both include AlN sublayers, that is, AlN sublayers are introduced between the buffer layer and the channel layer, and between the channel layer and the barrier layer, to form a double heterostructure. Since AlN has the characteristic of a high bandgap width, the double AlN sublayer structure can reduce alloy scattering, improve the electron mobility of the two-dimensional electron gas, and avoid leakage of electrons from the channel layer to the buffer layer, thereby reducing leakage current and suppressing the current collapse effect. In addition, the introduction of the AlN sublayer can improve the problem that it is difficult for the barrier layer to grow a smooth contact surface on the channel layer, thereby improving device characteristics.

[0027] 3. The AlInGaN sublayer between the buffer layer and the channel layer, and between the channel layer and the barrier layer, can effectively reduce the lattice mismatch between the channel layer and the AlN sublayer, improve the crystal quality of the device, and enhance the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of a gallium nitride-based high electron mobility transistor in one embodiment of the present invention;

[0029] Figure 2 The present invention is a flow chart of a method for preparing a gallium nitride-based high electron mobility transistor according to an embodiment of the present invention.

[0030] In the figure: 1, substrate; 2, buffer layer; 3, first composite insertion layer; 31, first AlN sublayer; 32, first AlInGaN sublayer; 4, channel layer; 5, second composite insertion layer; 51, second AlN sublayer; 52, second AlInGaN sublayer; 6, barrier layer; 7, cap layer. DETAILED DESCRIPTION

[0031] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0032] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0034] The present invention provides a gallium nitride-based high electron mobility transistor, comprising a substrate 1, and a buffer layer 2, at least one first composite insertion layer 3, a channel layer 4, at least one second composite insertion layer 5, a barrier layer 6 and a cap layer 7 sequentially stacked on the substrate 1;

[0035] Wherein, the first composite insertion layer 3 and the second composite insertion layer 5 each include at least two sublayers, and the two sublayers are respectively an AlN sublayer and an AlInGaN sublayer;

[0036] The barrier layer 6 is an AlInN layer having an Al component and an In component ratio of 4:1-6:1, and the channel layer 4 is a GaN layer.

[0037] Further, the first composite insertion layer 3 includes a first AlN sublayer 31 and a first AlInGaN sublayer 32 sequentially stacked on the buffer layer 2;

[0038] The second composite insertion layer 5 includes a second AlN sublayer 51 and a second AlInGaN sublayer 52 which are sequentially stacked on the channel layer 4 .

[0039] Furthermore, the Al component in the first AlInGaN sublayer 32 gradually decreases toward the channel layer 4 , and the In component and the Ga component in the first AlInGaN sublayer 32 gradually increase toward the channel layer 4 .

[0040] Furthermore, the Al component in the second AlInGaN sublayer 52 gradually increases toward the barrier layer 6 , and the In component and the Ga component in the second AlInGaN sublayer 52 gradually decrease toward the barrier layer 6 .

[0041] Furthermore, the bandgap width of the first AlInGaN sublayer 32 is smaller than the bandgap width of the second AlInGaN sublayer 52 .

[0042] Furthermore, the first AlInGaN sublayer 32 is carbon doped, and the carbon doping concentration is 4.0×10 12 atoms / cm 3 -1.0×10 20 atoms / cm 3 .

[0043] Further, the Al component in the first AlInGaN sublayer 32 is 0.15-1, the In component in the first AlInGaN sublayer 32 is 0-0.05, and the Ga component in the first AlInGaN sublayer 32 is 0-0.8;

[0044] The Al composition of the second AlInGaN sublayer 52 is 0.6-1, the In composition of the second AlInGaN sublayer 52 is 0-0.1, and the Ga composition of the second AlInGaN sublayer 52 is 0-0.3.

[0045] Furthermore, the thickness of the first AlN sublayer 31 and the second AlN sublayer 51 are both 0.5nm-2nm, the thickness of the first AlInGaN sublayer 32 and the second AlInGaN sublayer 52 are both 1nm-10nm, and the thickness of AlInN in the barrier layer 6 is 10nm-100nm.

[0046] Another aspect of the present invention is to provide a method for preparing a gallium nitride-based high electron mobility transistor, comprising: providing a substrate 1;

[0047] A buffer layer 2, at least one first composite insertion layer 3, a channel layer 4, at least one second composite insertion layer 5, a barrier layer 6 and a cap layer 7 are sequentially deposited on a substrate 1;

[0048] Wherein, in the step of depositing the first composite insertion layer 3, the first composite insertion layer 3 is grown on the buffer layer 2 at a first preset temperature, a first preset pressure and a first preset mixed gas;

[0049] In the step of depositing the second composite insertion layer 5 , the second composite insertion layer 5 is grown on the channel layer 4 at a second preset temperature, a second preset pressure and a second preset mixed gas.

[0050] Further, the first preset temperature is 700° C.-1000° C., the first preset pressure is 100 torr-250 torr, and the first preset mixed gas includes an Al source, an In source, a Ga source, and a N source;

[0051] The second preset temperature is 700° C.-1000° C., the second preset pressure is 100 torr-250 torr, and the second preset mixed gas includes an Al source, an In source, a Ga source, and a N source.

[0052] First embodiment

[0053] See also Figure 1 In one aspect, the present invention provides a gallium nitride-based high electron mobility transistor, comprising a substrate 1, and a buffer layer 2, at least one first composite insertion layer 3, a channel layer 4, at least one second composite insertion layer 5, a barrier layer 6 and a cap layer 7 sequentially stacked on the substrate 1;

[0054] Wherein, the first composite insertion layer 3 and the second composite insertion layer 5 each include at least two sublayers, and the two sublayers are respectively an AlN sublayer and an AlInGaN sublayer;

[0055] The barrier layer 6 is an AlInN layer having an Al component and an In component ratio of 4:1-6:1, and the channel layer 4 is a GaN layer.

[0056] It should be noted that, in some preferred embodiments, the channel layer 4 includes InGaN / GaN, that is, the channel layer 4 can be InGaN or GaN. In this example, the channel layer 4 is a GaN layer.

[0057] That is, by making the barrier layer 6 in the transistor an InAlN layer, and controlling the ratio of the Al component to the In component in the InAlN layer within the range of 4:1-6:1, the lattice mismatch between the barrier layer 6 and the channel layer 4 is within 0.5%, and the lattice of the barrier layer 6 and the channel layer 4 is basically matched, thereby significantly improving the crystal quality of the barrier layer 6 and improving the reliability of the device. In addition, since the ratio of the Al component to the In component is within the range of 4:1-6:1, the band gap difference between the barrier layer 6 and the channel layer 4 is extremely large, thereby realizing the preparation of a relatively thin barrier layer 6, and at the same time, a higher two-dimensional electron gas concentration can be obtained. While ensuring the high-power characteristics of the device, the short channel effect can be effectively limited, thereby solving the technical problems in the prior art that the short channel effect will occur in the heterojunction, and the two-dimensional electron gas formed by the heterojunction can easily enter the buffer layer 2 in the transistor, thereby causing a current collapse effect and affecting the output characteristics of the device.

[0058] However, when the barrier layer 6 and the channel layer 4 are stacked, a heterojunction is formed. In the case of lattice mismatch and strong polarization effect, the heterojunction will produce serious lattice defects, affecting the reliability of the device. In addition, the present invention forms a higher two-dimensional electron gas concentration through the InAlN barrier layer 6. In some actual situations, the high-concentration two-dimensional electron gas is easy to enter the buffer layer 2 and be captured by the traps in the buffer layer 2, causing a current collapse effect, affecting the output characteristics of the device. It should be noted that the AlGaN / GaN heterostructure in the prior art will also produce serious lattice defects in the case of lattice mismatch and strong polarization effect, and the high-concentration two-dimensional electron gas generated by the two will also be captured by the traps in the buffer layer 2, causing a current collapse effect, affecting the output characteristics of the device.

[0059] To this end, in an embodiment of the present invention, the transistor includes a first composite insertion layer 3 and a second composite insertion layer 5. Specifically, in some preferred embodiments, the first composite insertion layer 3 includes a first AlN sublayer 31 and a first AlInGaN sublayer 32 sequentially stacked on the buffer layer 2;

[0060] The second composite insertion layer 5 includes a second AlN sublayer 51 and a second AlInGaN sublayer 52 which are sequentially stacked on the channel layer 4 .

[0061] That is to say, in some practical situations, by introducing a first AlN sublayer 31 between the buffer layer 2 and the channel layer 4, and introducing a second AlN sublayer 51 between the channel layer 4 and the barrier layer 6, since AlN has the characteristic of a high bandgap width, the double AlN sublayer structure can reduce alloy scattering, improve the electron mobility of the two-dimensional electron gas, while avoiding the leakage of electrons from the channel layer 4 to the buffer layer 2, thereby reducing leakage current and suppressing the current collapse effect. In addition, the introduction of the AlN sublayer can improve the problem that it is difficult for the barrier layer 6 to grow a smooth contact surface on the channel layer 4, thereby improving the device characteristics.

[0062] In addition, the AlInGaN sublayer between the buffer layer 2 and the channel layer 4 and between the channel layer 4 and the barrier layer 6 can effectively reduce the lattice mismatch between the channel layer 4 and the AlN sublayer, improve the crystal quality of the device, and enhance the performance of the device.

[0063] Specifically, the Al component in the first AlInGaN sublayer 32 gradually decreases toward the channel layer 4, the In component and the Ga component in the first AlInGaN sublayer 32 gradually increase toward the channel layer 4, and the Al component in the second AlInGaN sublayer 52 gradually increases toward the barrier layer 6, and the In component and the Ga component in the second AlInGaN sublayer 52 gradually decrease toward the barrier layer 6. By gradually changing the Al, In, and Ga components in the first AlInGaN sublayer 32 and the second AlInGaN sublayer 52, the lattice mismatch between the channel layer 4 and the second AlN sublayer 51 can be effectively reduced, thereby improving the crystal quality of the device and enhancing the performance of the device.

[0064] Furthermore, carbon is doped into the first AlInGaN sublayer 32, and the carbon doping concentration is 4.0×10 12 atoms / cm 3 -1.0×10 20 atoms / cm 3 By doping carbon elements in the first AlInGaN sublayer 32 between the buffer layer 2 and the channel layer 4, the doping of carbon elements can introduce certain deep energy level traps to capture electrons leaking from the channel layer 4 to the buffer layer 2, thereby reducing leakage current.

[0065] In some preferred embodiments, the bandgap of the first AlInGaN sublayer 32 is smaller than the bandgap of the second AlInGaN sublayer 52 , so that the second AlInGaN sublayer 52 has a higher bandgap, which can increase the two-dimensional electron concentration of the channel layer 4 .

[0066] It should be noted that, in this embodiment, the Al component in the first AlInGaN sublayer 32 is 0.15-1, the In component in the first AlInGaN sublayer 32 is 0-0.05, and the Ga component in the first AlInGaN sublayer 32 is 0-0.8; the Al component in the second AlInGaN sublayer 52 is 0.6-1, the In component in the second AlInGaN sublayer 52 is 0-0.1, and the Ga component in the second AlInGaN sublayer 52 is 0-0.3.

[0067] In addition, the thickness of the first AlN sublayer 31 and the second AlN sublayer 51 are both 0.5nm-2nm, the thickness of the first AlInGaN sublayer 32 and the second AlInGaN sublayer 52 are both 1nm-10nm, and the thickness of AlInN in the barrier layer 6 is 10nm-100nm.

[0068] Specifically, in this embodiment, the thickness of the first AlN sublayer 31 is 1.5 nm, the thickness of the first AlInGaN sublayer 32 is 6 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 1.0×10 19 atoms / cm 3 , the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0069] The thickness of the second AlN sublayer 51 is 1 nm, the thickness of the second AlInGaN sublayer 52 is 4 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0070] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0071] In summary, the gallium nitride-based high electron mobility transistor provided by the present invention has at least the following beneficial effects compared with traditional transistors:

[0072] 1. In a gallium nitride-based high electron mobility transistor provided by the present invention, the barrier layer 6 in the transistor is an InAlN layer, and the ratio of the Al component to the In component in the InAlN layer is controlled within the range of 4:1-6:1, so that the lattice mismatch between the barrier layer 6 and the channel layer 4 is within 0.5%, and the lattice of the barrier layer 6 and the channel layer 4 is basically matched, thereby significantly improving the crystal quality of the barrier layer 6 and improving the reliability of the device. In addition, since the ratio of the Al component to the In component is within the range of 4:1-6:1, the band gap difference between the barrier layer 6 and the channel layer 4 is extremely large, thereby realizing the preparation of a relatively thin barrier layer 6, and at the same time, a higher two-dimensional electron gas concentration can be obtained. While ensuring the high-power characteristics of the device, the short channel effect can be effectively limited, thereby solving the technical problems that the short channel effect will occur in the heterojunction in the prior art, and the two-dimensional electron gas formed by the heterojunction easily enters the buffer layer 2 in the transistor, thereby causing a current collapse effect and affecting the output characteristics of the device.

[0073] 2. In combination with the first composite insertion layer 3 and the second composite insertion layer 5 in the transistor of the present invention, and the first composite insertion layer 3 and the second composite insertion layer 5 both include AlN sublayers, that is, AlN sublayers are introduced between the buffer layer 2 and the channel layer 4, and between the channel layer 4 and the barrier layer 6, to form a double heterostructure. Since AlN has the characteristic of a high bandgap width, the double AlN sublayer structure can reduce alloy scattering, improve the electron mobility of the two-dimensional electron gas, and prevent the leakage of electrons from the channel layer 4 to the buffer layer 2, thereby reducing leakage current and suppressing the current collapse effect. In addition, the introduction of the AlN sublayer can improve the problem that it is difficult for the barrier layer 6 to grow a smooth contact surface on the channel layer 4, thereby improving the device characteristics.

[0074] 3. The AlInGaN sublayer between the buffer layer 2 and the channel layer 4, and between the channel layer 4 and the barrier layer 6, can effectively reduce the lattice mismatch between the channel layer 4 and the AlN sublayer, improve the crystal quality of the device, and enhance the performance of the device.

[0075] Second embodiment

[0076] A gallium nitride-based high electron mobility transistor is provided in a second embodiment of the present invention. The gallium nitride-based high electron mobility transistor in this embodiment is different from the gallium nitride-based high electron mobility transistor in the first embodiment in that:

[0077] In this embodiment, the thickness of the first AlN sublayer 31 is 1.5 nm, the thickness of the first AlInGaN sublayer 32 is 6 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 4.0×10 12 atoms / cm 3, the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0078] The thickness of the second AlN sublayer 51 is 1 nm, the thickness of the second AlInGaN sublayer 52 is 4 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0079] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0080] Third embodiment

[0081] A gallium nitride-based high electron mobility transistor is provided in a third embodiment of the present invention. The gallium nitride-based high electron mobility transistor in this embodiment is different from the gallium nitride-based high electron mobility transistor in the first embodiment in that:

[0082] In this embodiment, the thickness of the first AlN sublayer 31 is 1.5 nm, the thickness of the first AlInGaN sublayer 32 is 6 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 5.5×10 12 atoms / cm 3 , the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0083] The thickness of the second AlN sublayer 51 is 1 nm, the thickness of the second AlInGaN sublayer 52 is 4 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0084] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0085] Fourth embodiment

[0086] A gallium nitride-based high electron mobility transistor is provided in a fourth embodiment of the present invention. The gallium nitride-based high electron mobility transistor in this embodiment is different from the gallium nitride-based high electron mobility transistor in the first embodiment in that:

[0087] In this embodiment, the thickness of the first AlN sublayer 31 is 1.5 nm, the thickness of the first AlInGaN sublayer 32 is 6 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 7.0×10 12 atoms / cm 3 , the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0088] The thickness of the second AlN sublayer 51 is 1 nm, the thickness of the second AlInGaN sublayer 52 is 4 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0089] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0090] Fifth embodiment

[0091] A fifth embodiment of the present invention provides a gallium nitride-based high electron mobility transistor. The gallium nitride-based high electron mobility transistor in this embodiment is different from the gallium nitride-based high electron mobility transistor in the first embodiment in that:

[0092] In this embodiment, the thickness of the first AlN sublayer 31 is 1.5 nm, the thickness of the first AlInGaN sublayer 32 is 6 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 1.0×10 20 atoms / cm 3 , the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0093] The thickness of the second AlN sublayer 51 is 1 nm, the thickness of the second AlInGaN sublayer 52 is 4 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0094] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0095] Sixth embodiment

[0096] A gallium nitride-based high electron mobility transistor is provided in a sixth embodiment of the present invention. The gallium nitride-based high electron mobility transistor in this embodiment is different from the gallium nitride-based high electron mobility transistor in the first embodiment in that:

[0097] In this embodiment, the thickness of the first AlN sublayer 31 is 0.5 nm, the thickness of the first AlInGaN sublayer 32 is 6 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 5.5×10 12 atoms / cm 3 , the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0098] The thickness of the second AlN sublayer 51 is 0.5 nm, the thickness of the second AlInGaN sublayer 52 is 4 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0099] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0100] Seventh embodiment

[0101] A seventh embodiment of the present invention provides a gallium nitride-based high electron mobility transistor. The gallium nitride-based high electron mobility transistor in this embodiment is different from the gallium nitride-based high electron mobility transistor in the first embodiment in that:

[0102] In this embodiment, the thickness of the first AlN sublayer 31 is 2 nm, the thickness of the first AlInGaN sublayer 32 is 6 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 5.5×10 12 atoms / cm 3 , the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0103] The thickness of the second AlN sublayer 51 is 2 nm, the thickness of the second AlInGaN sublayer 52 is 4 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0104] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0105] Eighth embodiment

[0106] In an eighth embodiment of the present invention, a gallium nitride-based high electron mobility transistor is provided. The gallium nitride-based high electron mobility transistor in this embodiment is different from the gallium nitride-based high electron mobility transistor in the first embodiment in that:

[0107] In this embodiment, the thickness of the first AlN sublayer 31 is 1.5 nm, the thickness of the first AlInGaN sublayer 32 is 1 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 5.5×10 12 atoms / cm 3 , the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0108] The thickness of the second AlN sublayer 51 is 1 nm, the thickness of the second AlInGaN sublayer 52 is 1 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0109] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0110] Ninth embodiment

[0111] A gallium nitride-based high electron mobility transistor is provided in a ninth embodiment of the present invention. The gallium nitride-based high electron mobility transistor in this embodiment is different from the gallium nitride-based high electron mobility transistor in the first embodiment in that:

[0112] In this embodiment, the thickness of the first AlN sublayer 31 is 1.5 nm, the thickness of the first AlInGaN sublayer 32 is 10 nm, and the concentration of carbon doped into the first AlInGaN sublayer 32 is 5.5×10 12 atoms / cm3 , the Al component in the first AlInGaN sublayer 32 decreases from 1 to 0.15, the In component in the first AlInGaN sublayer 32 increases from 0 to 0.05, and the Ga component in the first AlInGaN sublayer 32 increases from 0 to 0.8;

[0113] The thickness of the second AlN sublayer 51 is 1 nm, the thickness of the second AlInGaN sublayer 52 is 10 nm, and the Al component in the second AlInGaN sublayer 52 increases from 0.6 to 1, the In component in the second AlInGaN sublayer 52 decreases from 0.1 to 0, and the Ga component in the second AlInGaN sublayer 52 decreases from 0.3 to 0;

[0114] The AlInN barrier layer 6 has an Al composition of 0.83, an In composition of 0.17, and a thickness of 20 nm.

[0115] The first comparison

[0116] The present invention provides a first comparative example, in which the substrate in the first embodiment is included, and a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer are sequentially stacked on the substrate;

[0117] In this comparative example, the first composite insertion layer does not include an AlN sublayer, and the rest is the same as that of the first embodiment.

[0118] The second comparison

[0119] The present invention provides a second comparative example, in which the substrate in the first embodiment is included, and a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer are sequentially stacked on the substrate;

[0120] In this comparative example, the first composite insertion layer does not include an AlInGaN sublayer, and the rest is the same as the first embodiment.

[0121] The third comparison

[0122] The present invention provides a third comparative example, in which the third comparative example includes the substrate in the first embodiment, and a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer sequentially stacked on the substrate;

[0123] In this comparative example, the AlInGaN sublayer in the first composite insertion layer is not doped with carbon, and the rest is the same as the first embodiment.

[0124] The fourth comparison

[0125] The present invention provides a fourth comparative example, in which the fourth comparative example includes the substrate in the first embodiment, and a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer sequentially stacked on the substrate;

[0126] In this comparative example, the second composite insertion layer does not contain an AlN sublayer, and the rest is the same as that of the first embodiment.

[0127] Fifth comparison

[0128] The present invention provides a fifth comparative example, in which the fifth comparative example includes the substrate in the first embodiment, and a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer sequentially stacked on the substrate;

[0129] In this comparative example, the second composite insertion layer does not contain an AlInGaN sublayer, and the rest is the same as that of the first embodiment.

[0130] Sixth comparison

[0131] The present invention provides a sixth comparative example, in which the sixth comparative example includes the substrate in the first embodiment, and a buffer layer, a channel layer, a barrier layer and a cap layer sequentially stacked on the substrate;

[0132] In this comparative example, the first composite insertion layer and the second composite insertion layer are not included, and the rest is the same as the first embodiment.

[0133] In order to effectively verify the performance of the gallium nitride-based high electron mobility transistor in the embodiment of the present invention, the gallium nitride-based high electron mobility transistors prepared in the first embodiment to the ninth embodiment and the first comparative example to the sixth comparative example are respectively selected to perform the relevant performance tests shown in Table 1 and Table 2 below. The test results are shown in Table 1 and Table 2 below:

[0134] The following table 1 is a data comparison of the first embodiment to the ninth embodiment;

[0135]

[0136] Table 1

[0137] Table 2 below is a data comparison of the first to ninth embodiments and the first to sixth comparative examples;

[0138]

[0139] Table 2

[0140] In general, the experiments in Table 1 and Table 2 show that the GaN-based high electron mobility transistor in this embodiment can improve the electron mobility of the two-dimensional electron gas to the best compared with the traditional GaN-based high electron mobility transistor, and has a significant improvement compared with the first to sixth comparative examples.

[0141] Tenth embodiment

[0142] See also Figure 2 , shown is a method for preparing a gallium nitride-based high electron mobility transistor provided by the tenth embodiment of the present invention, which is used to prepare the gallium nitride-based high electron mobility transistor in the first embodiment, including providing a substrate;

[0143] Depositing a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer in sequence on a substrate;

[0144] Wherein, in the step of depositing the first composite insertion layer, the first composite insertion layer is grown on the buffer layer at a first preset temperature, a first preset pressure and a first preset mixed gas;

[0145] In the step of depositing the second composite insertion layer, the second composite insertion layer is grown on the channel layer at a second preset temperature, a second preset pressure and a second preset mixed gas.

[0146] Further, the first preset temperature is 700° C.-1000° C., the first preset pressure is 100 torr-250 torr, and the first preset mixed gas includes an Al source, an In source, a Ga source, and a N source;

[0147] The second preset temperature is 700° C.-1000° C., the second preset pressure is 100 torr-250 torr, and the second preset mixed gas includes an Al source, an In source, a Ga source, and a N source.

[0148] Specifically, the preparation method thereof may include S01-S07;

[0149] S01, providing a substrate;

[0150] It should be noted that the substrate includes but is not limited to a silicon substrate, a sapphire substrate, a silicon carbide substrate, and a GaN substrate. To facilitate understanding of this case, a silicon substrate is used as the epitaxial layer growth substrate in this example.

[0151] S02, depositing a buffer layer on the substrate;

[0152] It should be noted that the buffer layer includes but is not limited to any one of an AlN layer, an AlGaN layer, and a GaN layer or a combination thereof. As an example of the present invention, the buffer layer is an AlGaN buffer layer, and the specific deposition process thereof is as follows: the N (nitrogen) source may be NH3 The Ga (gallium) source can be TMGa, the Al (aluminum) source can be TMAl, and the specific deposition process is that the reaction chamber temperature can be 750℃-1050℃, the chamber pressure can be 80torr-180torr, and the AlGaN buffer layer with a thickness of 1.8um-3um is grown. The specific thickness of the AlGaN buffer layer is 2um.

[0153] S03, depositing a first composite insertion layer on the buffer layer;

[0154] It should be noted that the first composite insertion layer includes a first AlN sublayer and a first AlInGaN sublayer deposited in sequence. The Al component of the first AlInGaN sublayer is 0.15-1, the In component is 0-0.05, the Ga component is 0-0.8, and the carbon doping concentration is 4.0×10 12 atoms / cm 3 -1.0×10 20 atoms / cm 3 , and the Al component in the first AlInGaN sublayer gradually decreases, and the In component and the Ga component gradually increase along the growth direction. As an example of the present invention, the Al component decreases from 1 to 0.15, the In component increases from 0 to 0.05, and the Ga component increases from 0 to 0.8.

[0155] The specific process of depositing the first composite insertion layer is: introducing Al (aluminum) source, In (indium) source, Ga (gallium) source, and N (nitrogen) source required for growth into the reaction chamber. As an example of the present invention, the Al source (aluminum) can be TMAl (trimethylaluminum), the In (indium) source can be TMIn (trimethylindium), the Ga (gallium) source can be TMGa (trimethylgallium), and the N (nitrogen) source can be NH 3 (ammonia), maintaining the reaction chamber temperature at 700℃-1000℃, the reaction chamber pressure at 100torr-250torr, and sequentially growing the first AlN sublayer with a thickness of 0.5nm-2nm, the carbon doping concentration of 1nm-10nm and the carbon doping concentration of 4.0×10 12 atoms / cm 3 -1.0×10 20 atoms / cm 3 The first AlInGaN sublayer has an Al composition decreased from 1 to 0.15, an In composition increased from 0 to 0.05, and a Ga composition increased from 0 to 0.8.

[0156] S04, depositing a channel layer on the first composite insertion layer;

[0157] It should be noted that the channel layer includes but is not limited to an InGaN channel layer and a GaN channel layer. To facilitate understanding of this case, the channel layer is now adopted as a GaN channel layer. The specific deposition process is to introduce an N (nitrogen) source and a Ga (gallium) source into the reaction chamber. The reaction chamber temperature can be 650°C-950°C, the reaction chamber pressure can be 50torr-200torr, and a GaN channel layer with a thickness of 50nm-300nm is grown. The specific thickness of the GaN channel layer can be 180nm.

[0158] S05, depositing a second composite insertion layer on the channel layer;

[0159] The second composite insertion layer includes a second AlN sublayer and a second AlInGaN sublayer deposited sequentially, the Al component of the second AlInGaN sublayer is 0.6-1, the In component is 0-0.1, and the Ga component is 0-0.3, and the Al component of the second AlInGaN sublayer gradually increases along the growth direction, and the In component and the Ga component gradually decrease. As an example of the present invention, the Al component increases from 0.6 to 1, the In component decreases from 0.1 to 0, and the Ga component decreases from 0.3 to 0.

[0160] The specific process of depositing the second composite insertion layer is: introducing the Al (aluminum) source, In (indium) source, Ga (gallium) source, and N (nitrogen) source required for growth into the reaction chamber. As an example of the present invention, the Al source (aluminum) can be TMAl (trimethylaluminum), the In (indium) source can be TMIn (trimethylindium), the Ga (gallium) source can be TEGa (triethylgallium), and the N (nitrogen) source can be NH3 (ammonia). The reaction chamber temperature is maintained at 700°C-1000°C, and the reaction chamber pressure is 100torr-250torr. A second AlInGaN sublayer with a thickness of 1nm-10nm and a second AlN sublayer with a thickness of 0.5nm-2nm are grown in sequence, wherein the Al component of the second AlInGaN sublayer increases from 0.6 to 1, the In component decreases from 0.1 to 0, and the Ga component decreases from 0.3 to 0.

[0161] S06, depositing a barrier layer on the second composite insertion layer;

[0162] It should be noted that the barrier layer is an AlInN barrier layer, and the ratio of Al to In components in the AlInN barrier layer is 4:1-6:1.

[0163] The specific process of depositing the barrier layer is: introducing Al (aluminum) source, In (indium) source, and N (nitrogen) source required for growth into the reaction chamber. As an example of the present invention, the Al source (aluminum) can be TMAl (trimethylaluminum), the In (indium) source can be TMIn (trimethylindium), and the N (nitrogen) source can be NH 3(ammonia), maintaining the reaction chamber temperature at 800°C-1000°C, the reaction chamber pressure at 80torr-200torr, and growing an AlInN barrier layer with a thickness of 10nm-100nm.

[0164] S07, depositing a cap layer on the barrier layer;

[0165] The cap layer is GaN cap layer, and the N (nitrogen) source can be NH 3 The Ga (gallium) source can be TEGa, the reaction chamber temperature can be 750°C-1100°C, the reaction chamber pressure can be 150torr-250torr, and a GaN cap layer with a thickness of 10nm-50nm is grown. The specific thickness of the GaN cap layer can be 30nm.

[0166] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0167] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the attached claims.

Claims

1. A gallium nitride-based high electron mobility transistor, characterized in that: It includes a substrate, and a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer stacked in sequence on the substrate; Wherein, the first composite insertion layer and the second composite insertion layer each include at least two sublayers, and the two sublayers are an AlN sublayer and an AlInGaN sublayer respectively; The barrier layer is an AlInN layer having an Al component to In component ratio of 4:1-6:1, and the channel layer is a GaN layer; The first composite insertion layer includes a first AlN sublayer and a first AlInGaN sublayer sequentially stacked on the buffer layer; The second composite insertion layer includes a second AlN sublayer and a second AlInGaN sublayer sequentially stacked on the channel layer; The bandgap width of the first AlInGaN sublayer is smaller than the bandgap width of the second AlInGaN sublayer.

2. The gallium nitride-based high electron mobility transistor according to claim 1, characterized in that: The Al component in the first AlInGaN sublayer gradually decreases toward the channel layer, and the In component and the Ga component in the first AlInGaN sublayer gradually increase toward the channel layer.

3. The gallium nitride-based high electron mobility transistor according to claim 1, characterized in that: The Al component in the second AlInGaN sublayer gradually increases toward the barrier layer, and the In component and the Ga component in the second AlInGaN sublayer gradually decrease toward the barrier layer.

4. The gallium nitride-based high electron mobility transistor according to claim 1, characterized in that: The first AlInGaN sublayer is carbon doped with a carbon doping concentration of 4.0×10 12 atoms / cm 3 -1.0×10 20 atoms / cm 3 .

5. The gallium nitride-based high electron mobility transistor according to claim 1, characterized in that: The Al component in the first AlInGaN sublayer is 0.15-1, the In component in the first AlInGaN sublayer is 0-0.05, and the Ga component in the first AlInGaN sublayer is 0-0.8; The Al component of the second AlInGaN sublayer is 0.6-1, the In component of the second AlInGaN sublayer is 0-0.1, and the Ga component of the second AlInGaN sublayer is 0-0.

3.

6. The gallium nitride-based high electron mobility transistor according to claim 1, characterized in that: The thickness of the first AlN sublayer and the thickness of the second AlN sublayer are both 0.5nm-2nm, the thickness of the first AlInGaN sublayer and the thickness of the second AlInGaN sublayer are both 1nm-10nm, and the thickness of AlInN in the barrier layer is 10nm-100nm.

7. A method for preparing a gallium nitride-based high electron mobility transistor, characterized in that: The preparation method is used to prepare the gallium nitride-based high electron mobility transistor according to any one of claims 1 to 6, and the preparation method comprises: providing a substrate; Depositing a buffer layer, at least one first composite insertion layer, a channel layer, at least one second composite insertion layer, a barrier layer and a cap layer in sequence on the substrate; Wherein, in the step of depositing the first composite insertion layer, the first composite insertion layer is grown on the buffer layer at a first preset temperature, a first preset pressure and a first preset mixed gas; In the step of depositing the second composite insertion layer, the second composite insertion layer is grown on the channel layer at a second preset temperature, a second preset pressure and a second preset mixed gas.

8. The method for preparing a gallium nitride-based high electron mobility transistor according to claim 7, characterized in that: The first preset temperature is 700° C.-1000° C., the first preset pressure is 100 torr-250 torr, and the first preset mixed gas includes an Al source, an In source, a Ga source, and a N source; The second preset temperature is 700° C.-1000° C., the second preset pressure is 100 torr-250 torr, and the second preset mixed gas includes an Al source, an In source, a Ga source, and a N source.

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