A super junction power device and a method for manufacturing the same

Abstract

The present application discloses a super junction power device, including a substrate layer, an epitaxial layer, a gate structure and a dielectric region located below the gate structure, a well region located on both sides of the gate structure and the dielectric region, a source region located in the well region, and a well contact region. A semiconductor layer having a second conductivity type is covered on part of the sidewalls of the dielectric region. The portion of the dielectric region that is not covered by the semiconductor layer is at least located below the gate structure between the source regions. The super junction power device provided by the present application has a significantly reduced cell size and good conduction performance of the device. At the same time, the manufacturing method provided by the present application is simple and easy to implement, which can significantly reduce process time and manufacturing costs.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a super junction power device and a method for manufacturing the same. Background Art

[0002] In a power device with a super junction structure, the drift layer generally includes an n-type column and a p-type column. The n-type column forms the current path of the power device. The p-type column is used to obtain a high reverse breakdown voltage between the drain and source of the power device. When the power device is turned on, the high impurity concentration in the n-type column makes the on-resistance of the power device small. When the power device is turned off and a reverse voltage is applied, the depletion region between the n-type column and the p-type column extends laterally so that a high reverse breakdown voltage can be formed even with a high impurity concentration in the n-type column.

[0003] There are two main methods for making existing super junction power devices. One method is multi-layer epitaxial technology, that is, multiple epitaxial layers are formed, and a p-type region is formed in each epitaxial layer using a mask process. The p-type regions in multiple epitaxial layers are superimposed up and down to form a p-type column, thereby realizing a super junction structure. The p-type column of the multi-layer epitaxial technology is formed by multiple p-type ion implantation and push junction. Therefore, the device size is large. And the concentration of the interface of the pn junction formed by the injection push junction is uneven, showing a candied haws-like distribution. This curved interface is not conducive to the charge balance on both sides of the pn junction, and may cause the breakdown voltage of the power device to drop. Another method is deep trench epitaxial backfill technology, that is, multiple deep trenches are etched in the epitaxial layer, and then p-type materials are filled in the deep trenches to form p-type columns, thereby realizing a super junction structure. The p-type column of the deep trench epitaxial backfill technology is realized by digging deep trenches and backfilling p-type materials. Its process flow is relatively simple compared to multi-layer epitaxial technology, the device size is usually smaller than multi-layer epitaxy, and the concentration distribution of the pn junction interface is relatively straight, uniform and stable. However, the process of filling the deep trench with epitaxy is difficult, and the p-type columns formed by backfilling are prone to voids, which leads to increased leakage between the source and drain of the power device, and in severe cases may cause the power device to fail. Summary of the invention

[0004] The present application provides a super junction power device and a method for manufacturing the same. The super junction power device provided by the present application has a significantly reduced cell size and excellent on-state performance of the device. In addition, the structure of filling the dielectric in the deep trench greatly reduces the gate-drain capacitance of the device, improves the switching speed of the device, and thereby reduces the switching loss of the device. The manufacturing method provided by the present application forms a semiconductor layer of a specific doping type on the sidewall of the deep trench of the epitaxial layer, and then fills the dielectric in the deep trench covering the semiconductor layer to form a super junction structure in the epitaxial layer. The manufacturing method provided by the present application is simple and easy to implement, and can significantly reduce process time and manufacturing costs.

[0005] According to one embodiment of the present application, a super junction power device is provided, including a substrate layer, an epitaxial layer, a gate structure, a dielectric region, a well region, a source region and a well contact region. The substrate layer has a first conductivity type. The epitaxial layer is located on the substrate layer and has a first conductivity type. The dielectric region is located below the gate structure. The well region is located in the epitaxial layer and on both sides of the gate structure and has a second conductivity type. The source region is located in the well region and on both sides of the gate structure and has a first conductivity type. The well contact region is located in the well region and on both sides of the gate structure and has a second conductivity type. Part of the sidewalls of the dielectric region are covered with a semiconductor layer having a second conductivity type. The portion of the dielectric region that is not covered with the semiconductor layer is at least located below the gate structure between the source regions.

[0006] According to an embodiment of the present application, in the aforementioned super junction power device, on each side of the gate structure, the source region and the well contact region are alternately distributed in a first direction parallel to the length direction of the gate structure.

[0007] According to an embodiment of the present application, in the super junction power device, the well contact region includes an underhang portion, which is connected to a sidewall of the gate structure and to a top of the semiconductor layer.

[0008] According to an embodiment of the present application, a method for manufacturing a super junction power device is provided. The super junction power device includes a first surface and a second surface that are parallel and opposite to each other. The manufacturing method comprises: forming a substrate layer; forming an epitaxial layer on the substrate layer; forming a well region in a portion of the epitaxial layer close to the first surface of the super junction power device; forming a strip-shaped source region in the well region; forming a groove in the epitaxial layer along a direction perpendicular to the strip-shaped source region; covering the groove region between the source regions and the source region with an ion implantation protection layer; performing a first tilted ion implantation to form a semiconductor layer in the groove sidewalls and the well region surface region not covered by the ion implantation protection layer; performing a second tilted ion implantation to form a well contact region in the region of the semiconductor layer close to the top of the groove, wherein the angle of the second tilted ion implantation is greater than the angle of the first tilted ion implantation, and the well contact region includes a flat portion and a hanging portion, and the hanging portion is connected to the semiconductor layer; after removing the ion implantation protection layer, filling the groove with a dielectric to form a dielectric region, wherein the distance from the top of the dielectric region to the first surface of the super junction power device is greater than the distance from the bottom of the well region to the first surface of the super junction power device; and forming a gate structure in the groove filled with the dielectric.

[0009] According to one embodiment of the present application, a method for manufacturing a super junction power device is provided. The super junction power device includes a first surface and a second surface that are parallel and opposite to each other. The manufacturing method includes: forming a substrate layer; forming an epitaxial layer on the substrate layer; forming a well region in the epitaxial layer near the first surface of the super junction power device; forming a strip-shaped source region in the well region; forming a groove in the epitaxial layer along a direction perpendicular to the strip-shaped source region; covering the groove region between the source regions corresponding to both sides of the groove and the source region with an ion implantation protection layer; performing a first tilted ion implantation to form a semiconductor layer on the groove sidewalls and the surface area of ​​the well region that are not covered by the ion implantation protection layer; performing a second tilted ion implantation to reduce the impurity concentration in the region of the semiconductor layer near the top of the groove, wherein the first tilted ion implantation is performed to reduce the impurity concentration in the region of the semiconductor layer near the top of the groove, wherein the second ... The impurity type of the second tilted ion injection is related to the impurity type of the first tilted ion injection, and the angle of the second tilted ion injection is greater than the angle of the first tilted ion injection; vertical ion injection forms a well contact area in the area of ​​the semiconductor layer located in the well area, and the bottom of the well contact area is higher than the bottom of the well area; after removing the ion injection protection layer, a dielectric is filled in the trench to form a dielectric area, wherein the distance from the top of the dielectric area to the first surface of the super junction power device is greater than the distance from the bottom of the well area to the first surface of the super junction power device; and a gate structure is formed in the trench filled with the dielectric.

[0010] According to one embodiment of the present application, a method for manufacturing a super junction power device is provided. The super junction power device includes a first surface and a second surface that are parallel and opposite to each other. The manufacturing method includes: forming a substrate layer; forming an epitaxial layer on the substrate layer; forming a well region in the epitaxial layer near the first surface of the super junction power device; forming a strip-shaped source region in the well region; forming a first groove in the epitaxial layer along a direction perpendicular to the strip-shaped source region; removing the epitaxial layer below the first groove between the well regions to form a second groove, while retaining the epitaxial layer below the first groove between the source regions; covering the area in the first groove between the source regions and above the source region with an ion implantation protection layer; performing a first oblique ion implantation to form a semiconductor layer on the sidewall of the second groove and the surface area of ​​the well region that are not covered by the ion implantation protection layer; performing a second Oblique ion implantation is performed to form a well contact region in the semiconductor layer near the top of the second trench, wherein the angle of the second oblique ion implantation is greater than the angle of the first oblique ion implantation, and the well contact region includes a flat portion and a hanging portion, and the hanging portion is connected to the semiconductor layer; after removing the ion implantation protection layer, a dielectric is filled in the second trench to form a dielectric region, wherein the top of the dielectric region in the second trench is flush with the bottom of the first trench, and the distance from the top of the dielectric region in the second trench to the first surface of the super junction power device is greater than the distance from the bottom of the well region to the first surface of the super junction power device; and a gate structure is formed in the first trench and above the dielectric region.

[0011] According to an embodiment of the present application, in the aforementioned super junction power device, the position where the underhang portion of the well contact region is connected to the semiconductor layer is lower than the bottom of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings:

[0013] Figure 1 is a schematic structural diagram of a partial cell region of a super junction power device 100 according to an embodiment of the present application;

[0014] Figure 2 According to an embodiment of the present application, Figure 1 The schematic diagram of the cross-sectional structure of a partial cell region of the super junction power device 100 along line AA is shown;

[0015] Figure 3 According to an embodiment of the present application Figure 1 The schematic diagram of the cross-sectional structure of a partial cell region of the super junction power device 100 along line BB is shown;

[0016] Figure 4 FIG. 4 shows a top view of a super junction power device 400 according to an embodiment of the present application;

[0017] Figure 5 The steps of a method 500 for manufacturing a super junction power device 100 according to an embodiment of the present application are shown;

[0018] Figure 6A-6J A schematic diagram of a device structure during the process of manufacturing a super junction power device 100 according to a manufacturing method 500 according to an embodiment of the present application is shown;

[0019] Figure 7 is a schematic structural diagram of a partial cell region of a super junction power device 700 according to an embodiment of the present application;

[0020] Figure 8 The steps of a method 800 for manufacturing a super junction power device 700 according to an embodiment of the present application are shown;

[0021] Fig. 9 is a schematic structural diagram of a partial cell region of a super junction power device 900 according to an embodiment of the present application;

[0022] Fig.10 According to an embodiment of the present application Fig. 9 The schematic diagram of the cross-sectional structure of a partial cell region of the super junction power device 900 along the CC line is shown;

[0023] Fig.11According to an embodiment of the present application, Fig. 9 The schematic diagram of the cross-sectional structure of a partial cell region of the super junction power device 900 along the DD line is shown;

[0024] Fig.12 According to another embodiment of the present application, Fig. 9 The schematic diagram of the cross-sectional structure of a partial cell region of the super junction power device 900 along the DD line is shown;

[0025] Fig.13 The steps of a method 1300 for manufacturing a super junction power device 900 according to an embodiment of the present application are shown;

[0026] Figure 14A-14E A schematic diagram of a device in a process of manufacturing a super junction power device 900 according to a manufacturing method 1300 according to an embodiment of the present application is shown;

[0027] Fig.15 Schematic diagram of the structure of a partial cell region of a super junction power device 1500 according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The specific embodiments of the present application will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present application. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present application. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be adopted to implement the present application. In other examples, in order to avoid confusing the present application, known circuits, materials or methods are not specifically described.

[0029] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, particular features, structures or characteristics may be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and that the drawings are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise specified, the same elements have been designated by corresponding reference numerals in different drawings.

[0030] The terms “having,” “comprising,” “including,” “including,” and the like are open ended, and these terms indicate the presence of stated structures, elements, or features, but do not exclude additional elements or features.

[0031] When describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" another layer or region.

[0032] If it is intended to describe a situation where it is directly on another layer or another area, this article will use the expression “directly on…” or “on… and adjacent to…”.

[0033] In this document, relative doping concentrations are described by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means that the doping concentration is lower than the doping concentration of an "n"-doped region, while the "n"-doped region has a higher doping concentration than the "n-"-doped region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doped regions may have the same or different absolute doping concentrations.

[0034] In an embodiment of the present application, each semiconductor layer or region has a first conductivity type or a second conductivity type. The first conductivity type refers to one of n-type or p-type, and the second conductivity type is the other one. That is to say, the semiconductor layer with the first conductivity type can be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer with the first conductivity type is an n-type semiconductor layer, the semiconductor layer with the second conductivity type is a p-type semiconductor layer. The n-type semiconductor layer is formed by doping n-type impurities in the semiconductor layer. The n-type impurities can be pentavalent elements such as phosphorus and arsenic. The p-type semiconductor layer is formed by doping p-type impurities in the semiconductor layer. The p-type impurities can be trivalent elements such as boron, indium, and gallium.

[0035] Figure 1 FIG. 1 is a schematic diagram of a structure of a partial cell region of a super junction power device 100 according to an embodiment of the present application. It should be understood that the super junction power device 100 includes multiple functional regions such as a cell region and a terminal region, and the cell region also includes multiple repeated cell units. For the sake of clarity, Figure 1 Part of the cell regions are shown to facilitate understanding of the embodiments of the present application.

[0036] The super junction power device 100 may be or include an isolated gate field effect transistor, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0037] like Figure 1 As shown, the super junction power device 100 has a first surface 101 and a second surface 102. The first surface 101 and the second surface 102 are parallel to each other and face each other. Figure 1 The y direction shown is in the opposite direction. The super junction power device 100 includes a substrate layer 110 , an epitaxial layer 111 , a gate structure 103 , a well region 112 , a well contact region 114 and a source region 115 .

[0038] exist Figure 1 In the embodiment, the substrate layer 110 has a first surface and a second surface that are parallel and opposite to each other. The first surface of the substrate layer 110 is connected to the epitaxial layer 111, that is, the epitaxial layer 111 is located on the first surface of the substrate layer 110. The second surface of the substrate layer 110 is the second surface 102 of the super junction power device 100. The epitaxial layer 111 has a first surface and a second surface. The first surface of the epitaxial layer 111 is the first surface 101 of the super junction power device 100. The second surface of the epitaxial layer 111 is connected to the first surface of the substrate layer 110. Figure 1 In the embodiment, the substrate layer 110 and the epitaxial layer 111 both have the first conductivity type. The doping concentration of the substrate layer 110 is higher than the doping concentration of the epitaxial layer 111 .

[0039] exist Figure 1 In the embodiment, the super junction power device 100 is an n-type MOSFET, the first conductivity type is n-type, and the second conductivity type is p-type. It should be understood that the first conductivity type and the second conductivity type can be converted with different applications. For example, in a p-type MOSFET, the first conductivity type is p-type and the second conductivity type is n-type.

[0040] Figure 1 The embodiment shows a structure in which the epitaxial layer is a semiconductor layer with a single doping concentration. It should be understood that in other embodiments, the epitaxial layer may include a plurality of semiconductor layers with different doping concentrations.

[0041] exist Figure 1 In the embodiment, the gate structure 103 is a trench gate structure, which is in a strip shape and is located in the epitaxial layer 111, and its length direction is along the Figure 1The gate structure 103 includes a gate trench 131, a gate insulating layer 117 and a gate electrode 116. The gate trench 131 extends vertically from the first surface 101 into the epitaxial layer 111. The gate insulating layer 117 covers the inner wall of the gate trench 131. The gate electrode 116 is located in the gate trench 131 and is isolated from the gate trench 131 by the gate insulating layer 117. In some embodiments, the material of the gate insulating layer 117 can be silicon oxide, silicon nitride or a combination of the two, etc., formed by thermal oxygen growth or deposition. In some embodiments, the gate electrode 116 is made of a conductive material such as metal or polysilicon.

[0042] like Figure 1 As shown, the well region 112 is located in the portion of the epitaxial layer 111 close to the first surface 101. The well region 112 is distributed on both sides of the gate structure 103. The well region 112 has a second conductivity type. The source region 115 is located in the well region 112 and is exposed to the first surface 101. On the first surface 101, as shown in FIG. Figure 1 In the x direction shown in FIG. 1 , the source region 115 is distributed in a strip shape. The strip-shaped source region 115 is perpendicular to the length direction of the gate structure 103 and is cut off by the gate structure 103, forming a structure distributed on both sides of the gate structure 103. The source region 115 has a first conductivity type. The well contact region 114 is located in the well region 112 and is exposed to the first surface 101. On the first surface 101, as shown in FIG. Figure 1 In the x direction shown, the well contact region 114 is distributed in a strip shape. The strip well contact region 114 is perpendicular to the length direction of the gate structure 103 and is cut off by the gate structure 103, forming a structure distributed on both sides of the gate structure 103. Figure 1 In the z direction shown, the well contact region 114 is connected to the source region 115. The source region 115 and the well contact region 114 are distributed on both sides of the gate structure 103 along the length direction of the gate structure 103.

[0043] exist Figure 1 In the embodiment, a dielectric region 118 is distributed below the gate structure 103 . The dielectric region 118 extends from the bottom of the gate structure 103 to the second surface of the epitaxial layer 111 , that is, to the first surface of the substrate layer 110 .

[0044] exist Figure 1 In the embodiment, the dielectric region 118 includes a first dielectric region 118a and a second dielectric region 118b. The first dielectric region 118a and the second dielectric region 118b are alternately arranged along the z direction. The first dielectric region 118a is located below the gate structure 103 and between the well contact regions 114 on both sides of the gate structure 103. The second dielectric region 118b (eg Figure 2The first dielectric region 118a and the second dielectric region 118b are arranged alternately along the z direction. The sidewalls of the first dielectric region 118a along the z direction are covered with a semiconductor layer 113. The semiconductor layer 113 has a second conductivity type.

[0045] The well contact region 114 includes a flat portion 114a and a hanging portion 114b. Figure 1 The two regions are distinguished by dashed lines. The underhang portion 114b is connected to the flat portion 114a and extends downward along the sidewall of the gate structure 103, that is, extends in a direction away from the first surface 101. The bottom of the underhang portion 114b of the well contact region 114 is connected to the semiconductor layer 113. Figure 1 In the embodiment, the interface position where the underhang portion 114b of the well contact region 114 and the semiconductor layer 113 are connected is lower than the bottom of the gate structure 103. For SiC MOSFET devices, when the gate structure 103 is a trench gate structure, the interface position where the well contact region 114 and the semiconductor layer 113 are connected is lower than the bottom of the gate structure 103, which can effectively reduce the maximum electric field of the gate oxide of the trench gate and improve the long-term reliability of the device.

[0046] exist Figure 1 In an embodiment, the doping concentration of the well contact region 114 is higher than the doping concentration of the semiconductor layer 113. Relatively speaking, the well contact region 114 and the source region 115 are both high doping concentration regions. When the super junction power device 100 is applied to a circuit, the well contact region 114 is connected to the well potential, and the source region 115 is connected to the source potential. In some embodiments, the well potential and the source potential are the same.

[0047] Figure 2 According to an embodiment of the present application, Figure 1 FIG. 1 is a schematic diagram of a cross-sectional structure of a portion of a cell region of a super junction power device 100 along line AA. Figure 2As shown, the well region 112 is located in the region of the epitaxial layer 111 close to the first surface 101, and the source region 115 is located in the well region 112, and its bottom does not exceed the bottom of the well region 112, that is, the entire source region 115 is located in the well region 112. One side wall of the source region 115 and the well region 112 is connected to the side wall of the gate structure 103. Below the gate structure 103 is a second dielectric region 118b connected to the bottom of the gate structure 103. In this cross section, there is no semiconductor layer 113 on the side walls of the second dielectric region 118b along the z direction, and the second dielectric region 118b is directly connected to the epitaxial layer 111 on both sides. The epitaxial layer 111 on both sides of the second dielectric region 118b provides a current path from the source region 115 to the substrate layer 110. It should be understood that when the current capability of the device is not required to be high, the semiconductor layer 113 can be appropriately extended to the area between the source regions 115, and it is not necessary to be under the gate structure 103 between the well contact regions 114. Similarly, when the power device has other regions besides the well contact region 114 and the source region 115, the sidewalls of the dielectric region under the gate structure between the other regions can also be covered with the semiconductor layer 113. In other words, as long as a certain area not covered by the semiconductor layer 113 is retained on the sidewalls of the dielectric region under the gate structure between the sources to ensure the current path from the source region to the substrate layer, it is not necessary that all the sidewalls of the dielectric region under the gate structure between the sources are not covered by the semiconductor layer 113. Similarly, the semiconductor layer 113 does not necessarily cover all the sidewalls of the dielectric region under the gate structure 103 between the well contact regions 114.

[0048] In the super junction power device 100, the n-type epitaxial layer 111 and the p-type semiconductor layer 113 form a super junction structure. The dielectric region 118 located below the gate structure 103 also reduces the gate-drain capacitance of the super junction power device 100, thereby increasing the switching speed of the super junction power device 100 and reducing switching losses.

[0049] Figure 3 According to an embodiment of the present application Figure 1 The cross-sectional structure diagram of a part of the cell region of the super junction power device 100 along the BB line is shown. The cross section along the BB line is parallel to the first surface 101 and the second surface 102. Figure 3 As shown in the cross section, the first dielectric region 118a and the second dielectric region 118b arranged alternately at the bottom of the gate structure 103 can be seen. The first dielectric region 118a is arranged along the length direction of the gate structure 103 (i.e., along the length direction of the gate structure 103). Figure 1 The side walls in the z direction (as shown) are covered with a semiconductor layer 113.

[0050] Figure 4FIG. 4 shows a top view of a super junction power device 400 according to an embodiment of the present application. The top view shows a first surface of a partial cell region of the super junction power device 400. Figure 4 As shown, on the first surface, the source region 415 and the well contact region 414 are alternately arranged along the length direction of the gate structure 103. In existing power devices, the source region and the well contact region are usually arranged in a direction perpendicular to the length direction of the gate structure, for example, one side of the source region is connected to the side wall of the gate structure, and the well contact region is arranged on the other side of the source region and connected to the other side of the source region. In this case, the length of a single cell in a direction perpendicular to the length direction of the gate structure is relatively large. The embodiment of the present application arranges the source region and the well contact region alternately in a direction parallel to the gate structure, which effectively reduces the cell size of the super junction power device and improves the conduction performance of the super junction power device.

[0051] Figure 5 FIG. 5 shows the steps of a method 500 for manufacturing a super junction power device 100 according to an embodiment of the present application. Figure 5 The steps of the manufacturing method 500 shown do not necessarily have a sequential order. The manufacturing method 500 includes: step 501, forming a substrate layer 110; step 502, forming an epitaxial layer 111 on the substrate layer 110; step 503, forming a well region 112 in the epitaxial layer 111 near the first surface 101 of the super junction power device 100; step 504, forming a strip-shaped source region 115 in the well region 112; step 505, forming a groove in the epitaxial layer 111 along a direction perpendicular to the strip-shaped source region 115; step 506, covering the groove area between the source regions 115 and the source region 115 with an ion implantation protection layer; step 507, performing a first tilted ion implantation to form a semiconductor layer on the sidewalls of the groove and the surface of the well region 112 not covered by the ion implantation protection layer; step 508, performing a second tilted ion implantation to form a semiconductor layer on the sidewalls of the groove and the surface of the well region 112 not covered by the ion implantation protection layer. Injection, forming a well contact region 114 in the area of ​​the semiconductor layer near the top of the groove, wherein the angle of the second tilted ion injection is greater than the angle of the first tilted ion injection, and the well contact region 114 includes a flat portion 114a and a hanging portion 114b, and the hanging portion 114b is connected to the semiconductor layer 113, and the connecting position is lower than the bottom of the well region 114; step 509, after removing the ion implantation protection layer, filling the trench with a dielectric to form a dielectric region 118, wherein the distance from the top of the dielectric region 118 to the first surface 101 of the super junction power device 100 is greater than the distance from the bottom of the well region 112 to the first surface 101 of the super junction power device 100; and step 510, forming a gate structure 103 in the trench filled with the dielectric.

[0052] Figure 6A-6JFIG. 5 is a schematic diagram showing a device structure in a process of manufacturing a super junction power device 100 according to a manufacturing method 500 according to an embodiment of the present application. Figure 5 and Figures 6A-6J A method 500 for manufacturing the super junction power device 100 is described below.

[0053] Fig. 6A Schematic diagram of the device structure after the steps 501 and 502 are implemented according to an embodiment of the present application. At this time, the super junction power device 100 has a substrate layer 110 and an epitaxial layer 111 located on the substrate layer 110. The substrate layer 110 and the epitaxial layer 111 have a first conductivity type, and the doping concentration of the substrate layer 110 is higher than the doping concentration of the epitaxial layer 111. In some embodiments, the first conductivity type is n-type, and the substrate layer 110 and the epitaxial layer 111 are both n-type semiconductor layers, but have different doping concentrations.

[0054] Figure 6B Schematic diagram of the device structure after step 503 according to an embodiment of the present application is implemented. At this time, the epitaxial layer 111 of the super junction power device 100 close to the first surface 101 forms a well region 112. The manufacturing method of the well region 112 can be any applicable method, such as ion implantation. It should be understood that when there are other areas on the surface of the power device and ion implantation is required in certain specific areas to form the well region 112, the manufacturing method of the well region 112 also includes a masking process to achieve ion implantation in specific areas.

[0055] Figure 6C Schematic diagram of the device structure after step 504 is implemented according to an embodiment of the present application. At this time, a source region 115 with a high doping concentration is formed in the well region 112 of the super junction power device 100. In some embodiments, the well region 112 is a p-type semiconductor region with a relatively low doping concentration, and the source region 115 is an n-type semiconductor region with a relatively high doping concentration. The source region 115 can be made by a suitable process technology, such as a mask process, that is, covering the first surface 101 of the device with a mask (such as photoresist), and then forming a window at a specific position on the mask, and then injecting impurities into the device through the window of the mask to form the source region 115.

[0056] Fig.6D Schematic diagram of the device structure after step 505 is implemented according to an embodiment of the present application. At this time, the super junction power device 100 forms a groove 104 in a direction perpendicular to the strip-shaped source region 115, dividing the source region 115 into parts located on both sides of the groove. The bottom of the groove 104 reaches the substrate layer 110. The groove 104 can be made by any applicable method. For example, a window is formed at the position of the groove by a mask process, and then the epitaxial layer 111 is etched toward the window position.

[0057] Fig. 6ESchematic diagram of the device structure after step 506 is implemented according to an embodiment of the present application. At this time, the source region 115 and the groove 104 between the source regions 115 are covered with an ion implantation protection layer 105. The ion implantation protection layer 105 can be a photoresist, a silicon oxide layer, a silicon nitride layer, polysilicon or a combination of different materials. After covering the ion implantation protection layer 105, the well region 112 on the first surface 101 of the device and the portion in the groove 104 not covered by the ion implantation protection layer 105 are both in an exposed state.

[0058] Fig. 6F FIG. 5 is a schematic diagram of the device structure after step 507 is implemented according to an embodiment of the present application. In step 507, a first oblique ion implantation method is used to implant impurities into the sidewalls of the trench 104 and the surface of the well region 112 of the device to form a semiconductor layer with a specific conductivity type. In one embodiment, the implanted impurities are p-type impurities, and the trench sidewalls and the well region not covered by the ion implantation protection layer 105 form a p-type layer, such as Fig. 6F As shown. By controlling the angle A1 of the tilted ion implantation and the intensity of the implantation, the thickness and doping concentration of the p-type layer can be controlled. Fig. 6F In the embodiment, the semiconductor layer 113 covers the bottom of the trench, that is, the bottom of the semiconductor layer 113 reaches the substrate layer 110 . In some embodiments, the bottom of the semiconductor layer 113 may not extend to the substrate layer 110 .

[0059] Figure 6G Schematic diagram of the device structure after step 508 according to an embodiment of the present application is implemented. In step 508, a second tilted ion implantation is used to form a well contact region 114 in a region near the top of the trench in the semiconductor layer 113 formed after the first tilted ion implantation. In one embodiment, the implanted impurities are p-type impurities, and the angle A2 of the second tilted ion implantation is greater than the angle A1 of the first tilted ion implantation, thereby forming a region near the top of the trench with a higher doping concentration than the original semiconductor layer 113. By controlling the angle A2 of the second tilted ion implantation, the length of the underhanging portion 114b of the well contact region 114 extending toward the semiconductor layer 113 can be controlled.

[0060] Figure 6H FIG. 1 is a schematic diagram of a device structure after removing the ion implantation protection layer 105 according to an embodiment of the present application. Figure 6HAs shown, at this time, the well region 112 on each side of the trench 104 forms a source region 115 and a well contact region 114 that are arranged at intervals and connected. The well contact region 114 includes a flat portion 114a and a hanging portion 114b that are connected. The hanging portion 114b is connected to the semiconductor layer 113. Below the source region 115 are the well region 112, the epitaxial layer 111 and the bottom substrate layer 110. Therefore, the current channel from the source region 115 to the substrate layer 110 is guaranteed.

[0061] Fig.6I Schematic diagram of the device structure after implementation step 509 according to an embodiment of the present application. At this time, the trench of the super junction device 100 is filled with a dielectric region 118. The material of the dielectric region 118 can be an insulating material with a high dielectric constant such as silicon oxide, silicon nitride, aluminum oxide, or a combination of different insulating materials. It should be understood that after the dielectric is filled into the trench, the top of the dielectric region may be uneven or the height of the dielectric region in each trench may be inconsistent due to process reasons. Therefore, there may also be a procedure for further processing the dielectric region 118, such as etching and polishing.

[0062] Figure 6J FIG. 5 is a schematic diagram of a device structure after step 510 is implemented according to an embodiment of the present application. Figure 6J As shown, after the dielectric region 118 is formed, a gate structure 103 is formed in the remaining trench at the top of the dielectric region 118. Any method suitable for forming a trench gate structure can be used in the embodiment of the present application. For example, a silicon oxide layer can be first formed in the trench as a gate insulating layer 117 by deposition, and then a conductive material such as metal or polysilicon is filled into the trench to form a gate electrode 116.

[0063] Figure 7 Schematic diagram of the structure of a partial cell region of a super junction power device 700 according to an embodiment of the present application. Compared with the super junction power device 100, the well contact region 714 of the super junction power device 700 does not include a hanging portion. The well contact region 714 of the super junction power device 700 includes only a flat portion, which is adjacent to the side wall of the gate structure 103 and the source region 115 in different directions, and is arranged at intervals with the source region 115 along the length direction of the gate structure 103 and distributed in the well region 712. In the super junction power device 700, when a specific voltage is applied to the device gate electrode so that the device channel is turned on to conduct current, the side wall of the well region 712 below the well contact region 714 also forms a channel, which increases the channel area, reduces the channel resistance, and improves the conduction capability of the device.

[0064] Figure 8 FIG. 8 shows the steps of a method 800 for manufacturing a super junction power device 700 according to an embodiment of the present application. Figure 8The steps of the manufacturing method 800 shown do not necessarily have a sequential order. The manufacturing method 800 comprises: step 801, forming a substrate layer 110; step 802, forming an epitaxial layer 111 on the substrate layer 110; step 803, forming a well region 712 in the epitaxial layer 111 near the first surface 101 of the super junction power device 700; step 804, forming a strip-shaped source region 115 in the well region 712; step 805, forming a groove 104 in the epitaxial layer along a direction perpendicular to the strip-shaped source region 115; step 806, covering the groove region between the source regions 115 and the source region 115 with an ion implantation protection layer; step 807, performing a first tilted ion implantation, forming a semiconductor layer 113 on the groove sidewall and the well region surface region not covered by the ion implantation protection layer; step 808, performing a second tilted ion implantation, reducing the impurity concentration of the region of the semiconductor layer near the top of the groove (i.e., the region of the well region 712 where the doping concentration is increased by the first tilted ion implantation to form the semiconductor layer) to restore the semiconductor layer to the state as shown in FIG. Figure 7 The well region 712 is shown. In some embodiments, the impurities implanted by the first tilted ion implantation are p-type impurities, and the semiconductor layer 113 is p-type doped. During the first tilted ion implantation, the concentration of the well region 712 near the groove is higher than that of the remaining portion. During the second tilted ion implantation, n-type impurities are implanted to neutralize the concentration of the well region 712 near the groove, restoring it to its original doping concentration. In order to allow the impurities of the second tilted ion injection to be injected into the part of the well region 712 close to the groove, the angle of the second tilted ion injection is greater than the angle of the first tilted ion injection; step 809, vertical ion injection to form a well contact region 714 in the well region 712; step 810, after removing the ion injection protection layer, filling the trench with dielectric to form a dielectric region 118, wherein the distance from the top of the dielectric region 118 to the first surface 101 of the super junction power device 700 is greater than the distance from the bottom of the well region 712 to the first surface 101 of the super junction power device 700; and step 811, forming a gate structure 103 in the trench filled with dielectric.

[0065] Except for the difference in the angle of the second tilted ion implantation, the impurity type and the subsequent steps of forming the well contact region, the manufacturing method 800 of the super junction power device 700 is substantially the same as the manufacturing method 500 of the super junction power device 100 and will not be further elaborated here.

[0066] Fig. 9 FIG. 1 is a schematic diagram of a structure of a partial cell region of a super junction power device 900 according to an embodiment of the present application. Figure 1 Compared to the illustrated super junction power device 100 , the structure of the dielectric region 918 of the super junction power device 900 is different. Fig.10 According to an embodiment of the present application Fig. 9The cross-sectional structure diagram of a partial cell region of a super junction power device 900 along the CC line is shown.

[0067] like Fig.10 As shown, the well region 112 is located in the epitaxial layer 111 in the region close to the first surface 101, and the source region 115 is located in the well region 112, and its bottom does not exceed the bottom of the well region 112, that is, the entire source region 115 is located in the well region 112. The sidewalls of the source region 115 and the well region 112 are connected to the sidewalls of the gate structure 103. Below the gate structure 103 is the epitaxial layer 111 connected to the bottom of the gate structure 103. In other words, compared with the super junction power device 100, the super junction power device 900 does not have a second dielectric region. The middle of each dielectric region 918 is isolated by the epitaxial layer 111. The dielectric region 918 is located at the bottom of the gate structure 103 and between the well contact regions 114. At the bottom of the gate structure 103 and between the source regions 115 is the epitaxial layer 111.

[0068] Fig.11 According to an embodiment of the present application, Fig. 9 The cross-sectional structure diagram of a part of the cell region of the super junction power device 900 along the DD line is shown. The cross section along the DD line is parallel to the first surface 101 and the second surface 102. Fig.11 As shown in FIG. 1 , in this cross section, a dielectric region 918 located at the bottom of the gate structure 103 can be seen. The two dielectric regions 918 are separated by the epitaxial layer 111. Figure 1 The side walls in the z direction (as shown) are covered with a semiconductor layer 113.

[0069] Fig.12 According to another embodiment of the present application, Fig. 9 The cross-sectional structure diagram of a part of the cell region of the super junction power device 900 along the DD line is shown. The cross section along the DD line is parallel to the first surface 101 and the second surface 102. Fig.12 As shown in FIG. 1 , in this cross section, a dielectric region 918 located at the bottom of the gate structure 103 can be seen. The two dielectric regions 918 are separated by the epitaxial layer 111. Figure 1 The z direction shown in FIG. 1 ) and the length direction perpendicular to the gate structure 103 (i.e., along the direction shown in FIG. Figure 1 The side walls (in the x direction shown) are covered with a semiconductor layer 113.

[0070] Fig.13 FIG. 1 shows the steps of a method 1300 for manufacturing a super junction power device 900 according to an embodiment of the present application. Fig.13The steps of the manufacturing method 1300 shown are not necessarily in a sequential order. The manufacturing method 1300 includes: step 1301, forming a substrate layer 110; step 1302, forming an epitaxial layer 111 on the substrate layer 110; step 1303, forming a well region 112 in the epitaxial layer 111 near the first surface 101 of the super junction power device 900; step 1304, forming a strip-shaped source region 115 in the well region 112; step 1305, forming a first trench 904 in the epitaxial layer 111 along a direction perpendicular to the strip-shaped source region 115; step 1306, On the basis of the first trench 904, the epitaxial layer 111 located between the well regions below the first trench is removed to form a second trench 905, and the epitaxial layer 111 located between the source regions 115 below the first trench 904 is retained at the same time; step 1307, the region between the source regions 115 in the first trench 904 and the region above the source region 115 are covered with an ion implantation protection layer; step 1308, a first tilted ion implantation is performed to form an ion implantation protection layer on the sidewall of the second trench 905 and the region on the surface of the well region 112 not covered by the ion implantation protection layer The semiconductor layer 113 is formed by a second tilted ion implantation, wherein the well contact region 114 is formed in the region of the semiconductor layer 113 near the top of the second trench 905, wherein the angle A2 of the second tilted ion implantation is greater than the angle A1 of the first tilted ion implantation, and the well contact region 114 includes a flat portion 114a and a hanging portion 114b, wherein the hanging portion 114b is connected to the semiconductor layer 113, and the connecting position is lower than the bottom of the well region 112; Step 1310, after removing the ion implantation protection layer, the well contact region 114 is formed by a second tilted ion implantation, wherein the angle A2 of the second tilted ion implantation is greater than the angle A1 of the first tilted ion implantation, and the well contact region 114 includes a flat portion 114a and a hanging portion 114b, wherein the hanging portion 114b is connected to the semiconductor layer 113, and the connecting position is lower than the bottom of the well region 112; Step 1311, after removing the ion implantation protection layer, the well contact region 114 is formed by a second tilted ion implantation, wherein ... A dielectric is filled in the second trench 905 to form a dielectric region 918, wherein the top of the dielectric region 918 in the second trench 905 is flush with the bottom of the first trench 904, and the distance from the top of the dielectric region 918 in the second trench 905 to the first surface 101 of the super junction power device 900 is greater than the distance from the bottom of the well region 112 to the first surface 101 of the super junction power device 900; and step 1311, forming a gate structure 103 in the first trench 904 and above the dielectric region 918.

[0071] Figure 14A-14E FIG. 1 is a schematic diagram of a device in a process of manufacturing a super junction power device 900 according to a manufacturing method 1300 according to an embodiment of the present application. Fig.13 and Figures 14A-14E A method 1300 for manufacturing the super junction power device 900 is described.

[0072] Fig.14ASchematic diagram of the device structure after the steps 1301-1305 of one embodiment of the present application are implemented. At this time, the super junction power device 900 forms a first groove 904 in a direction perpendicular to the strip-shaped source region 115, dividing the source region 115 into parts located on both sides of the first groove 904. The bottom of the first groove 904 is located in the epitaxial layer 111 and is lower than the bottom of the well region 112. The first groove 904 can be made by any applicable method. For example, a window is formed at the position of the groove by a masking process, and then the epitaxial layer 111 is etched at the window position.

[0073] Fig. 14B 1 is a schematic diagram of the device structure after step 1306 according to an embodiment of the present application is implemented. At this time, the epitaxial layer 111 located between the well regions below the first trench 904 is removed to form the second trench 905. At the same time, the epitaxial layer 111 located between the source regions 115 below the first trench 904 is retained. The second trench 905 can be made by any suitable method. For example, a window is formed at the position of the second trench by a masking process, and then the epitaxial layer 111 is etched at the window position. Then, as shown in FIG. Fig. 14B The mask plate 106 shown will be removed, or the mask plate 106 will be further photolithographically processed to form the ion implantation protection layer 105 required in the next step.

[0074] Fig. 14C 1 is a schematic diagram of the device structure after step 1307 according to an embodiment of the present application is implemented. At this time, the first trench 904 between the source regions 115 and the surface position of the source region 115 are covered with the ion implantation protection layer 105. The ion implantation protection layer can be a photoresist, a silicon oxide layer, a silicon nitride layer, polysilicon or a combination of multiple materials. After covering the ion implantation protection layer 105, the well region position not covered by the ion implantation protection layer 105 and the second trench 905 are both in an exposed state.

[0075] Fig.14D1 is a schematic diagram of the device structure after the steps 1308 and 1309 of one embodiment of the present application are implemented. In step 1308, the first tilted ion implantation method is used to implant impurities into the sidewalls and well region surfaces inside the second trench 905 of the device to form a semiconductor layer 113 with a specific conductivity type. In one embodiment, the implanted impurities are p-type impurities, and the two sides of the trench and the well region that are not covered by the ion implantation protection layer 105 form a p-type layer. Then in step 1309, a second tilted ion implantation method is used to form a well contact region 114 in the region near the top of the second trench 905 of the semiconductor layer 113 formed after the first tilted ion implantation. In one embodiment, the implanted impurities are p-type impurities, and the angle A2 of the second tilted ion implantation is greater than the angle A1 of the first tilted ion implantation, thereby forming a region with a higher doping concentration than the original semiconductor layer 113 in the region near the top of the trench. By controlling the angle A2 of the second tilted ion implantation, the length of the hanging portion 114b of the well contact region 114 can be controlled.

[0076] It should be understood that the underhang portion 114b of the well contact region 114 is not necessary. In the manufacturing method 1300, the step 1309 of performing the second tilted ion implantation can be replaced with the steps 808 and 809 in the manufacturing method 800, that is, performing the second tilted ion implantation and the vertical ion implantation, so as to form the well contact region 114 without the underhang portion.

[0077] Fig.14E FIG. 1 is a schematic diagram of a device structure after step 1310 is implemented according to an embodiment of the present application. In step 1310, the ion implantation protection layer 105 is removed, and then a dielectric is filled in the second trench 905 to form a dielectric region 918. The top of the dielectric region 918 and the top of the epitaxial layer 111 located between adjacent dielectric regions 918 together constitute the bottom of the gate structure 103. Fig.14E After forming the gate structure 103 in the device trench shown in FIG. Fig. 9 A super junction power device 900 is shown.

[0078] Fig.15 FIG. 1 is a schematic diagram of a structure of a partial cell region of a super junction power device 1500 according to an embodiment of the present application. Figure 1Compared with the super junction power device 100 shown in FIG. 1 , the sidewalls of the dielectric region 1518 of the super junction power device 1500 are not perpendicular to the first surface and the second surface of the super junction power device 1500. The dielectric region 1518 forms a structure that is narrow at the bottom and wide at the top, which is beneficial to improving the quality of the semiconductor layer 113 during the device manufacturing process. It should be understood that in the super junction power device 1500, the distribution of the dielectric region 1518 can be divided into a first dielectric region between the well contact regions 114 and a second dielectric region between the source regions 115 alternately as in the super junction power device 100, or the dielectric region 1518 can be located between the well contact regions 114 and the epitaxial layer 111 is located between the source regions 115 as in the super junction power device 900.

[0079] This application uses a MOSFET device with a trench gate structure as an example to illustrate the principle of the invention. It should be understood that the present invention is also applicable to power devices with a planar gate structure. After reading this application, a person of ordinary skill in the art can combine the present invention with a power device with a planar gate structure as needed to realize a superjunction structure in a power device with a planar gate structure.

[0080] This application uses strip cells as an example to illustrate the principles of the invention. It should be understood that the present invention is also applicable to cell structures of other shapes, such as circular, hexagonal, etc. Specifically, in cell structures of other shapes, for example, p-columns in the superjunction can be replaced with dielectric regions of the p-type semiconductor layer whose sidewalls are covered in the embodiment of this application, or n-columns in the superjunction can be replaced with dielectric regions of the n-type semiconductor layer whose sidewalls are covered in the embodiment of this application, which is also in line with the spirit of the present invention.

[0081] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A super junction power device, comprising: A substrate layer having a first conductivity type; an epitaxial layer, located on the substrate layer, and having a first conductivity type; Gate structure; a dielectric region, located below the gate structure; The well region is located in the epitaxial layer and on both sides of the gate structure, and has a second conductivity type; A source region, located in the well region and on both sides of the gate structure, connected to the sidewall of the gate structure, and having a first conductivity type; as well as A well contact region, located in the well region and on both sides of the gate structure, connected to the sidewall of the gate structure, and having a second conductivity type; Wherein, on each side of the gate structure, the source region and the well contact region are alternately distributed in a first direction parallel to the length direction of the gate structure; A semiconductor layer of the second conductivity type is covered on the sidewall of the dielectric region, the semiconductor layer is discontinuous in the first direction, and a portion of the dielectric region not covered by the semiconductor layer is at least located under the gate structure between the source regions. 2 . The super junction power device according to claim 1 , wherein the well contact region comprises an underhang portion, wherein the underhang portion is connected to a side wall of the gate structure and to a top of the semiconductor layer. 3 . The super junction power device as claimed in claim 2 , wherein the position where the underhanging portion of the well contact region is connected to the semiconductor layer is lower than the bottom of the gate structure.

4. The super junction power device as claimed in claim 1, wherein the dielectric region includes a first dielectric region and a second dielectric region that are alternately distributed and connected in a first direction parallel to the length direction of the gate structure, the first dielectric region is located under the gate structure between the well contact regions, and the first dielectric region is covered with a semiconductor layer with a second conductivity type on the side wall along the first direction, and the second dielectric region is located under the gate structure between the source regions.

5. The super junction power device as claimed in claim 1, wherein the dielectric region is located below the gate structure between the well contact regions, and below the gate structure between the source regions is an epitaxial layer, and in a first direction parallel to the length direction of the gate structure, multiple dielectric regions are isolated by the epitaxial layer, and the side walls of the dielectric region along the first direction are covered with a semiconductor layer having a second conductivity type.

6. The super junction power device as claimed in claim 1, wherein the dielectric region is located below the gate structure between the well contact regions, and below the gate structure between the source regions is an epitaxial layer, in a first direction parallel to the length direction of the gate structure, multiple dielectric regions are isolated by the epitaxial layer, and the side walls of the dielectric region are covered with a semiconductor layer having a second conductivity type.

7. The super junction power device as described in claim 1 has a parallel first surface and a second surface, wherein the top of the dielectric region is connected to the bottom of the gate structure, and the distance from the bottom of the gate structure to the first surface of the super junction power device is greater than the distance from the bottom of the well region to the first surface of the super junction power device. 8 . The super junction power device of claim 1 , wherein the gate structure comprises a trench gate structure.

9. A method for manufacturing a super junction power device, the super junction power device comprising a first surface and a second surface that are parallel and opposite to each other, the method comprising: forming a substrate layer; forming an epitaxial layer on the substrate layer; forming a well region in a portion of the epitaxial layer close to the first surface of the super junction power device; forming a source region distributed in a stripe shape in the well region; forming a trench in the epitaxial layer along a direction perpendicular to the strip-shaped source region; Covering the trench regions between the source regions and the source regions with an ion implantation protection layer; A first oblique ion implantation is performed to form a semiconductor layer on the trench sidewalls and the surface area of ​​the well region that are not covered by the ion implantation protection layer; A second tilted ion implantation is performed to form a well contact region in a region of the semiconductor layer close to the top of the trench, wherein the angle of the second tilted ion implantation is greater than the angle of the first tilted ion implantation, and the well contact region includes a flat portion and a hanging portion, and the hanging portion is connected to the semiconductor layer; After removing the ion implantation protection layer, a dielectric is filled in the trench to form a dielectric region, wherein a distance from a top of the dielectric region to a first surface of the super junction power device is greater than a distance from a bottom of the well region to the first surface of the super junction power device; and A gate structure is formed in the trench filled with the dielectric.

10. The method for manufacturing a super junction power device according to claim 9, wherein: The position where the underhang portion of the well contact region contacts the semiconductor layer is lower than the bottom of the well region.

11. A method for manufacturing a super junction power device, the super junction power device comprising a first surface and a second surface which are parallel and opposite to each other, the method comprising: forming a substrate layer; forming an epitaxial layer on the substrate layer; forming a well region in a portion of the epitaxial layer close to the first surface of the super junction power device; forming a source region distributed in a stripe shape in the well region; forming a trench in the epitaxial layer along a direction perpendicular to the strip-shaped source region; Covering the trench area between the source areas corresponding to the two sides of the trench and the source areas with an ion implantation protection layer; A first oblique ion implantation is performed to form a semiconductor layer on the trench sidewalls and the surface area of ​​the well region that are not covered by the ion implantation protection layer; A second tilted ion implantation is performed to reduce the impurity concentration in the region of the semiconductor layer close to the top of the trench, wherein the impurity type of the second tilted ion implantation is opposite to the impurity type of the first tilted ion implantation, and the angle of the second tilted ion implantation is greater than the angle of the first tilted ion implantation; Vertical ion implantation forms a well contact region in a region of the semiconductor layer located in the well region, wherein the bottom of the well contact region is higher than the bottom of the well region; After removing the ion implantation protection layer, a dielectric is filled in the trench to form a dielectric region, wherein a distance from a top of the dielectric region to a first surface of the super junction power device is greater than a distance from a bottom of the well region to the first surface of the super junction power device; and A gate structure is formed in the trench filled with the dielectric.

12. A method for manufacturing a super junction power device, the super junction power device comprising a first surface and a second surface which are parallel and opposite to each other, the method comprising: forming a substrate layer; forming an epitaxial layer on the substrate layer; forming a well region in a portion of the epitaxial layer close to the first surface of the super junction power device; forming a source region distributed in a stripe shape in the well region; forming a first trench in the epitaxial layer along a direction perpendicular to the strip-shaped source region; removing the epitaxial layer below the first trench between the well regions to form a second trench, while retaining the epitaxial layer below the first trench between the source regions; Covering the region within the first trench between the source regions and the source regions with an ion implantation protection layer; A first oblique ion implantation is performed to form a semiconductor layer on the sidewall of the second trench and the surface area of ​​the well region that are not covered by the ion implantation protection layer; A second tilted ion implantation is performed to form a well contact region in a region of the semiconductor layer close to the top of the second trench, wherein the angle of the second tilted ion implantation is greater than the angle of the first tilted ion implantation, and the well contact region includes a flat portion and a hanging portion, and the hanging portion is connected to the semiconductor layer; After removing the ion implantation protection layer, a dielectric is filled in the second trench to form a dielectric region, wherein the top of the dielectric region in the second trench is flush with the bottom of the first trench, and the distance from the top of the dielectric region in the second trench to the first surface of the super junction power device is greater than the distance from the bottom of the well region to the first surface of the super junction power device; as well as A gate structure is formed in the first trench and over the dielectric region.

13. The method for manufacturing a super junction power device according to claim 12, wherein: The position where the underhang portion of the well contact region contacts the semiconductor layer is lower than the bottom of the well region.

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