Enhanced cascade coupled laser chip and preparation method thereof

Abstract

The present invention discloses an enhanced cascade coupling laser chip and a preparation method, comprising: an on-chip Bragg reflection grating, a ridge waveguide array, a first leakage groove, a tapered waveguide array, a second leakage groove and a cascade coupling region sequentially arranged on the upper surface of the same epitaxial structure; the on-chip Bragg reflection grating is arranged on the rear end face of the ridge waveguide array, the first leakage groove is arranged on both sides of each ridge waveguide in the ridge waveguide array, the second leakage groove is arranged on both sides of each tapered waveguide in the tapered waveguide array, and the cascade coupling region is arranged on the front end face of the tapered waveguide array. The present invention improves the selection characteristics of the laser longitudinal mode and the transverse mode mode by arranging the on-chip Bragg reflection grating at the rear end of the ridge waveguide array and cooperating with the first leakage groove and the second leakage groove, and then obtains a high-power laser beam output through the amplification effect of the tapered waveguide array and the coupling effect of the cascade coupling region, and finally obtains a high-brightness, high-power fundamental mode beam output.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and in particular to an enhanced cascade coupled laser chip and a preparation method thereof. Background Art

[0002] With the development of semiconductor technology and laser technology, the application fields of semiconductor lasers are becoming more and more extensive, including medical treatment, laser processing, optical communication and other fields. Among them, the conical laser is composed of a ridge-shaped single-mode region and a conical amplification region. Because of its simple preparation process and high-brightness and high-power laser output, it has become a research hotspot in semiconductor lasers.

[0003] During the operation of tapered laser arrays, the tapered waveguide feedback light of each laser will lead to the generation of high-order modes. High-order mode feedback light will also appear during the array coupling process, resulting in a decrease in the laser array beam quality and chaotic mode operation, affecting the performance of the laser in practical applications. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides an enhanced cascade coupled laser chip and a preparation method thereof.

[0005] The present invention discloses an enhanced cascade coupling laser chip, comprising: an on-chip Bragg reflection grating, a ridge waveguide array, a first leakage groove, a tapered waveguide array, a second leakage groove and a cascade coupling region, which are sequentially arranged on the upper surface of the same epitaxial structure;

[0006] The on-chip Bragg reflection grating is arranged on the rear end face of the ridge waveguide array, and the periods of the on-chip Bragg reflection grating, the ridge waveguide array, and the tapered waveguide array are consistent; the first leakage groove is arranged on both sides of each ridge waveguide in the ridge waveguide array and close to the tapered waveguide array; the second leakage groove is arranged on both sides of each tapered waveguide in the tapered waveguide array and close to the cascade coupling region; the cascade coupling region is arranged on the front end face of the tapered waveguide array.

[0007] As a further improvement of the present invention, the epitaxial structure includes an N-type confinement layer, an N-face waveguide layer, an active region, a P-face waveguide layer, a P-type confinement layer and a P-face ohmic contact layer which are sequentially arranged on the upper surface of the N-type substrate from bottom to top, an N-face electrode is arranged on the lower surface of the N-type substrate, an insulating layer and a P-face electrode are formed on the upper surface of the epitaxial structure, and P-face electrode windows are opened at the insulating layers corresponding to the ridge waveguide array, the tapered waveguide array and the cascade coupling region; wherein the on-chip Bragg reflection grating is vertically etched to the P-type confinement layer, the ridge waveguide array is vertically etched to the P-face waveguide layer, the tapered waveguide array is vertically etched to the P-type confinement layer, the first leakage groove and the second leakage groove are etched to the N-face waveguide layer, and the cascade coupling region is vertically etched to the P-face waveguide layer.

[0008] As a further improvement of the present invention, in the ridge waveguide array,

[0009] The lateral dimensions of the ridge waveguide are determined by the lateral single-mode cutoff condition get;

[0010] Where W is the ridge waveguide width, λ is the wavelength of free space light, and n eff is the equivalent refractive index of the ridge region, n L is the equivalent refractive index of the remaining confining layer;

[0011] The longitudinal dimension of the ridge waveguide is determined by the longitudinal single-mode cutoff condition get;

[0012] Where d is the ridge waveguide etching depth, λ is the free space light wavelength, and n 1 is the equivalent refractive index of the confining layer, n 2 is the equivalent refractive index of the waveguide layer.

[0013] As a further improvement of the present invention, the width of the ridge waveguide is 4-6 μm, and the etching depth is 2.0-2.3 μm.

[0014] As a further improvement of the present invention, in the tapered waveguide array, the tapered waveguide taper angle should be less than or equal to the fundamental mode diffraction angle, and the fundamental mode diffraction angle is given by θ=λ[2tan -1 (b / (1-b)) 1 / 2 ] / n 3 W got,

[0015]

[0016] Where θ is the fundamental mode diffraction angle, W is the ridge waveguide width, λ is the wavelength of free space light, and n eff-n is the equivalent refractive index when the ridge waveguide width approaches infinity, n eff is the equivalent refractive index when the ridge waveguide width is W, n3 is the bulk refractive index of the P-plane waveguide layer.

[0017] As a further improvement of the present invention, the cone angle of the tapered waveguide is 4.2-5.8°, and the etching depth is 1.5-1.7 μm.

[0018] As a further improvement of the present invention, the lateral dimensions of the first leakage groove include high-order lateral modes in the tapered waveguide feedback light, and the shape of the first leakage groove is a parallelogram with an angle of 60°, a long side of 180 to 220 μm, a short side of 40 to 50 μm, and an etching depth of 2.8 to 3.1 μm.

[0019] As a further improvement of the present invention, the lateral dimensions of the second leakage groove include high-order lateral modes in the feedback light of the cascade coupling zone, and the shape of the second leakage groove is arrow-shaped, with an angle of 60°, a long side of 180 to 220 μm, a short side of 40 to 50 μm, and an etching depth of 2.8 to 3.1 μm.

[0020] As a further improvement of the present invention,

[0021] The insulating layer comprises one of silicon dioxide and silicon nitride;

[0022] The P-side electrode includes one or more of gold, platinum, and titanium;

[0023] The N-side electrode includes one or more of germanium, niobium, and gold.

[0024] The present invention also discloses a method for preparing the enhanced cascade coupled laser chip, comprising:

[0025] Step 1, select an N-type substrate;

[0026] Step 2, epitaxial growth is performed using metal organic compound vapor deposition technology, and an N-type confinement layer, an N-side waveguide layer, an active region, a P-side waveguide layer, a P-type confinement layer and a P-side ohmic contact layer are sequentially grown from bottom to top on the upper surface of the N-type substrate to obtain an epitaxial structure;

[0027] Step 3: using plasma enhanced vapor chemical deposition technology to deposit a layer of silicon dioxide mask on the epitaxial structure;

[0028] Step 4: Using electron beam exposure technology, transfer the on-chip Bragg reflection grating pattern to a silicon dioxide mask;

[0029] Step 5, using inductively coupled plasma dry etching technology to etch the on-chip Bragg reflection grating;

[0030] Step 6: using ultraviolet exposure technology and inductively coupled plasma dry etching technology to etch the ridge waveguide array, the tapered waveguide array, the first leakage groove and the second leakage groove;

[0031] Step 7: using wet etching technology to etch the silicon dioxide mask layer;

[0032] Step 8: using plasma enhanced vapor chemical deposition technology to deposit a silicon dioxide insulating layer;

[0033] Step 9, using photolithography technology to etch the P-side electrode windows of the ridge waveguide array, the tapered waveguide array and the cascade coupling region;

[0034] Step 10: sputtering a P-side electrode on the epitaxial structure using magnetron sputtering technology;

[0035] Step 11, thinning and polishing the N-type substrate;

[0036] Step 12, sputtering an N-side electrode on the back side of the N-type substrate using a magnetron sputtering technique;

[0037] Step 13: cleave, wire bond and package the mutual injection conical coherent array laser chip.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The present invention arranges an on-chip Bragg reflection grating at the rear end of a ridge waveguide array, arranges a first leakage groove on both sides of each ridge waveguide in the ridge waveguide array and close to a tapered waveguide array; arranges a second leakage groove on both sides of each tapered waveguide in the tapered waveguide array and close to a cascade coupling region, thereby improving the selection characteristics of the laser longitudinal mode and the transverse mode, and then obtains a high-power laser beam output through the amplification effect of the tapered waveguide array and the coupling effect of the cascade coupling region, and finally obtains a high-brightness, high-power fundamental mode beam output. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a side view structural diagram of the enhanced cascade coupled laser chip disclosed in the present invention;

[0041] Figure 2 It is a front view structural diagram of the enhanced cascade coupled laser chip disclosed in the present invention;

[0042] Figure 3 This is a top view of the structure of the enhanced cascade coupled laser chip disclosed in the present invention.

[0043] In the figure:

[0044] 1. N-side electrode; 2. N-type substrate; 3. N-type confinement layer; 4. N-side waveguide layer; 5. Active region; 6. P-side waveguide layer; 7. P-type confinement layer; 8. P-side ohmic contact layer; 9. P-side electrode; 10. On-chip Bragg reflection grating; 11. Ridge waveguide array; 12. First leakage groove; 13. Conical waveguide array; 14. Second leakage groove; 15. Cascade coupling region; 16. Insulation layer. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0047] like Figures 1 to 3 As shown, the present invention provides an enhanced cascade coupling laser chip, which includes, from left to right, an on-chip Bragg reflection grating 10, a ridge waveguide array 11, a first leakage groove 12, a tapered waveguide array 13, a second leakage groove 14 and a cascade coupling region 15, which are arranged on the upper surface of the same epitaxial structure. Among them, the on-chip Bragg reflection grating 10 is arranged on the rear end face of the ridge waveguide array 11, and the periods of the on-chip Bragg reflection grating 10, the ridge waveguide array 11 and the tapered waveguide array 13 are consistent; the first leakage groove 12 is arranged on both sides of each ridge waveguide in the ridge waveguide array 11 and close to the tapered waveguide array 13; the second leakage groove 14 is arranged on both sides 13 of each tapered waveguide in the tapered waveguide array and close to the cascade coupling region 15; the cascade coupling region 15 is arranged on the front end face of the tapered waveguide array 13.

[0048] Specific:

[0049] The epitaxial structure of the present invention comprises an N-type confinement layer 3, an N-face waveguide layer 4, an active region 5, a P-face waveguide layer 6, a P-type confinement layer 7, and a P-face ohmic contact layer 8 which are sequentially arranged on the upper surface of an N-type substrate 2 from bottom to top, an N-face electrode 1 is arranged on the lower surface of the N-type substrate 2, an insulating layer 16 and a P-face electrode 9 are formed on the upper surface of the epitaxial structure, and P-face electrode windows are opened at the insulating layers corresponding to the ridge waveguide array 11, the tapered waveguide array 13 and the cascade coupling region 15; wherein the on-chip Bragg reflection grating 10 is vertically etched to the P-type confinement layer 7, the ridge waveguide array 11 is vertically etched to the P-face waveguide layer 6, the tapered waveguide array 13 is vertically etched to the P-type confinement layer 7, the first leakage groove 12 and the second leakage groove 14 are etched to the N-face waveguide layer 4, and the cascade coupling region 15 is vertically etched to the P-face waveguide layer 6.

[0050] The lateral size of the ridge waveguide array 11 of the present invention is determined by the lateral single-mode cutoff condition Where W is the ridge waveguide width, λ is the wavelength of free space light, and n eff is the equivalent refractive index of the ridge region, n L is the equivalent refractive index of the remaining confinement layer. The longitudinal dimension of the ridge waveguide array 11 is determined by the longitudinal single-mode cutoff condition Where d is the ridge waveguide etching depth, λ is the free space light wavelength, n 1 is the equivalent refractive index of the confining layer, n 2 is the equivalent refractive index of the waveguide layer. Preferably, the dimension parameters of the ridge waveguide array 11 are: the ridge waveguide width is 4-6 μm, and the ridge waveguide etching depth is 2.0-2.3 μm.

[0051] The cone angle of the tapered waveguide array 13 of the present invention should be less than or equal to the fundamental mode diffraction angle, and the fundamental mode diffraction angle is given by θ=λ[2tan -1 (b / (1-b)) 1 / 2 ] / n 3 W got, Where θ is the fundamental mode diffraction angle, W is the ridge waveguide width, λ is the wavelength of free space light, and n eff-n is the equivalent refractive index when the ridge waveguide width approaches infinity, n eff is the equivalent refractive index when the ridge waveguide width is W, n 3 is the volume refractive index of the P-plane waveguide layer. Preferably, the parameters of the tapered waveguide array 13 are: a tapered angle of 4.2-5.8°, and an etching depth of 1.5-1.7 μm.

[0052] The lateral dimensions of the first leakage groove 12 of the present invention include the high-order lateral modes in the feedback light of the tapered waveguide array 13, thereby increasing the loss of the high-order modes; the first leakage groove 12 is in the shape of a parallelogram, the internal angles of the parallelogram are 60°, 120°, 60°, and 120°, respectively, the long side is 180-220 μm, the short side is 40-50 μm, and the etching depth is 2.8-3.1 μm.

[0053] The lateral dimensions of the second leakage groove 14 of the present invention include the high-order transverse modes in the feedback light of the cascade coupling region 15, thereby increasing the loss of the high-order modes; the second leakage groove 14 is arrow-shaped, that is, an arrow-shaped shape composed of two mirror-symmetrical parallelograms; the internal angles of each parallelogram are 60°, 120°, 60°, and 120°, respectively, the long side is 180-220μm, the short side is 40-50μm, and the etching depth is 2.8-3.1μm.

[0054] The insulating layer 16 of the present invention includes but is not limited to one of silicon dioxide and silicon nitride; the P-side electrode 9 includes but is not limited to one or more of gold, platinum, and titanium; the N-side electrode 1 includes but is not limited to one or more of germanium, niobium, and gold.

[0055] The present invention provides a method for preparing an enhanced cascade coupled laser chip, comprising:

[0056] Step 1, selecting an N-type substrate 2;

[0057] Step 2, epitaxial growth is performed using metal organic compound vapor deposition technology, and an N-type confinement layer 3, an N-side waveguide layer 4, an active region 5, a P-side waveguide layer 6, a P-type confinement layer 7 and a P-side ohmic contact layer 8 are sequentially grown from bottom to top on the upper surface of the N-type substrate 2 to obtain an epitaxial structure;

[0058] Step 3: using plasma enhanced vapor chemical deposition technology to deposit a layer of silicon dioxide mask on the epitaxial structure;

[0059] Step 4: Using electron beam exposure technology, transfer the on-chip Bragg reflection grating pattern to a silicon dioxide mask;

[0060] Step 5, using inductively coupled plasma dry etching technology to etch the on-chip Bragg reflection grating 10;

[0061] Step 6: using ultraviolet exposure technology and inductively coupled plasma dry etching technology to etch the ridge waveguide array 11, the tapered waveguide array 13, the first leakage groove 12 and the second leakage groove 14;

[0062] Step 7: using wet etching technology to etch the silicon dioxide mask layer;

[0063] Step 8: using plasma enhanced vapor chemical deposition technology to deposit a silicon dioxide insulating layer 16;

[0064] Step 9: using photolithography technology to etch the P-side electrode windows of the ridge waveguide array 11, the tapered waveguide array 13 and the cascade coupling region 15;

[0065] Step 10: sputtering a P-side electrode 9 on the epitaxial structure using magnetron sputtering technology;

[0066] Step 11, thinning and polishing the N-type substrate 2;

[0067] Step 12: sputtering an N-side electrode 1 on the back side of the N-type substrate 2 using magnetron sputtering technology;

[0068] Step 13: cleave, wire bond and package the mutual injection conical coherent array laser chip.

[0069] Example:

[0070] Taking an enhanced cascade coupled laser chip with an operating wavelength of 808 nm as an example, the preparation method thereof includes:

[0071] S1, selecting a GaAs substrate with a thickness of 300 μm to 600 μm as an N-type substrate 2;

[0072] S2. Using metal organic compound vapor deposition technology to perform epitaxial growth on a GaAs substrate to form an epitaxial structure; wherein the epitaxial structure is as follows from bottom to top: the N-type confinement layer 3 is Al 0.52～0.55 Ga 0.48～0.45 As, doping Si concentration is 1.0×10 19 ~1.5×10 19 / cm -3 , with a thickness of 1.0μm to 1.5μm; the N-type waveguide layer 4 is Al 0.35～0.55 Ga 0.65～0.45 As, doping Si concentration is 1.0×10 17 ~1.0×10 18 / cm -3 , with a thickness of 0.4μm to 0.6μm; in the quantum well active region 5, the quantum well is GaAs, with a thickness of 0.004μm, and the quantum barrier layer is Al 0.15 Ga 0.85 As, thickness 0.006μm; P-side waveguide layer 6 is Al 0.35～0.55 Ga 0.65～0.45 As, doping concentration of Be is 1.0×10 17 ~1.0×10 18 / cm -3 , with a thickness of 0.4μm to 0.6μm; the P-type confinement layer 7 is Al 0.52～0.55Ga 0.48～0.45 As, doping concentration of Be is 1.0×10 19 ~1.5×10 19 / cm -3 , with a thickness of 1.0 μm to 1.5 μm; the P-side ohmic contact layer 8 is GaAs, with a Be doping concentration of 1.0×10 19 / cm -3 , thickness is 0.15μm~0.2μm.

[0073] S3. Clean the epitaxial structure with acetone, methanol and isopropanol, blow dry with nitrogen and dry on a hot plate. Use plasma enhanced vapor chemical deposition technology to deposit a layer of 0.4μm thick silicon dioxide as a mask; use electron beam exposure technology to transfer the on-chip Bragg reflection grating pattern to the silicon dioxide mask layer.

[0074] S4. Using inductively coupled plasma dry etching technology, the Bragg reflection grating 10 on the chip is etched with an etching depth of 2.0 to 2.3 μm; using ultraviolet exposure technology and inductively coupled plasma dry etching technology, the ridge waveguide array 11, the tapered waveguide array 13, the first leakage groove 12 and the second leakage groove 14 are etched with depths of 2.0 to 2.3 μm, 1.5 to 1.7 μm and 2.3 to 3.1 μm respectively.

[0075] S5. Use wet etching technology to etch the silicon dioxide mask layer; use plasma enhanced vapor deposition technology to deposit a silicon dioxide insulating layer 16 with a thickness of 0.13 μm.

[0076] S6. Using photolithography technology, etch the P-surface electrode windows of the ridge waveguide array 11, the tapered waveguide array 13 and the cascade coupling region 15, with an etching depth of 0.13 μm.

[0077] S7. Use magnetron sputtering technology to sputter the P-side electrode 9 on the epitaxial structure, and sputter Ti, Pt, and Au in sequence, with thicknesses of 30 nm, 50 nm, and 300 nm, respectively.

[0078] S8. Thinning and polishing the GaAs substrate, and the remaining substrate thickness is 100 μm to 150 μm.

[0079] S9. Use magnetron sputtering technology to sputter an N-side electrode 1 on the back side of the GaAs substrate, and sputter Ge, Ni, and Au in sequence, with thicknesses of 100 nm, 10 nm, and 150 nm, respectively.

[0080] S10, cleaving, wire bonding and packaging the manufactured mutual injection conical coherent array laser chip.

[0081] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An enhanced cascade coupled laser chip, characterized in that: include: An on-chip Bragg reflection grating, a ridge waveguide array, a first leakage groove, a tapered waveguide array, a second leakage groove and a cascade coupling region are sequentially arranged on the upper surface of the same epitaxial structure; The on-chip Bragg reflection grating is arranged on the rear end face of the ridge waveguide array, and the periods of the on-chip Bragg reflection grating, the ridge waveguide array, and the tapered waveguide array are consistent; the first leakage groove is arranged on both sides of each ridge waveguide in the ridge waveguide array and close to the tapered waveguide array; the second leakage groove is arranged on both sides of each tapered waveguide in the tapered waveguide array and close to the cascade coupling region, and the lateral dimension of the second leakage groove includes the high-order transverse mode in the feedback light of the cascade coupling region; the cascade coupling region is arranged on the front end face of the tapered waveguide array.

2. The enhanced cascade coupled laser chip according to claim 1, characterized in that: The epitaxial structure comprises an N-type confinement layer, an N-face waveguide layer, an active region, a P-face waveguide layer, a P-type confinement layer and a P-face ohmic contact layer which are sequentially arranged on the upper surface of an N-type substrate from bottom to top, an N-face electrode is arranged on the lower surface of the N-type substrate, an insulating layer and a P-face electrode are formed on the upper surface of the epitaxial structure, and P-face electrode windows are opened at the insulating layers corresponding to the ridge waveguide array, the tapered waveguide array and the cascade coupling region; wherein the on-chip Bragg reflection grating is vertically etched to the P-type confinement layer, the ridge waveguide array is vertically etched to the P-face waveguide layer, the tapered waveguide array is vertically etched to the P-type confinement layer, the first leakage groove and the second leakage groove are etched to the N-face waveguide layer, and the cascade coupling region is vertically etched to the P-face waveguide layer.

3. The enhanced cascade coupled laser chip according to claim 1, characterized in that: In the ridge waveguide array, The lateral dimensions of the ridge waveguide are determined by the lateral single-mode cutoff condition get; Where W is the ridge waveguide width, λ is the wavelength of free space light, and n eff is the equivalent refractive index of the ridge region, n L is the equivalent refractive index of the remaining confining layer; The longitudinal dimension of the ridge waveguide is determined by the longitudinal single-mode cutoff condition get; Where d is the ridge waveguide etching depth, λ is the free space light wavelength, n1 is the equivalent refractive index of the confinement layer, and n2 is the equivalent refractive index of the waveguide layer.

4. The enhanced cascade coupled laser chip according to claim 3, characterized in that: The width of the ridge waveguide is 4-6 μm, and the etching depth is 2.0-2.3 μm.

5. The enhanced cascade coupled laser chip according to claim 1, characterized in that: In the tapered waveguide array, the tapered waveguide angle should be less than or equal to the fundamental mode diffraction angle, and the fundamental mode diffraction angle is given by θ=λ[2tan -1 (b / (1-b)) 1 / 2 ] / n3W got, Where θ is the fundamental mode diffraction angle, W is the ridge waveguide width, λ is the wavelength of free space light, and n eff-n is the equivalent refractive index when the ridge waveguide width approaches infinity, n eff is the equivalent refractive index when the ridge waveguide width is W, and n3 is the bulk refractive index of the P-plane waveguide layer.

6. The enhanced cascade coupled laser chip according to claim 5, characterized in that: The tapered waveguide has a taper angle of 4.2-5.8° and an etching depth of 1.5-1.7 μm.

7. The enhanced cascade coupled laser chip according to claim 1, characterized in that: The lateral dimensions of the first leakage groove include the high-order lateral modes in the tapered waveguide feedback light. The first leakage groove is in the shape of a parallelogram with an angle of 60°, a long side of 180-220 μm, a short side of 40-50 μm, and an etching depth of 2.8-3.1 μm.

8. The enhanced cascade coupled laser chip according to claim 1, characterized in that: The shape of the second leakage groove is an arrow shape, that is, an arrow shape composed of two mirror-symmetrical parallelograms; the internal angles of each parallelogram are 60°, 120°, 60°, and 120° respectively, the long side is 180-220μm, the short side is 40-50μm, and the etching depth is 2.8-3.1μm.

9. The enhanced cascade coupled laser chip according to claim 2, characterized in that: The insulating layer comprises one of silicon dioxide and silicon nitride; The P-side electrode includes one or more of gold, platinum, and titanium; The N-side electrode includes one or more of germanium, niobium, and gold.

10. A method for preparing an enhanced cascade coupled laser chip according to any one of claims 1 to 9, characterized in that: include: Step 1, select an N-type substrate; Step 2, epitaxial growth is performed using metal organic compound vapor deposition technology, and an N-type confinement layer, an N-side waveguide layer, an active region, a P-side waveguide layer, a P-type confinement layer and a P-side ohmic contact layer are sequentially grown from bottom to top on the upper surface of the N-type substrate to obtain an epitaxial structure; Step 3: using plasma enhanced vapor chemical deposition technology to deposit a layer of silicon dioxide mask on the epitaxial structure; Step 4: Using electron beam exposure technology, transfer the on-chip Bragg reflection grating pattern to a silicon dioxide mask; Step 5, using inductively coupled plasma dry etching technology to etch the on-chip Bragg reflection grating; Step 6: using ultraviolet exposure technology and inductively coupled plasma dry etching technology to etch the ridge waveguide array, the tapered waveguide array, the first leakage groove and the second leakage groove; Step 7: using wet etching technology to etch the silicon dioxide mask layer; Step 8: using plasma enhanced vapor chemical deposition technology to deposit a silicon dioxide insulating layer; Step 9, using photolithography technology to etch the P-side electrode windows of the ridge waveguide array, the tapered waveguide array and the cascade coupling region; Step 10: sputtering a P-side electrode on the epitaxial structure using magnetron sputtering technology; Step 11, thinning and polishing the N-type substrate; Step 12, sputtering an N-side electrode on the back side of the N-type substrate using a magnetron sputtering technique; Step 13: cleave, wire bond and package the mutual injection conical coherent array laser chip.

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