Method, device, electronic equipment and storage medium for layout unit placement testing

Abstract

The embodiments of the present application disclose a method, device, electronic device and storage medium for layout unit placement testing, wherein the layout units to be tested include new layout units and other layout units, and the other layout units include any one of the other new layout units and the existing layout units in the layout unit information library that do not have DRC test problems. The method can obtain all splicing methods between the new layout unit and the other layout units by determining the verification method corresponding to the layout unit to be tested, and then place the layout unit to be tested in the newly created layout according to the verification method and then perform a DRC test. In one test, all possible splicing methods of the layout unit to be tested can be automatically placed and tested without manual placement by the user, thereby avoiding the problem of incomplete testing due to omissions in manual placement, and ensuring the reliability of the layout unit to be tested.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit layout technology, and in particular to a layout unit placement test method, a layout unit placement test device, an electronic device and a computer-readable storage medium. Background Art

[0002] At present, designers usually work in a collaborative mode when designing integrated circuit layouts. The layouts completed by individuals can often only check the DRC (Design Rule Check) issues of the layout units themselves. In order to deal with floorplan layout planning in different situations, after the layout unit design is completed, a new layout will be created to manually place each layout unit to test the layout plan, and then the DRC test will be performed on the laid-out layout.

[0003] In the related art, after completing the layout unit design, the layouts in different directions are usually manually placed according to the current layout plan, and then the DRC test is performed. However, this solution can only ensure that the current layout plan will not cause DRC problems. If the layout plan is changed, it needs to be re-checked. It is difficult to ensure that no DRC problems will occur when the layout units are spliced ​​according to different layout plans, making it difficult to ensure the reliability of the layout unit; and, by manually placing the layouts in different directions and then performing the DRC test, omissions may result in incomplete testing, making it difficult to ensure the reliability of the layout unit. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a method, device, electronic device and computer-readable storage medium for testing layout unit placement, so as to ensure the reliability of the layout unit.

[0005] According to one aspect of an embodiment of the present application, a method for layout unit placement testing is provided, the method comprising: determining a verification method corresponding to a layout unit to be tested; wherein the layout unit to be tested comprises a new layout unit and other layout units, the verification method is used to characterize a splicing method between the new layout unit and other layout units, the other layout units comprise other new layout units and any one of the existing layout units in a layout unit information library that do not have a DRC test problem, the layout unit information library storing a number of layout units; placing the layout unit to be tested in a newly created layout according to the verification method to obtain a layout to be tested; and performing a DRC test on the layout to be tested.

[0006] In another exemplary embodiment, determining the verification method of the layout unit to be tested includes: obtaining the test type corresponding to the layout unit to be tested; when the test type does not require a mutual splicing test between new layout units, determining the verification method is to splice one of the new layout units between two identical existing layout units; when the test type requires a mutual splicing test between new layout units, determining the verification method is to splice one of the layout units to be tested between two identical layout units to be tested.

[0007] In another exemplary embodiment, obtaining the test type corresponding to the layout unit to be tested includes: obtaining attribute information of the new layout unit to obtain an attribute information acquisition result; when the attribute information acquisition result includes all attributes of the new layout unit, determining that the test type is not required to perform mutual splicing test between new layout units; when the attribute information acquisition result does not include all attributes of the new layout unit, determining that the test type is required to perform mutual splicing test between new layout units.

[0008] In another exemplary embodiment, the layout units to be tested are placed in a newly created layout according to the verification method to obtain the layout to be tested, including: determining a placement starting point for a layout unit in the newly created layout; obtaining a unit width of the layout unit to be tested; determining a placement coordinate point of the layout unit to be tested according to the placement starting point of the layout unit and the unit width; and splicing and placing the layout units to be tested in sequence according to the verification method and the placement coordinate points to obtain the layout to be tested.

[0009] In another exemplary embodiment, determining the starting point for placing a layout unit in the newly created layout includes: obtaining a test direction of the layout unit to be tested; and when the test direction is a first direction or a second direction, determining the coordinate origin in the newly created layout as the starting point for placing the layout unit.

[0010] In another exemplary embodiment, determining the starting point for placing a publication unit in the newly created layout includes: obtaining a test direction of the layout unit to be tested; when the test direction includes a first direction and a second direction, determining the first vertex coordinates of a preset corner in the newly created layout as the starting point for placing the layout unit in the first direction, and determining the second vertex coordinates of the preset corner in the newly created layout as the starting point for placing the layout unit in the second direction; wherein the first direction is longitudinal, the second direction is transverse, and the first vertex and the second vertex are two diagonals of the preset corner.

[0011] In another exemplary embodiment, after determining the verification method of the layout unit to be tested, it also includes: comparing the new layout unit with a preset reference layout unit to obtain a comparison result; when the comparison result is that the target parameter of the new layout unit is the same as the target parameter of the preset reference layout unit, placing it according to the verification method; wherein the target parameter includes the layout unit shape and the transistor direction; when the comparison result is that the target parameter of the new layout unit is different from the target parameter of the preset reference layout unit, rotating the new layout unit by a preset angle and then placing it according to the verification method.

[0012] According to one aspect of an embodiment of the present application, a device for layout unit placement test is provided, the device comprising: a determination module, configured to determine a verification method corresponding to a layout unit to be tested; wherein the layout unit to be tested comprises a new layout unit and other layout units, the verification method is used to characterize a splicing method between the new layout unit and other layout units, the other layout units comprise any one of the other new layout units and the existing layout units in a layout unit information library that do not have a DRC test problem, and the layout unit information library stores a plurality of layout units; a placement module, configured to place the layout units to be tested in a newly created layout according to the verification method to obtain a layout to be tested; and a testing module, configured to perform a DRC test on the layout to be tested.

[0013] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: a processor; and a memory for storing one or more programs, which, when the one or more programs are executed by one or more processors, enables the one or more processors to implement the method for layout unit placement testing as described above.

[0014] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor of a computer, the computer executes the method for layout unit placement testing as described above.

[0015] In the technical solution provided in the embodiments of the present application, the layout units to be tested include new layout units and other layout units, and the other layout units include other new layout units and any one of the existing layout units in the layout unit information library that do not have DRC test problems. By determining the verification method corresponding to the layout unit to be tested, all splicing methods between the new layout unit and the other layout units can be obtained, and then the layout units to be tested are placed in the newly created layout according to the verification method, and then the DRC test is performed. In one test, all possible splicing methods of the layout units to be tested can be automatically placed and tested without manual placement by the user, thereby avoiding the problem of incomplete test conditions due to omissions in manual placement, and ensuring the reliability of the layout units to be tested.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 is a flow chart of a layout unit placement test method shown in an exemplary embodiment of the present application;

[0019] Figure 2 yes Figure 1 Step S110 in the illustrated embodiment is a flow chart of a method for determining a verification method corresponding to a layout unit to be tested in an exemplary embodiment;

[0020] Figure 3 yes Figure 1 Step S120 in the illustrated embodiment is a flowchart of a method for obtaining a layout to be tested in an exemplary embodiment;

[0021] Figure 4 is a flow chart of a layout unit placement test method shown in another exemplary embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a graphical user window for performing a method for layout unit placement testing according to an exemplary embodiment of the present application;

[0023] Figure 6 It is an application schematic diagram of the splicing arrangement of the units to be tested in the first direction when only one direction is tested;

[0024] Figure 7 is another application schematic diagram of the splicing arrangement of the units to be tested in the first direction when only one direction is tested;

[0025] Figure 8 is a schematic diagram of a graphical user window for performing a method for layout unit placement testing according to another exemplary embodiment of the present application;

[0026] Fig. 9 It is an application schematic diagram of the splicing arrangement of the units to be tested in the first direction when testing two directions simultaneously;

[0027] Fig.10 It is an application schematic diagram of the splicing arrangement of the units to be tested in the second direction when testing two directions simultaneously;

[0028] Fig.11 is another application schematic diagram of the splicing arrangement of the units to be tested in the first direction when testing two directions simultaneously;

[0029] Fig.12 is another application schematic diagram of the splicing arrangement of the units to be tested in the second direction when testing two directions simultaneously;

[0030] Fig.13 is a structural schematic diagram of a layout unit placement test device shown in an exemplary embodiment of the present application;

[0031] Fig.14 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0032] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that are the same as the present application. Instead, they are only examples of devices and methods that are the same as some aspects of the present application as detailed in the attached claims.

[0033] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in the form of an application program, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0034] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0035] It should be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0036] The following is an introduction and explanation of several terms and background technologies involved in this application:

[0037] Layout unit: In the integrated circuit layout, the layout unit is the basic element that constitutes the physical layout of the chip. They together define the shape, area and position of each hardware unit on the chip. Among them, the layout unit in this application is the IO unit (Input / Output unit).

[0038] The IO unit usually consists of the following parts: IO PAD (chip pin processing module), ESD (Electrostatic Discharge) protection circuit, level conversion circuit and drive circuit. IO PAD is the physical interface between the IO unit and the outside, including the pad (PAD) and its surrounding circuits, power lines and ground lines. The pad is used to connect the chip to the package socket with gold wire, while the circuit part is responsible for signal conversion and isolation. The ESD protection circuit is to prevent electrostatic discharge from damaging the internal circuit of the chip. The ESD protection circuit can quickly conduct the charge during static electricity shock, thereby protecting the internal circuit from damage. The level conversion circuit is used to achieve level conversion through the level conversion circuit when the signal level of the internal circuit of the chip is inconsistent with the external circuit to ensure the correct transmission of the signal. The drive circuit is to improve the driving ability of the signal. The drive circuit can amplify the signal to drive external loads, such as other components on the PCB board.

[0039] DRC (Design Rule Check) test: DRC testing can prevent manufacturing defects, optimize design quality, improve production yield and standardize design processes. DRC testing is usually performed by professional EDA (Electronic Design Automation) software, such as Cadence Virtuoso, Mentor Graphics Calibre or Altium Designer. These tools can read design files (such as GDSII or ODB++ format) and the rule sets defined in PDK (Process Design Kit), automatically check, and generate reports to indicate where the rules are violated so that designers can make corrections.

[0040] DRC inspection usually includes the following aspects: minimum spacing inspection, minimum feature size inspection, layer alignment inspection, through-hole and conductor spacing inspection, and trace width and spacing inspection.

[0041] Among them, the minimum spacing check is used to ensure that there is enough space between circuit components and wires to prevent short circuits; the minimum feature size check is used to ensure that any geometric shape in the design is not smaller than the minimum size supported by the process; the inter-layer alignment check is used to verify whether the alignment between different metal layers or mask layers meets the requirements; the spacing check between vias and conductors is used to ensure that there is enough insulation area around the vias to avoid electrical problems; the trace width and spacing is used to check whether all wires meet the width and minimum spacing requirements between adjacent wires.

[0042] In related technologies, after completing the layout unit design, the layouts in different directions are usually manually placed according to the current layout plan, and then DRC testing is performed. However, layout units below 32nm generally have two sets of layouts, one in the EW (east-west) direction and the other in the NS (north-south) direction. This means that layout personnel need to manually place and test the layouts in two directions, which is an extremely time-consuming process.

[0043] Moreover, on the one hand, in the related art, the layout personnel manually simulate the placement test. If there are many layout units, the situation requiring simulation test will become more complicated, and the workload will increase accordingly. Manual simulation test may also miss some items, resulting in incomplete test results. On the other hand, in the related art, the layout units are only placed according to the existing current layout plan, and DRC test is performed after the placement is completed. The layout units that do not meet the DRC are modified according to the test results. However, this solution can only ensure that the splicing of the layout units under the current layout plan will not cause DRC problems. If the layout plan changes, the splicing and placement must be re-performed, which means that it is difficult to ensure that the splicing of the same layout unit in different layout plans will not cause problems, making it difficult to ensure the reliability of the layout unit.

[0044] Based on this, in order to ensure the reliability of the layout unit, the embodiments of the present application propose a method, device, electronic device and computer-readable storage medium for layout unit placement testing.

[0045] The layout unit placement test method in this application is implemented through a SKILL script, and the corresponding API (Application Programming Interface) function dbCreateInstByMasterName is configured in the SKILL script.

[0046] This API function includes the following main parameters, such as cv, libName, cellName, viewName, instName, Origin and Orient.

[0047] Among them, cv is used to represent the view ID of the new layout being edited. This parameter is used to tell the function in which view to execute the API; the view ID of the new layout can be directly obtained through the preset function geGetEditCellView().

[0048] libName is the name of the information library where the cell to be placed is located, and the parameter is in string format ("abc"); cellName is the cell name of the layout cell to be tested, and the parameter is in string format ("X"); viewName is the view name of the layout cell to be tested; libName, cellName and viewName can be directly entered through the input bar of the graphical user window or selected and entered through the library browser Browse.

[0049] instName is the device name that will be used to place the layout unit in the newly created layout. This parameter can be set to nil, which means that no explicit device name is given. The API will give a unique name to the newly created device because this parameter is irrelevant to this method.

[0050] Origin is the reference coordinate point for placing layout units. The selected coordinate point is the lower left corner of the border BORDER of the layout (the preset corners and layout units in this application are both layouts) (generally, when the layout is completed, a rectangle will be drawn in the layout with the BORDER layer to frame other layers inside, which is defined as the boundary of the layout). When placing layout units in the first direction, that is, the NS direction, the vertical coordinate y=0 of the reference coordinate (x, y) is placed, and the horizontal coordinate x is completed through coordinate calculation. When placing layout units in the second direction, that is, the EW direction, the horizontal coordinate x=0 of the reference coordinate is placed, and the vertical coordinate y is completed through coordinate calculation.

[0051] Orient is the direction of placing the layout unit. The direction parameter is in string format, mainly including "R0" for no rotation, "R90" for 90 degrees counterclockwise rotation, "R180" for 180 degrees counterclockwise rotation, "R270" for 270 degrees counterclockwise rotation, "MX" for symmetry about the X axis, "MY" for symmetry about the Y axis, "MXR90" for symmetry about the X axis first and then rotate 90 degrees counterclockwise, and "MYR90" for symmetry about the Y axis first and then rotate 90 degrees counterclockwise. Among them, MX and MY are symmetric about X and Y. Taking the IO layout as an example, the first direction, that is, when the layout unit in the NS direction is placed horizontally, the direction is "R0", and the second direction, that is, when the layout unit in the EW direction is placed along the Y axis, the direction is also "R0". In the above two cases, there is no need to rotate the layout unit. There is also a special case that in the layout unit below 32nm, the layout unit in the EW direction is obtained by modifying the layout unit in the NS direction. For example, after rotating some transistors in the layout unit in the NS direction by 90 degrees, the layout unit in the EW direction is obtained. At this time, the two are the same in terms of the overall appearance of the layout, but some transistors inside have different directions. Therefore, in order to meet the structure in the floorplan layout planning, when placing the layout unit in the EW direction, it is necessary to rotate the layout unit in the EW direction by 90 degrees before placing it, so that the direction of the transistor in the layout unit in the EW direction after rotation is the same as the direction of the transistor in the layout unit in the NS direction, so as to meet the DRC requirements.

[0052] The following is a description of the layout unit placement test method provided in the embodiments of the present application.

[0053] See also Figure 1 , Figure 11 is a flow chart of a layout unit placement test method shown in an exemplary embodiment of the present application. The method can be applied to electronic devices, including but not limited to tablet computers, personal computers, or computers. In this embodiment, the electronic device can be a computer.

[0054] The following describes in detail the layout unit placement test method proposed in the embodiment of the present application using a computer as a specific execution subject.

[0055] like Figure 1 As shown, in an exemplary embodiment, the method for layout unit placement testing includes at least steps S110 to S130, which are described in detail as follows:

[0056] Step S110, determining the verification method corresponding to the layout unit to be tested.

[0057] In the embodiment of the present application, the layout unit to be tested includes a new layout unit and other layout units, and the verification method is used to characterize the splicing method between the new layout unit and other layout units. Other layout units include any one of the other new layout units and the existing layout units. The existing layout unit is a layout unit in the layout unit information library that does not have a DRC test problem, and the layout unit information library stores several layout units. A plurality of layout unit information libraries can be set in the computer, and different layout units can be stored in different layout unit information libraries.

[0058] It should be understood that, when there are multiple new layout units, other new layout units include the new layout unit and other new layout units except the new layout unit. When there is only one new layout unit, there are no other new layout units.

[0059] For example, the splicing methods include the splicing method between a single new layout unit and multiple existing layout units, the splicing method between multiple new layout units and multiple existing layout units, the splicing method between the same new layout units, and the splicing method between different new layout units.

[0060] Step S120, placing the layout units to be tested in the newly created layout according to the verification method to obtain the layout to be tested.

[0061] It should be understood that when the layout units to be tested are placed in the newly created layout, each layout unit to be tested must be spliced ​​with each other, so as to ensure that other DRC problems are not easily caused during testing. Since the verification method includes all possible splicing methods between the new layout unit and other layout units, the layout units to be tested are placed through this verification method, so that all possible splicing methods between the layout units to be tested can be placed.

[0062] Step S130, performing a DRC test on the layout to be tested.

[0063] In the embodiment of the present application, since the arranged layout to be tested can include all splicing methods between the units of the layout to be tested, when the layout to be tested is subjected to DRC testing, all possible splicing methods of the layout units to be tested can be automatically arranged and tested in one test without the need for manual arrangement by the user, thereby avoiding the problem of incomplete testing due to omissions in manual arrangement, and ensuring the reliability of the layout units to be tested.

[0064] See also Figure 2 , Figure 2 yes Figure 1 Step S110 in the illustrated embodiment is a flowchart of a method for determining a verification method corresponding to a layout unit to be tested in an exemplary embodiment, which at least includes steps S210 to S230, which are described in detail as follows:

[0065] Step S210, obtaining the test type corresponding to the layout unit to be tested.

[0066] In the embodiment of the present application, the layout unit to be tested includes new layout units and other layout units, and other layout units include other new layout units and existing layout units. The test type is used to indicate whether this DRC test requires a mutual splicing test between new layout units.

[0067] In some implementations, the test type corresponding to the layout unit to be tested may be obtained through the following process:

[0068] Step S211, acquiring the attribute information of the new layout unit to obtain an attribute information acquisition result.

[0069] Step S212: when the attribute information acquisition result includes all attributes of the new layout unit, determine the test type as not needing to perform a mutual splicing test between the new layout units.

[0070] Step S213: when the attribute information acquisition result does not include all the attributes of the new layout unit, determine that the test type is to perform a mutual splicing test between the new layout units.

[0071] Among them, all attribute information of the new layout unit includes the name of the information library used to store the new layout unit, the unit name of the new layout unit and the view name of the new layout unit.

[0072] Exemplarily, in an embodiment of the present application, when the computer obtains all the properties of the new layout unit, such as the library name, unit name and view name, it considers that the test type is that there is no need to perform mutual splicing test between the new layout units.

[0073] If the computer does not obtain the properties of the new layout unit, or only obtains some of the properties of the new layout unit, such as one or two of the information library name, unit name and view name, it is considered that the test type requires mutual splicing test between new layout units.

[0074] Step S220, when the test type is that no mutual splicing test between new layout units is required, determine the verification method as splicing a new layout unit between two identical existing layout units.

[0075] For example, when the new layout unit is X and the existing layout units are A, B and C, when all the attribute information of the new layout unit X is obtained, it is considered that the test type is that there is no need to perform mutual splicing test between the new layout units. At this time, the verification method is to splice a new layout unit between two identical existing layout units. For example, the verification method includes "AXA", "BXB", and "CXC". Since the existing layout units are layout units that do not have DRC problems, there is no need to perform splicing tests between the existing layout units, and the existing layout units can be safely connected. After all possible splicing methods are spliced, it is "AXABXBCXC". In this way, by splicing a new layout unit between different existing layout units, it can be tested at one time whether the new layout unit will cause DRC problems when connected with all the existing layout units.

[0076] Step S230, when the test type is to perform a mutual splicing test between new layout units, determine the verification method as splicing a layout unit to be tested between two identical layout units to be tested.

[0077] It can be understood that in the embodiment of the present application, the layout units to be tested include new layout units and other layout units, and the other layout units include other new layout units and existing layout units.

[0078] Then, splicing a layout unit to be tested between two identical layout units to be tested includes the following different situations:

[0079] Case 1: splicing an identical new layout unit between two identical new layout units, that is, splicing three new layout units with each other; for example, the new layout units include X and Y, then the splicing method includes "XXX" and "YYY";

[0080] Case 2: splicing an identical existing layout unit between two identical existing layout units, that is, splicing three existing layout units with each other; for example, the existing layout units include A and B, then the splicing method includes "AAA" and "BBB";

[0081] Case 3: splicing another new layout unit between two identical new layout units; for example, if the new layout units are X and Y, the splicing methods include "XYX" and "YXY";

[0082] Case 4: splicing an existing layout unit between two identical existing layout units; for example, if the new layout units are A and B, the splicing methods include "ABA" and "BAB";

[0083] Case 5: Splice an existing layout unit between two identical new layout units; for example, the new layout units are X and Y, and the existing layout units are A and B, then the splicing methods include "XAX", "XBX", "YAY" and "YBY".

[0084] Case 6: Splice a new layout unit between two identical existing layout units; for example, the new layout units are X and Y, and the existing layout units are A and B, then the splicing methods include "AXA", "BXB", "AYA" and "BYB".

[0085] For example, when the new layout units are X and Y, and the existing layout units are A and B, if all the attribute information of the new layout units cannot be obtained at this time, the test type is that the mutual splicing test between the new layout units is required, and the corresponding verification method is to splice a layout unit to be tested between two identical layout units to be tested. Then the verification method includes "XXX", "XYX", "XAX", "XBX", "YXY", "YYY", "YAY", "YBY", "AXA", "AYA", "AAA", "ABA", "BXB", "BYB", "BAB" and "BBB".

[0086] Therefore, compared with the case where the test type does not require the mutual splicing test between new layout units, the case where the test type requires the mutual splicing test between new layout units will include more splicing situations such as "XXX" and "YYY". Therefore, the test can be more comprehensive, avoiding omissions caused by manual placement, thereby improving the reliability of new layout units.

[0087] See also Figure 3 , Figure 3 yes Figure 1 Step S120 in the illustrated embodiment is a flowchart of a method for obtaining a layout to be tested in an exemplary embodiment, which at least includes steps S310 to S340, which are described in detail as follows:

[0088] Step S310, determining the starting point for placing the publication drawing unit in the newly created layout.

[0089] It should be understood that the layout unit placement test method in the embodiment of the present application can be used to test layout units in one direction or two directions at the same time, and different test directions will result in different placement starting points of the layout units. This is because when it is necessary to test layout units in two directions, it is necessary to connect the layout units in the two directions through the preset corners in the new layout, so as to avoid causing other DRC problems as much as possible. When testing layout units in one direction, there is no need to preset corners.

[0090] Exemplarily, determining the starting point for placing a layout unit in a newly created layout includes: obtaining a test direction of the layout unit to be tested; and when the test direction is a first direction or a second direction, determining the coordinate origin in the newly created layout as the starting point for placing the layout unit.

[0091] The first direction is the longitudinal direction, ie, the NS direction, and the second direction is the transverse direction, ie, the EW direction.

[0092] In an embodiment of the present application, the test direction of the layout unit to be tested can be determined in the following manner, including: detecting whether the user places a preset corner in the newly created layout; if it is detected that the user places the preset corner in the newly created layout, determining that the test direction includes a first direction and a second direction; if it is detected that the user does not place the preset corner in the newly created layout, determining that the test direction is the first direction or the second direction.

[0093] Exemplarily, determining the placement starting point of the layout unit in the newly created layout includes: obtaining the test direction of the layout unit to be tested; when the test direction includes the first direction and the second direction, determining the first vertex coordinate of the preset corner in the newly created layout as the placement starting point of the layout unit in the first direction, and determining the second vertex coordinate of the preset corner in the newly created layout as the placement starting point of the layout unit in the second direction. In this way, by connecting the layout units in two directions through the preset corner, it is possible to simultaneously test the layout units in two directions, thereby improving the test efficiency.

[0094] The first direction is the longitudinal direction, i.e., the NS direction, the second direction is the transverse direction, i.e., the EW direction, the preset corner is a square, and the first vertex and the second vertex are two diagonals of the preset corner. In some embodiments, the coordinates of the first vertex are the coordinates of the lower right corner of the preset corner, and the coordinates of the second vertex are the coordinates of the upper left corner of the preset corner.

[0095] Step S320, obtaining the cell width of the layout cell to be tested.

[0096] It can be understood that when other layout units are other new layout units, it is necessary to obtain the unit widths of the new layout units and other new layout units; when other layout units are existing layout units, it is necessary to obtain the widths of the new layout units and the existing layout units.

[0097] In some embodiments, the existing layout units are filtered in the following manner: the user inputs the unit name of the existing layout unit to obtain a target layout unit set, and the existing layout units in the target layout unit set are arranged in a preset order. The preset order is the order in which the user filters the existing layout units. For example, if the user's filtering order is the existing layout units ABCD, the existing layout units in the target layout unit set are arranged in this order.

[0098] In some embodiments, the shape of the layout unit is generally a rectangle, and the hierarchical information table of the layout unit to be tested is captured through a preset function to obtain a shape coordinate table of the layout unit to be tested; wherein the shape coordinate table includes the horizontal coordinate of the lower left corner and the horizontal coordinate of the upper right corner of the layout unit to be tested, and the difference between the horizontal coordinate of the lower left corner and the horizontal coordinate of the upper right corner is determined as the unit width.

[0099] For example, the dbid (memory address ID, which contains the layer information of BORDER, bBOX, etc.) of the BORDER boundary layer is obtained through the preset function dbShapeQuery, and then the bBOX of the BORDER boundary is obtained through dbid->bBOX (bBOX is a list of the lower left corner coordinates and upper right corner coordinates of the shape graphics of the unit to be tested), and the horizontal coordinates of the lower left corner (usually 0, because the completed unit to be tested generally needs to draw the BORDER and put it at the origin of the coordinates) and the upper right corner of the layout unit in the list are obtained through commands such as car / cdr. The horizontal coordinate, the difference between the two is the width of the layout unit to be tested in the first direction. The width of the layout unit to be tested in the second direction is the difference between the upper right corner ordinate and the lower left corner ordinate of the layout unit in the list. Among them, there is a parameter in the preset function dbShapeQuery for grabbing the layer information list ("layer name" and "drawing"), because the BORDER needs to be grabbed here, and the name of the BORDER is different due to different process types, and the parameter will change according to the process type. The process types in the embodiments of the present application include SMIC Semiconductor Manufacturing International Corporation and TSMC Taiwan Semiconductor Manufacturing Co., Ltd.

[0100] Step S330, determining the placement coordinate point of the layout unit to be tested according to the layout unit placement starting point and the unit width.

[0101] It can be understood that in the embodiment of the present application, when the test direction is the first direction, i.e., the NS direction, the ordinates of the placement coordinate points of each unit to be tested are all 0, and the horizontal coordinates are spaced apart by one unit width. When the test direction is the second direction, i.e., the EW direction, the horizontal coordinates of the placement coordinate points of each unit to be tested are all 0, and the vertical coordinates are spaced apart by one unit width.

[0102] When the verification method is to splice a new layout unit between two identical existing layout units, for example, the existing layout unit is A, the new layout unit is X, that is, the splicing method is "AXA", the unit width of the existing layout unit A is IOwidth, the IO width of the new layout unit X is IOwidth_t, and the test direction is the first direction, that is, the NS direction, then the placement coordinate point of the existing layout unit A in the first layout unit is pointx1, the placement coordinate point of the new layout unit X in the second layout unit is pointx2, and the placement coordinate point of the existing layout unit A in the third layout unit is pointx3. Among them, pointx2=plus(pointx1 IOwidth_t), that is, pointx2 is the sum of pointx1 and the unit width IOwidth_t of the new layout unit X, and pointx3=plus(pointx2 IOwidth), that is, pointx2 is the sum of the unit width IOwidth of the existing layout unit A.

[0103] It can be seen that the sum of the horizontal coordinate of the coordinate point of the first unit to be tested and the unit width of the second unit to be tested is the horizontal coordinate of the coordinate point of the second unit to be tested. Similarly, the horizontal coordinate of the third unit to be tested can be determined; thus, a cycle of coordinate calculation of the units to be tested is completed.

[0104] When the verification method is to splice a layout unit to be tested between two identical layout units to be tested, for example, the existing layout units are A and B, and the new layout units are X and Y, that is, the splicing method is "AAA, ABA, AXA and AYA", "BAB, BBB, BXB and BYB", "XAX, XBX, XXX and XYX", "YAY, YBY, YXY and YYY".

[0105] This verification method requires two layers of loop traversal to complete. The first layer of loop is (cells cellselects), and the second layer of loop is (cellx cellselsects). Cells is used to represent two identical layout units to be tested, and cellx is used to represent the middle layout unit to be tested.

[0106] In the second loop: first, verify that the method is the same as when a new layout unit is spliced ​​between two identical existing layout units, and obtain the width of the new layout unit and the width of the existing layout unit respectively. Then, create a cell through the preset function dbCreateInstByMasterName (cv TestLib cells "layout" nil list (pointx10) "R0"), and then calculate the width of pointx2 = pointx1 + cells to calculate the horizontal coordinate of the middle layout unit to be tested, and then create a new layout unit through dbCreateInstByMasterName (cv TestLib cellx "layout" nillist (pointx20) "R0"), and then calculate pointx3 = pointx2 + the width of the middle cellx, and then create a cell through the preset function dbCreateInstByMasterName (cv TestLib cells "layout" nil list (pointx30) "R0"). In this way, the arrangement of cells / cellx / cells is completed. However, these operations are written in the second-level loop. In this way, the cells remain unchanged and cellx is traversed in a loop. When the second-level loop is completed once, for example, cellselects includes four ABXY. When the traversal of the cells is completed, that is, the arrangement of AAA / ABA / AXA / AYA is completed, the cells will be replaced by another cell (B, X or Y). In this way, when the traversal of the first-level loop is also completed, the cell arrangement is completed, such as AAA / ABA / AXA / AYA, BAB / BBB / BXB / BYB, XAX / XBX / XXX / XYX, YAY / YBY / YXY / YYY.

[0107] The above is how to realize the placement of the layout units to be tested in the two verification methods in the first direction, that is, the NS direction. As for the second direction, that is, the placement in the EW direction, the difference from the NS direction is the difference in coordinates. In the EW direction, the horizontal coordinate in the above algorithm needs to be replaced by the vertical coordinate, and the calculation method of the corresponding unit width IOwidth becomes the difference between the vertical coordinate of the upper right corner and the vertical coordinate of the lower left corner.

[0108] Step S340 , splicing and placing the layout units to be tested in sequence according to the verification method and the placement coordinate points to obtain the layout to be tested.

[0109] It is understandable that if the test direction includes only one direction, that is, the first direction or the second direction, the verification method is to splice a new layout unit between two identical existing layout units. In addition to the new layout unit X and the existing layout unit A, if the selected existing layout units also include multiple existing layout units such as B, C, and D, they are arranged in the preset order, that is, the order in which the user selects the existing layout units. For example, splicing and arranging are performed in the order of AXABXBCXCDXD, and the layout to be tested is obtained after the arrangement is completed.

[0110] If the test direction includes two directions, namely the first direction and the second direction, the units of the existing layout are arranged in the first direction in the order in which the user selects them. For example, they are arranged in the order of AXABXBCXCDXD, and then arranged in the same way in the second direction. After the arrangement is completed, the layout to be tested is obtained.

[0111] In another exemplary embodiment, Figure 4 As shown, after determining the verification method of the layout unit to be tested, the layout unit placement test method is Figure 1 Based on the embodiment shown, steps S410 to S430 are also included, which are described in detail as follows:

[0112] Step S410, comparing the new layout unit with the preset reference layout unit to obtain a comparison result.

[0113] In an embodiment of the present application, preset reference layout units of multiple new layout units can be pre-set, so as to facilitate comparison by users without manual comparison, thereby improving the degree of automation.

[0114] Step S420, when the comparison result shows that the target parameters of the new layout unit are the same as the target parameters of the preset reference layout unit, the layout is arranged according to the verification method; wherein the target parameters include the layout unit shape and the transistor direction.

[0115] Step S430: If the comparison result shows that the target parameter of the new layout unit is different from the target parameter of the preset reference layout unit, the new layout unit is rotated by a preset angle and then placed according to the verification method. The preset angle is 90 degrees and the rotation direction is counterclockwise by default.

[0116] In the embodiment of the present application, due to the different layout unit shapes and transistor orientations, the new layout unit needs to be rotated by a preset angle before it can be used. Therefore, when performing a layout unit placement test, a comparison is required so that the layout unit can be placed correctly during placement.

[0117] It should be noted that the relevant step contents in the embodiments of the present application are consistent with the corresponding step contents recorded in the aforementioned embodiments. Therefore, for the detailed description of these steps, please refer to the records in the aforementioned embodiments, and the embodiments of the present application will not be repeated here.

[0118] Combination Figures 5 and 6 As shown, the corresponding verification method is to splice a new layout unit between two identical existing layout units, where: Figure 5 is a schematic diagram of a graphical user window for performing a layout unit placement test method according to an exemplary embodiment of the present application, Figure 6 It is an application diagram of the splicing and placement of the units to be tested in the first direction when only one direction is tested. The graphical user window includes NewIOLib input bar, NewIOCell input bar, NewIOView input bar, TestIOLib input bar, Search input bar, TestCells display box, CornerLibrary input bar, CornerCell input bar, CornerView input bar, FD process type selection, SelectedCells display box, +ALL add button, -ALL remove button, ==> add button, <== remove button, PlaceCorner button, PlaceEW button, PlaceEWMXR90 button and PlaceNS button.

[0119] The NewIOLib input field is used to input the name of the information library storing the new layout unit.

[0120] The NewIOCell input field is used to enter the cell name of the new layout cell.

[0121] The NewIOView input bar is used to input the view name of the new layout unit. The user can directly input the library name, unit name and view name through this input bar, or browse and select the corresponding library name, unit name and view name through the Browse button. The input bar of NewIOLib, NewIOCell and NewIOView is implemented by the preset function hiCreateStringField, and the callback function callback is "ddsUpdateSyncWithForm()".

[0122] TestIOLib is used to input the name of the library that stores the existing layout units. It can be input by the user or selected through the Browse button. The difference is that the callback function of the Browse button is "ddsSyncWithForm (form 'browse 'TestLibName)".

[0123] The Search input bar is used to input the cell name of an existing layout cell. The search function of the Search input bar creates a text input box through the preset function hiCreateStringField, obtains the content of the input box through the script, and uses the preset function rexMatchList() to filter the existing layout cells in TestIOLib by keywords. The Refresh button is implemented by the preset function hiCreateFormButton. The callback function callback of the Serach input bar is the same as the callback function callback of the Refresh button. When you click anywhere outside the Serach input box or click the Refresh button, you can execute the getcelllist() function. The getcelllist() function is a custom function for obtaining a list of layout cell names. If the input box of the Serach input bar is empty, that is, there is no keyword, the cell names of all existing layout cells in TestIOLib will be listed in the display box below. If a keyword is entered, it will be filtered by the preset function rexMatchList(), and the filtered ones will be listed in the TestCells window below for subsequent selection.

[0124] TestCells is a display box for all layout cells to be tested. After the user selects a new layout cell to be tested, such as X_NS, the new layout cell X_NS is displayed in the TestCells display box. Then the user selects several target layout cells arranged in a preset order from the existing layout cells stored in TestIOLib. The user can enter the library name of the existing layout cell in the TestIOLib input bar, or browse and select the corresponding library name through the Browse button.

[0125] For example, the user can enter the target layout unit names D_NS, C_NS, B_NS and A_NS in the Search input bar. After the user enters, click the Refresh button to display D_NS, C_NS, B_NS and A_NS in the TestCells display box in sequence. Alternatively, the user can directly enter " _NS" to filter out all target layout units with the suffix "_NS". Among them, the display box is realized by the preset function hiCreateListBoxField. The parameter choices in this function is the content in the selection list, that is, the unit name of the layout unit to be tested. Different contents can be displayed by modifying the parameter choices.

[0126] The CornerLibrary input field is used to input the name of the information library of the preset corner. The name of the information library of the preset corner can be input manually by the user, or the corresponding information library name can be browsed and selected through the Browse button.

[0127] The CornerCell input field is used to enter the cell name of the preset corner.

[0128] The CornerView input field is used to enter the view name of the preset corner.

[0129] The FD process type options include TSMC and SMIC. It is understandable that because different processes have different definitions of the name of the BORDER boundary layer, in order to adapt to more processes, the process type option is added. This function is a single selection implemented by the preset function hiCreateRadioField(). Different script contents are executed according to the selection here.

[0130] The SelectedCells display box is used to display the layout cells to be tested that have been selected by the user.

[0131] The +ALL add button is used to add all layout cells to be tested in TestCells to the SelectedCells display box.

[0132] The -ALL remove button is used to remove all layout cells to be tested in the SelectedCells display box.

[0133] ==>The Add button is used to add the layout cells to be tested selected in TestCells to the SelectedCells display box.

[0134] <==The remove button is used to remove the selected layout unit to be tested in the SelectedCells display box. The above addition and removal are realized by the callback function callback in the preset function hiCreateFormButton. The function in the callback function callback is fictButton_CB(), which is also a custom function. Press the corresponding button to trigger fictButton_CB() and set different parameters in the brackets. The execution of the custom function produces corresponding results according to the different parameters input after the button is triggered, thereby realizing the corresponding addition or removal function.

[0135] The PlaceCorner button is used to place a preset corner in a new layout.

[0136] The PlaceNS button is used to place the layout units to be tested in the first direction.

[0137] The PlaceEW button is used to place the layout units to be tested in the second direction.

[0138] The PlaceEWMXR90 button is used to place the layout unit to be tested in the second direction symmetrically about the X axis and then counterclockwise at 90 degrees. The above placement function can execute different functions through the callback function callback of the preset function hiCreateFormButton, thereby completing the placement of the layout unit to be tested and the preset corner.

[0139] Figure 6 In the , the user can click the "==>" add button to add the selected layout cells D_NS, C_NS, B_NS and A_NS in TestCells to the SelectedCells display box, and then click the PlaceNS button to place the layout cells to be tested in the first direction. After the placement is completed, the layout cells to be tested in the first direction are as follows: Figure 6 As shown in the lower right corner, arrange them according to the arrangement of DXDCXCBXBAXA.

[0140] Combination Figure 7 As shown, the corresponding verification method is to splice a layout unit to be tested in two identical layout units to be tested, wherein, Figure 7 This is another application diagram of the splicing arrangement of the units to be tested in the first direction when only one direction is tested. Figure 7 In the Figure 5 Filter out the layout units to be tested in the same way as in the above: D_NS, C_NS, B_NS and A_NS are displayed in the TestCells display box. Click the "==>" add button to add the layout units to be tested D_NS, C_NS, B_NS and A_NS selected in TestCells to the SelectedCells display box. Then click the PlaceNS button to place the layout units to be tested in the first direction. After the placement is completed, the layout units to be tested in the first direction are as follows: Figure 6 As shown in the lower right corner, it is arranged according to the arrangement of DDDDCDDBDDADCDCCCCCBCCACBDBBCBBBBBABADAACAABAAA.

[0141] Combination Figures 8 to 10 As shown, the corresponding verification method is to splice a new layout unit between two identical existing layout units, where: Figure 8 is a schematic diagram of a graphical user window of a method for performing layout unit placement testing according to another exemplary embodiment of the present application, Fig. 9This is an application diagram of the splicing arrangement of the units to be tested in the first direction when testing two directions at the same time. Fig.10 It is an application schematic diagram of the splicing arrangement of the units to be tested in the second direction when testing two directions at the same time.

[0142] Figure 8 In the GUI, use the PlaceCorner button in the graphical user window to place preset corners in the new layout to connect the units to be tested in two directions, such as Figure 8 Shown in the lower right corner. Fig. 9 After the preset corners are placed, Figure 5 In the same way as in the above, the layout cells to be tested are selected from the information library: the new layout cell X_NS, the existing layout cells D_NS, C_NS, B_NS and A_NS are displayed in the TestCells display box, and then the "==>" add button is clicked to add the layout cells D_NS, C_NS, B_NS and A_NS to be tested in TestCells to the SelectedCells display box, and then the PlaceNS button is clicked to place the layout cells to be tested in the first direction. The layout cells after placement are as follows: Fig. 9 Shown in the lower right corner. Fig.10 In the first direction, after the layout units to be tested are placed, Figure 5 In the same way as in , the layout units to be tested are selected from the information library: the existing layout units D_EW, C_EW, B_EW and A_EW, the new layout unit X_EW is displayed in the TestCells display box, and then by clicking the "==>" add button, the layout units D_EW, C_EW, B_EW and A_EW selected in TestCells are added to the SelectedCells display box, and finally by clicking the PlaceEW button, the layout units to be tested in the second direction are placed, thus completing the placement of the layout units to be tested in two directions. The layout units that have been placed are shown in the figure below. Fig.10 Shown in the lower right corner.

[0143] Combination Figure 11 to Figure 12 As shown, the corresponding verification method is to splice a layout unit to be tested between two identical layout units to be tested, wherein, Fig.11 This is another application diagram of the splicing arrangement of the units to be tested in the first direction when testing two directions at the same time. Fig.12 This is another application schematic diagram of the splicing arrangement of the units to be tested in the second direction when testing two directions at the same time.

[0144] Fig.11In the GUI, first place the preset corners in the new layout by using the PlaceCorner button in the graphical user window to connect the units to be tested in two directions. Figure 5 Filter out the layout units to be tested in the same way as in the above: D_NS, C_NS, B_NS and A_NS are displayed in the TestCells display box. Click the "==>" add button to add the layout units to be tested D_NS, C_NS, B_NS and A_NS selected in TestCells to the SelectedCells display box. Then click the PlaceNS button to place the layout units to be tested in the first direction. After the placement is completed, the layout units to be tested in the first direction are as follows: Fig.11 As shown in the lower right corner:

[0145] Arrange it in the manner of DDDDCDDBDDADCDCCCCCBCCACBDBBCBBBBBABADAACAABAAA. Fig.12 In the example, after the layout units to be tested in the first direction are placed, D_EW, C_EW, B_EW and A_EW are selected from the information library in the same way, and X_EW is displayed in the display box of TestCells. Then, by clicking the "==>" add button, the layout units D_EW, C_EW, B_EW and A_EW selected in TestCells are added to the display box of SelectedCells. Finally, by clicking the PlaceEW button, the layout units to be tested in the second direction are placed, thereby completing the placement of the layout units to be tested in the two directions. The layout units after placement are shown in FIG. Fig.12 Shown in the lower right corner.

[0146] Combination Fig.13 As shown, Fig.13 It is a structural diagram of a layout unit placement test device shown in an exemplary embodiment of the present application, and the layout unit placement test device includes: a determination module 1310, a placement module 1320 and a test module 1330. The determination module 1310 is configured to determine the verification method corresponding to the layout unit to be tested. Among them, the layout unit to be tested includes new layout units and other layout units, and the verification method is used to characterize the splicing method between the new layout unit and other layout units. The other layout units include any one of other new layout units and existing layout units in the layout unit information library that do not have DRC test problems. The layout unit information library stores several layout units. The placement module 1320 is configured to place the layout unit to be tested in the newly created layout according to the verification method to obtain the layout to be tested. The test module 1330 is configured to perform DRC testing on the layout to be tested.

[0147] In some embodiments, the determination module 1310 is configured to determine the verification method of the layout unit to be tested in the following manner, including: obtaining the test type corresponding to the layout unit to be tested; when the test type does not require a mutual splicing test between new layout units, determining the verification method is to splice a new layout unit between two identical existing layout units; when the test type requires a mutual splicing test between new layout units, determining the verification method is to splice a layout unit to be tested between two identical layout units to be tested.

[0148] In some embodiments, the determination module 1310 is configured to obtain the test type corresponding to the layout unit to be tested in the following manner, including: acquiring the attribute information of the new layout unit to obtain the attribute information acquisition result; when the attribute information acquisition result includes all the attributes of the new layout unit, determining that the test type is not required to perform mutual splicing test between the new layout units; when the attribute information acquisition result does not include all the attributes of the new layout unit, determining that the test type is required to perform mutual splicing test between the new layout units.

[0149] In some embodiments, the placement module 1320 is configured to place the layout units to be tested in the newly created layout according to the verification method in the following manner to obtain the layout to be tested, including: determining the placement starting point of the layout unit in the newly created layout; obtaining the unit width of the layout unit to be tested; determining the placement coordinate points of the layout unit to be tested according to the placement starting point and unit width of the layout unit; splicing and placing the layout units to be tested in sequence according to the verification method and the placement coordinate points to obtain the layout to be tested.

[0150] In some embodiments, the placement module 1320 is configured to determine the starting point for placing the publication unit in the newly created layout in the following manner, including: obtaining the test direction of the layout unit to be tested; when the test direction is the first direction or the second direction, determining the coordinate origin in the newly created layout as the starting point for placing the layout unit.

[0151] In some embodiments, the placement module 1320 is configured to determine the starting point for placing the publication unit in the newly created layout in the following manner, including: obtaining the test direction of the layout unit to be tested; when the test direction includes a first direction and a second direction, determining the first vertex coordinates of a preset corner in the newly created layout as the starting point for placing the layout unit in the first direction, and determining the second vertex coordinates of the preset corner in the newly created layout as the starting point for placing the layout unit in the second direction; wherein the first direction is the longitudinal direction, the second direction is the transverse direction, and the first vertex and the second vertex are the two diagonals of the preset corner.

[0152] In some embodiments, the placement module 1320 is configured to, after determining the verification method of the layout unit to be tested, further include: comparing the new layout unit with the preset reference layout unit to obtain a comparison result; when the comparison result is that the target parameter of the new layout unit is the same as the target parameter of the preset reference layout unit, placing it according to the verification method; wherein the target parameter includes the layout unit shape and the transistor direction; when the comparison result is that the target parameter of the new layout unit is different from the target parameter of the preset reference layout unit, rotating the new layout unit by a preset angle and then placing it according to the verification method.

[0153] It should be noted that the layout unit placement test device provided in the above embodiment and the layout unit placement test method provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs the operation has been described in detail in the method embodiment and will not be repeated here. In actual applications, the layout unit placement test device provided in the above embodiment can distribute the above functions to different functional modules as needed, that is, divide the internal structure of the device into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0154] An embodiment of the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, and when the one or more programs are executed by the one or more processors, the electronic device implements the method for layout unit placement testing provided in the above-mentioned embodiments.

[0155] Fig.14 The structure diagram of the computer system suitable for implementing the electronic device of the embodiment of the present application is shown. It should be noted that: Fig.14 The computer system 1400 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0156] like Fig.14As shown, the computer system 1400 includes a central processing unit (CPU) 1401, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1402 or the program loaded from the storage part 1408 to the random access memory (RAM) 1403, such as executing the method described in the above embodiment. Various programs and data required for system operation are also stored in the RAM 1403. The CPU 1401, the ROM 1402 and the RAM 1403 are connected to each other through the bus 1404. The input / output (I / O) interface 1405 is also connected to the bus 1404.

[0157] The following components are connected to the I / O interface 1405: an input section 1406 including a keyboard, a mouse, etc.; an output section 1407 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1408 including a hard disk, etc.; and a communication section 1409 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1409 performs communication processing via a network such as the Internet. A drive 1410 is also connected to the I / O interface 1405 as needed. A removable medium 1411, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1410 as needed so that a computer program read therefrom is installed into the storage section 1408 as needed.

[0158] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication part 1409, and / or installed from a removable medium 1411. When the computer program is executed by the central processing unit (CPU) 1401, various functions defined in the system of the present application are executed.

[0159] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier, which carries a computer-readable computer program. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. A computer program contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0160] Another aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the layout unit placement test method as described above when the computer program is executed by a processor. The computer-readable storage medium may be included in the electronic device described in the above embodiment, or may exist independently without being assembled into the electronic device.

[0161] Another aspect of the present application also provides a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the layout unit placement test method provided in each of the above embodiments.

[0162] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. A person skilled in the art can easily make corresponding changes or modifications based on the main concept and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A method for testing layout unit placement, characterized in that: The method comprises: Determine a verification method corresponding to a layout unit to be tested; wherein the layout unit to be tested includes a new layout unit and other layout units, the verification method is used to characterize a splicing method between the new layout unit and other layout units, the other layout units include other new layout units and any one of existing layout units in a layout unit information library that do not have a DRC design rule check test problem, and the layout unit information library stores a plurality of layout units; Placing the layout units to be tested in the newly created layout according to the verification method to obtain the layout to be tested; Performing a DRC test on the layout to be tested; Determining the verification method of the layout unit to be tested, including: obtaining the test type corresponding to the layout unit to be tested; when the test type does not require a mutual splicing test between new layout units, determining that the verification method is to splice one of the new layout units between two identical existing layout units; when the test type requires a mutual splicing test between new layout units, determining that the verification method is to splice one of the layout units to be tested between two identical layout units to be tested; Obtaining the test type corresponding to the layout unit to be tested, including: obtaining the attribute information of the new layout unit to obtain an attribute information acquisition result; when the attribute information acquisition result includes all the attributes of the new layout unit, determining that the test type is not required to perform a mutual splicing test between the new layout units; when the attribute information acquisition result does not include all the attributes of the new layout unit, determining that the test type is required to perform a mutual splicing test between the new layout units.

2. The method according to claim 1, characterized in that Placing the layout units to be tested in the newly created layout according to the verification method to obtain the layout to be tested includes: Determine the starting point for placing the publication map unit in the newly created layout; Obtaining the unit width of the layout unit to be tested; Determining the placement coordinate point of the layout unit to be tested according to the layout unit placement starting point and the unit width; The units of the layout to be tested are sequentially spliced ​​and placed according to the verification method and the placement coordinate points to obtain the layout to be tested.

3. The method according to claim 2, characterized in that Determining the starting point for placing the publication map unit in the newly created layout includes: Obtaining a test direction of the layout unit to be tested; When the test direction is the first direction or the second direction, the coordinate origin in the newly created layout is determined as the starting point for placing the layout unit, the first direction is the vertical direction, and the second direction is the horizontal direction.

4. The method according to claim 2, characterized in that: Determining the starting point for placing the publication map unit in the newly created layout includes: Obtaining a test direction of the layout unit to be tested; When the test direction includes a first direction and a second direction, the first vertex coordinates of the preset corner in the newly created layout are determined as the starting point for placing the layout unit in the first direction, and the second vertex coordinates of the preset corner in the newly created layout are determined as the starting point for placing the layout unit in the second direction; wherein the first direction is vertical, the second direction is horizontal, and the first vertex and the second vertex are the two diagonals of the preset corner.

5. The method according to claim 1, characterized in that After determining the verification method of the layout unit to be tested, the method further includes: Comparing the new layout unit with a preset reference layout unit to obtain a comparison result; If the comparison result shows that the target parameters of the new layout unit are the same as the target parameters of the preset reference layout unit, the layout is arranged according to the verification method; wherein the target parameters include the layout unit shape and the transistor direction; When the comparison result shows that the target parameter of the new layout unit is different from the target parameter of the preset reference layout unit, the new layout unit is rotated by a preset angle and then placed according to the verification method.

6. A layout unit placement test device, characterized in that: The device comprises: A determination module is configured to determine a verification method corresponding to a layout unit to be tested; wherein the layout unit to be tested includes a new layout unit and other layout units, the verification method is used to characterize a splicing method between the new layout unit and other layout units, the other layout units include other new layout units and any one of the existing layout units without DRC test problems in a layout unit information library, and the layout unit information library stores a plurality of layout units; A placement module is configured to place the layout units to be tested in a newly created layout according to the verification method to obtain a layout to be tested; A testing module is configured to perform a DRC test on the layout to be tested; Determining the verification method of the layout unit to be tested, including: obtaining the test type corresponding to the layout unit to be tested; when the test type does not require a mutual splicing test between new layout units, determining that the verification method is to splice one of the new layout units between two identical existing layout units; when the test type requires a mutual splicing test between new layout units, determining that the verification method is to splice one of the layout units to be tested between two identical layout units to be tested; Obtaining the test type corresponding to the layout unit to be tested, including: obtaining the attribute information of the new layout unit to obtain an attribute information acquisition result; when the attribute information acquisition result includes all the attributes of the new layout unit, determining that the test type is not required to perform a mutual splicing test between the new layout units; when the attribute information acquisition result does not include all the attributes of the new layout unit, determining that the test type is required to perform a mutual splicing test between the new layout units.

7. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, enables the electronic device to implement the method for layout unit placement testing as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: Computer-readable instructions are stored thereon, and when the computer-readable instructions are executed by a processor of a computer, the computer is caused to execute the method for layout unit placement testing described in any one of claims 1 to 5.

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