Chip and method for preparing the same

Abstract

The present invention provides a chip and a preparation method thereof, and relates to the technical field of semiconductor lasers. The chip comprises: a semiconductor layer structure, a dielectric layer, a conductive structure and a heat dissipation structure, wherein the top layer of the semiconductor layer structure is an ohmic contact layer; the top surface of the semiconductor layer structure has a ridge waveguide structure; the dielectric layer covers the top surface of the semiconductor layer structure; along a first direction, the chip comprises a first part close to a front cavity surface and a second part away from the front cavity surface; the dielectric layer comprises a first dielectric layer belonging to the first part, and a second dielectric layer belonging to the second part; the second dielectric layer has a window corresponding to the position of the ridge waveguide structure, and the conductive structure is connected to the top surface of the ohmic contact layer of the second part through the window; the thickness h1 of the first dielectric layer is less than the thickness h2 of the second dielectric layer; a heat dissipation structure is arranged on the top surface of the first dielectric layer, and the thermal conductivity of the heat dissipation structure is higher than the thermal conductivity of the dielectric layer; the conductive structure and the heat dissipation structure are arranged at intervals to form a heat insulation gap.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor lasers, and in particular to a chip and a preparation method thereof. Background Art

[0002] When preparing the chip, the dielectric layer in the upper surface area of ​​the ridge waveguide needs to be etched away to form an ohmic contact for current injection, while the dielectric layer in other locations is retained to achieve electrical isolation. In traditional technology, the thickness of the dielectric layer is evenly distributed.

[0003] Technical problems existing in the prior art: When the semiconductor laser is working, the temperature of the front cavity surface rises. Overheating of the front cavity surface will cause damage to the cavity surface of the light-emitting area, or even device degradation, and ultimately cause device failure. Summary of the invention

[0004] The object of the present invention is to provide a chip and a preparation method thereof, so as to alleviate the technical problem of excessively high front cavity surface temperature of the existing chip.

[0005] In a first aspect, the present invention provides a chip, comprising: a semiconductor layer structure, a dielectric layer, a conductive structure and a heat dissipation structure; the top layer of the semiconductor layer structure is an ohmic contact layer;

[0006] The top surface of the semiconductor layer structure has a ridge waveguide structure;

[0007] The dielectric layer covers the top surface of the semiconductor layer structure;

[0008] Along the first direction, the chip includes a first portion close to the front cavity surface and a second portion away from the front cavity surface; the dielectric layer includes a first dielectric layer belonging to the first portion, and a second dielectric layer belonging to the second portion;

[0009] The second dielectric layer has a window corresponding to the position of the ridge waveguide structure, and the conductive structure is connected to the top surface of the ohmic contact layer of the second part through the window; the first direction is perpendicular to the front cavity surface;

[0010] The thickness h1 of the first dielectric layer is less than the thickness h2 of the second dielectric layer;

[0011] The heat dissipation structure is arranged on the top surface of the first dielectric layer, and the thermal conductivity of the heat dissipation structure is higher than the thermal conductivity of the dielectric layer; in the second direction, the heat dissipation structure completely covers the ridge waveguide structure, and at least one of the two outer side walls of the heat dissipation structure interval is located outside the ridge waveguide structure; the second direction is perpendicular to the first direction and the stacking direction of the semiconductor layer structure respectively;

[0012] Along the first direction, the conductive structure and the heat dissipation structure are spaced apart to form a thermal insulation gap.

[0013] Furthermore, the sub-top layer of the semiconductor layer structure is a P-type cladding; the portion of the first dielectric layer located below the heat dissipation structure is removed and a notch is formed on the dielectric layer; the top surface of the ridge waveguide structure is provided with a recessed portion sunken downward to the P-type cladding, and the heat dissipation structure passes through the notch and is connected to the bottom surface of the recess.

[0014] Furthermore, the material of the heat dissipation structure is a conductive material;

[0015] The doping concentration of the ohmic contact layer is greater than 1×10 19 cm -3 ;

[0016] The doping concentration of the bottom surface of the concave portion is less than 5×10 18 cm -3 .

[0017] Furthermore, a downwardly recessed groove is provided in a portion of the top surface of the ridge waveguide structure directly below the thermal insulation gap.

[0018] Furthermore, the groove includes a first groove wall and a second groove wall arranged along a first direction, the first groove wall is close to the conductive structure, and the second groove wall is close to the heat dissipation structure; the second groove wall extends along the up-down direction;

[0019] From top to bottom, there are at least two positions, wherein at the upper position, the distance between the second groove wall and the first groove wall is L1; at the lower position, the distance between the second groove wall and the first groove wall is L2, and L1 is greater than L2.

[0020] Furthermore, from top to bottom, the first groove wall is inclined toward the second groove wall;

[0021] Alternatively, the first groove wall includes a first side wall and a second side wall connected in sequence from top to bottom, the first side wall and the second side wall both extend in the up-down direction, and the distance between the first side wall and the second groove wall is greater than the distance between the second side wall and the second groove wall.

[0022] Furthermore, the material of the heat dissipation structure is a non-conductive material;

[0023] The portion of the first dielectric layer located below the heat dissipation structure is removed and a gap is formed on the dielectric layer; the heat dissipation structure is connected to the top surface of the ohmic contact layer through the gap.

[0024] Furthermore, the thickness h1 of the first dielectric layer ranges from 5 nm to 30 nm;

[0025] The thickness h2 of the second dielectric layer ranges from 80 nm to 300 nm.

[0026] In a second aspect, the present invention provides a chip preparation method, comprising the steps of:

[0027] Step S1. providing a semiconductor layer structure with an ohmic contact layer as the top layer;

[0028] Step S2. Etching the semiconductor layer structure to obtain a ridge waveguide structure;

[0029] Step S3. forming a dielectric layer covering the top surface of the semiconductor layer structure;

[0030] Step S4. Thinning a portion of the dielectric layer close to the front cavity surface in the first direction;

[0031] forming a window on the dielectric layer which is far away from the front cavity surface and has not been thinned, so as to expose a part of the ohmic contact layer;

[0032] Wherein, the first direction is perpendicular to the anterior cavity surface;

[0033] Step S5. Prepare a conductive structure in the window, the conductive structure is connected to the ohmic contact layer; prepare a heat dissipation structure on the thinned dielectric layer, the thermal conductivity of the heat dissipation structure is higher than the thermal conductivity of the dielectric layer; in the second direction, the heat dissipation structure completely covers the ridge waveguide structure, and at least one of the two outer side walls of the heat dissipation structure interval is located outside the ridge waveguide structure; the second direction is perpendicular to the first direction and the stacking direction of the semiconductor layer structure respectively;

[0034] In the first direction, there is a thermal insulation gap between the conductive structure and the heat dissipation structure.

[0035] Furthermore, in the step S4, when the portion of the dielectric layer close to the front cavity surface is thinned, the portion is thinned to zero thickness, so that a notch is formed on the dielectric layer, and the notch is closer to the front cavity surface than the window;

[0036] In the step S5, the step of preparing a heat dissipation structure on the thinned dielectric layer is replaced by preparing a heat dissipation structure made of a non-conductive material on the ohmic contact layer through the gap.

[0037] Furthermore, the second top layer of the semiconductor layer structure is a P-type cladding layer;

[0038] In the step S4, when the portion of the dielectric layer close to the front cavity surface is thinned to zero thickness, a notch is formed on the dielectric layer, and the notch is closer to the front cavity surface than the window;

[0039] The step S4 further comprises: after the step of thinning the portion of the dielectric layer close to the front cavity surface: forming a concave portion extending to the P cladding layer on the top surface of the ridge waveguide structure;

[0040] In the step S5, the step of preparing the heat dissipation structure on the thinned dielectric layer is replaced by preparing the heat dissipation structure on the bottom surface of the recess through the notch.

[0041] Furthermore, the chip preparation method further includes the following steps after step S2:

[0042] From top to bottom, the ridge waveguide structure is etched to form a groove, wherein the groove is located at the thermal insulation gap between the preset conductive structure position and the preset heat dissipation structure position.

[0043] The present invention has at least the following advantages or beneficial effects:

[0044] The chip provided by the present invention comprises: a semiconductor layer structure, a dielectric layer, a conductive structure and a heat dissipation structure; the top layer of the semiconductor layer structure is an ohmic contact layer; the top surface of the semiconductor layer structure has a ridge waveguide structure; the dielectric layer covers the top surface of the semiconductor layer structure; along the first direction, the chip comprises a first part close to the front cavity surface and a second part away from the front cavity surface; the dielectric layer comprises a first dielectric layer belonging to the first part, and a second dielectric layer belonging to the second part; the second dielectric layer has a window corresponding to the position of the ridge waveguide structure, and the conductive structure is connected to the top surface of the ohmic contact layer of the second part through the window; the first direction is perpendicular to the front cavity surface; the thickness h1 of the first dielectric layer is less than the thickness h2 of the second dielectric layer; the heat dissipation structure is arranged on the top surface of the first dielectric layer, and the thermal conductivity of the heat dissipation structure is higher than the thermal conductivity of the dielectric layer; in the second direction, the heat dissipation structure completely covers the ridge waveguide structure, and at least one of the two outer side walls of the heat dissipation structure interval is located on the outside of the ridge waveguide structure; the second direction is perpendicular to the first direction and the stacking direction of the semiconductor layer structure respectively; along the first direction, the conductive structure and the heat dissipation structure are arranged at intervals to form a thermal insulation gap.

[0045] The conductive structure is connected through the window ridge waveguide structure, and the conductive structure is used to connect to an external power supply. In the first direction, the heat dissipation structure and the conductive structure are spaced apart so that the conductive structure is away from the front cavity surface, reducing the heat conduction of the conductive structure to the front cavity surface, and at the same time, also reducing the heat conduction of the conductive structure to the front cavity surface through the heat dissipation structure. The thickness h1 of the first dielectric layer is set to be smaller than the thickness h2 of the second dielectric layer, and the thermal conductivity of the heat dissipation structure is higher than the thermal conductivity of the dielectric layer. In the second direction, the heat dissipation structure is wider than the ridge waveguide structure. Therefore, the heat generated by the ridge waveguide structure can be conducted to the two ends of the heat dissipation structure along the second direction to reduce the temperature at the position of the ridge waveguide structure, achieve better heat dissipation effect, avoid overheating of the front cavity surface and cause cavity surface damage, and improve the reliability of the cavity surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A schematic diagram of a chip provided in Embodiment 1 of the present invention (the conductive structure and the heat dissipation structure are not shown);

[0048] Figure 2 A top view of the chip provided in Embodiment 1 of the present invention;

[0049] Figure 3 for Figure 2 Sectional view in the AA direction;

[0050] Figure 4 for Figure 2 Cross-sectional view in the BB direction;

[0051] Figure 5 A schematic diagram of a chip provided in Example 2 of the present invention;

[0052] Figure 6 A top view of a chip provided in Embodiment 2 of the present invention;

[0053] Figure 7 for Figure 6 Cross-sectional view in CC direction;

[0054] Figure 8 for Figure 6 Cross-sectional view in the middle DD direction;

[0055] Fig. 9 A cross-sectional view of another chip provided in Embodiment 2 of the present invention;

[0056] Fig.10 A cross-sectional view of another chip provided in Embodiment 2 of the present invention;

[0057] Fig.11 A cross-sectional view of another chip provided in Embodiment 2 of the present invention;

[0058] Fig.12 A longitudinal cross-sectional view of the ridge waveguide structure of the chip provided in Example 3 of the present invention.

[0059] Icons: 1-substrate; 2-N-type cladding; 3-N-type waveguide layer; 4-quantum well; 5-P-type waveguide layer; 6-P-type cladding; 7-ohmic contact layer; 8-conductive structure; 9-heat dissipation structure; 11-groove; 12-first dielectric layer; 13-second dielectric layer; 14-ridge waveguide structure; 15-semiconductor layer structure; 16-first part; 17-second part; 18-window; 19-second groove wall; 20-first groove wall; 21-notch; 22-recess. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0063] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0064] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0065] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0066] Example 1

[0067] like Figure 1-Figure 4 As shown, the chip provided by the present invention includes a semiconductor layer structure 15 , a dielectric layer, a conductive structure 8 and a heat dissipation structure 9 .

[0068] like Figure 1 and Figure 3 As shown, the semiconductor layer structure 15 is formed by growing from the substrate 1 in a bottom-up direction. For the convenience of explaining the chip structure, the side of the substrate 1 is set as the lower side, and the side of the conductive structure 8 is set as the upper side. In this embodiment, the semiconductor layer structure 15 may include a substrate 1, an N-type cladding layer 2, an N-type waveguide layer 3, a quantum well 4, a P-type waveguide layer 5, a P-type cladding layer 6, and an ohmic contact layer 7 connected in sequence from bottom to top. In this embodiment, the ohmic contact layer 7 is etched from top to bottom to the P-type cladding layer 6 to obtain a ridge waveguide structure 14.

[0069] The quantum well 4 is an undoped semiconductor material layer, and the doping concentration gradually increases from the quantum well 4 upward through the P-type waveguide layer 5, the P-type cladding layer 6 to the ohmic contact layer 7, wherein the doping concentration of the ohmic contact layer 7 is greater than 1×10 19 cm -3The doping concentration of the P-type cladding layer 6 is less than the doping concentration of the ohmic contact layer 7. The doping concentrations of the P-type waveguide layer 5 and the P-type cladding layer 6 are gradually changed. For the semiconductor layer structure 15 of gallium arsenide material, the element doped in the P-type cladding layer 6 is carbon.

[0070] The top surface of the semiconductor layer structure 15 is provided with a dielectric layer. During preparation, the entire top surface of the semiconductor layer structure 15 is first completely covered with the dielectric layer (the dielectric layer covers the ridge waveguide structure 14) to achieve electrical isolation. The material of the dielectric layer can be silicon nitride (SiN) or silicon dioxide (SiO2).

[0071] like Figure 3 As shown, along the first direction, the chip includes a first portion 16 close to the front cavity surface and a second portion 17 away from the front cavity surface. For the convenience of describing the structure, the portion of the dielectric layer located in the first portion 16 is the first dielectric layer 12, and the portion located in the second portion 17 is the second dielectric layer 13.

[0072] Along the first direction, the length of the first portion 16 is less than the length of the second portion 17. The second dielectric layer 13 has a window 18 corresponding to the position of the ridge waveguide structure 14, which is formed by etching, and then a conductive structure 8 is formed at the window 18, and the conductive structure 8 is connected to the top surface of the ohmic contact layer 7 of the second portion 17 through the window 18, thereby forming an ohmic contact to achieve current injection.

[0073] like Figure 3 and Figure 4 As shown, the thickness h1 of the first dielectric layer 12 is less than the thickness h2 of the second dielectric layer 13. In this embodiment, the thickness h1 of the first dielectric layer 12 is greater than 0, and in other practicable solutions, the thickness h1 of the first dielectric layer 12 may be equal to 0.

[0074] During preparation, a dielectric layer of uniform thickness can be uniformly prepared, and then the second dielectric layer 13 can be thinned to form regions of different thicknesses. The thickness h1 of the first dielectric layer 12 is in the range of 5nm-30nm. The thickness h2 of the second dielectric layer 13 is in the range of 80nm-300nm.

[0075] A heat dissipation structure 9 is disposed on the top surface of the first dielectric layer 12, and the thermal conductivity of the heat dissipation structure 9 is higher than that of the dielectric layer. In the second direction, the heat dissipation structure 9 completely covers the ridge waveguide structure 14, and at least one of the two outer side walls separated by the heat dissipation structure 9 is located outside the ridge waveguide structure 14; the second direction is perpendicular to the first direction and the stacking direction of the semiconductor layer structure 15. In this embodiment, the two outer side walls separated by the heat dissipation structure 9 are both located outside the opposite side walls of the ridge waveguide structure 14, and the heat dissipation structure 9 can conduct the heat generated by the ridge waveguide structure 14 located in the middle of the heat dissipation structure 9 to the two ends of the heat dissipation structure 9 in the second direction.

[0076] The material of the heat dissipation structure 9 may be a conductive material, such as gold (Au) or platinum (Pt), or a non-conductive material, such as diamond, silicon carbide or aluminum nitride.

[0077] Along the first direction, the conductive structure 8 and the heat dissipation structure 9 are spaced apart to form a thermal insulation gap, that is, the conductive structure 8 is far away from the front cavity surface, and there is also a thermal insulation gap between the conductive structure 8 and the heat dissipation structure 9, so that heat is difficult to be transferred to the front cavity surface laterally (in the first direction).

[0078] The conductive structure 8 is connected to the ridge waveguide structure 14 through the window 18, and the conductive structure 8 is used to connect to an external power supply. In the first direction, the heat dissipation structure 9 is spaced apart from the conductive structure 8, so that the conductive structure 8 is away from the front cavity surface, reducing the heat conduction of the conductive structure 8 to the front cavity surface, and at the same time, also reducing the heat conduction of the conductive structure 8 to the front cavity surface through the heat dissipation structure 9. The thickness h1 of the first dielectric layer 12 is set to be smaller than the thickness h2 of the second dielectric layer 13, and the thermal conductivity of the heat dissipation structure 9 is higher than the thermal conductivity of the dielectric layer. Therefore, the heat dissipation structure 9 with high thermal conductivity can efficiently dissipate heat; at the same time, in the second direction, the heat dissipation structure 9 is wider than the ridge waveguide structure 14. Therefore, the heat generated by the ridge waveguide structure 14 can be conducted to the two ends of the heat dissipation structure 9 along the second direction to reduce the temperature at the position of the ridge waveguide structure 14, achieve better heat dissipation effect, avoid overheating of the front cavity surface and damage to the cavity surface, and improve the reliability of the cavity surface.

[0079] Example 2

[0080] like Figure 5-Figure 8 As shown, in this embodiment, the portion of the first dielectric layer 12 located below the heat dissipation structure 9 is removed and a notch 21 is formed on the dielectric layer; the top surface of the ridge waveguide structure 14 is provided with a recess 22 that is recessed downward to the P-type cladding 6, and the heat dissipation structure 9 is connected to the bottom surface of the recess 22 after passing through the notch 21.

[0081] In the first part 16, the part that originally needs to be thinned is thinned to zero thickness, thereby forming a notch 21 on the dielectric layer. In the second direction, the length of the notch 21 is the same as the length of the chip, that is, the first dielectric layer 12 is completely removed. The top surface of the ridge waveguide structure 14 is provided with a recessed portion 22 that is recessed downward, and the recess 22 extends all the way to the P-type cladding layer 6. In the second direction, the length of the recess 22 is consistent with the length of the ridge waveguide structure 14, and the heat dissipation structure 9 passes through the notch 21 and is connected to the bottom surface of the recess 22.

[0082] The first dielectric layer 12 may be completely removed to form a larger notch 21. Alternatively, only the dielectric layer below the preset heat dissipation structure 9 may be removed to form a smaller notch 21.

[0083] The material of the heat dissipation structure 9 can be a conductive material, and the difference from the embodiment 1 is that in the first part 16, the dielectric layer directly below the heat dissipation structure 9 is removed. In the top surface of the ridge waveguide structure 14, a portion directly below the heat dissipation structure 9 is provided with a recessed portion 22 that is recessed downward, and the recessed portion 22 extends to the P-type cladding layer 6. The heat dissipation structure 9 penetrates the dielectric layer and is connected to the bottom surface of the recessed portion 22.

[0084] The concave portion is the portion of the P-type cladding layer 6. From bottom to top, the doping concentration of the P-type cladding layer 6 gradually increases. The concave portion 22 can be formed by etching. 18 The doping concentration of the bottom surface of the recess 22 is less than 5×10 18 cm -3 The etching depth is approximately 300nm-500nm. The heat dissipation structure 9 is connected to the region with a lower doping concentration in the P-type cladding layer 6, thereby preventing the semiconductor layer structure 15 from leaking electricity and causing the heat dissipation structure 9 to generate heat.

[0085] It should be noted that the P-type waveguide layer 5 cannot be etched. The P-type waveguide layer 5 has a higher refractive index and is used to limit the waveguide. The P-type waveguide layer 5 is where the light field energy is concentrated. The deeper the P-type cladding layer 6 is etched below the heat dissipation structure 9, the more contact with the light field, and the greater the loss. Therefore, the P-type cladding layer 6 cannot be etched too deep.

[0086] Furthermore, a portion of the top surface of the ridge waveguide structure 14 directly below the thermal insulation gap is provided with a downwardly recessed groove 11 .

[0087] like Figure 7As shown, after the semiconductor layer structure 15 forms the ridge waveguide structure 14, after etching downward through the ohmic contact layer 7 at the preset insulation gap position, the P-type cladding layer 6 is further etched downward to obtain the groove 11. When the subsequent dielectric layer is prepared, the dielectric layer material will fill and cover the groove 11, thereby increasing the resistance in the first direction. The dielectric layer material located in the groove 11 can also be removed to form an air gap with greater resistance. Furthermore, in the first direction, the groove 11 and the concave portion 22 can be connected, that is, a complete groove structure is formed, which can be obtained by one etching, such as Fig.11 shown.

[0088] like Figure 3 As shown, the cross-sectional shape of the groove 11 can be rectangular or other shapes. The groove 11 includes a first groove wall 20 and a second groove wall 19 arranged along a first direction, the first groove wall 20 is close to the conductive structure 8, and the second groove wall 19 is close to the heat dissipation structure 9; the second groove wall 19 extends in the up-down direction; from top to bottom, there are at least two positions, wherein at the upper position, the distance between the second groove wall 19 and the first groove wall 20 is L1; at the lower position, the distance between the second groove wall 19 and the first groove wall 20 is L2, and L1 is greater than L2.

[0089] The reason for setting the first groove wall 20 as a non-vertical plane is that the larger the distance between the first groove wall 20 and the second groove wall 19, the better. However, the corresponding position of the left conductive structure 8 is a large current area, which will affect the surface of the first groove wall 20, causing greater heat and lower stability. Therefore, from top to bottom, the first groove wall 20 can be set in a manner of gradually approaching the second groove wall 19 to increase the lateral width of the groove 11 as much as possible.

[0090] like Fig.10 As shown, in other feasible schemes, the cross-sectional shape of the groove 11 can be a step-type. Specifically, the first groove wall 20 includes a first side wall and a second side wall connected in sequence from top to bottom. The groove 11 is formed by an upper and lower part with different widths. The first side wall and the second side wall both extend in the up and down directions. The distance between the first side wall and the second groove wall 19 is greater than the distance between the second side wall and the second groove wall 19.

[0091] like Fig. 9 As shown, the cross-sectional shape of the groove 11 can also be a trapezoid, and from top to bottom, the first groove wall 20 is inclined toward the second groove wall 19 .

[0092] Example 3

[0093] like Fig.12As shown, the material of the heat dissipation structure 9 is a non-conductive material; the portion of the first dielectric layer 12 located below the heat dissipation structure 9 is removed and a notch 21 is formed on the dielectric layer; the heat dissipation structure 9 is connected to the top surface of the ohmic contact layer 7 through the notch 21.

[0094] The difference from Example 1 is that, in this embodiment, the material of the heat dissipation structure 9 is a non-conductive material, such as diamond or silicon carbide. Therefore, there is no need to set a dielectric layer in the first part 16. That is, in the first part 16, the portion of the dielectric layer directly below the heat dissipation structure 9 is removed to form a notch 21. The heat dissipation structure 9 is directly connected to the top surface of the ohmic contact layer 7, and heat conduction and heat dissipation are completely performed through the heat dissipation structure 9, resulting in a better heat dissipation effect.

[0095] Example 4

[0096] like Figure 1-Figure 4 As shown, the chip preparation method provided in this embodiment includes the steps of:

[0097] Step S1 . Providing a semiconductor layer structure 15 with an ohmic contact layer 7 as the top layer.

[0098] The semiconductor layer structure 15 grows from the substrate 1 in a bottom-up direction, and the semiconductor layer structure 15 may include a substrate 1, an N-type cladding layer 2, an N-type waveguide layer 3, a quantum well 4, a P-type waveguide layer 5, a P-type cladding layer 6 and an ohmic contact layer 7 connected in sequence from bottom to top.

[0099] Step S2 . Etching the semiconductor layer structure 15 to obtain a ridge waveguide structure 14 .

[0100] By etching from top to bottom, two grooves are opened on the top surface of the semiconductor layer structure 15 , the grooves penetrate the ohmic contact layer 7 , and a ridge waveguide structure 14 is formed between the two grooves. The preparation of the ridge waveguide structure 14 belongs to the prior art.

[0101] Step S3: forming a dielectric layer covering the top surface of the semiconductor layer structure 15.

[0102] A dielectric layer is prepared on the top surface of the semiconductor layer structure 15 . The dielectric layer completely covers the top surface of the semiconductor layer structure 15 and also covers the top surface of the ridge waveguide structure 14 .

[0103] The dielectric layer may be made of silicon nitride (SiN) or silicon dioxide (SiO2). The dielectric layer plays an electrical isolation role.

[0104] Step S4. Thinning the portion of the dielectric layer close to the front cavity surface in a first direction; forming a window 18 on the dielectric layer away from the front cavity surface and not thinned to expose part of the ohmic contact layer 7; wherein the first direction is perpendicular to the front cavity surface.

[0105] The portion of the dielectric layer close to the front cavity surface is thinned, while the portion away from the front cavity surface is not processed, so that the dielectric layer forms two portions with different thicknesses in the first direction, the portion close to the front cavity surface is thin, and the portion away from the front cavity surface is thick. For the convenience of explanation, along the first direction, the portion of the chip with the thinned dielectric layer is the first portion 16, and the portion of the chip with the unthinned dielectric layer is the second portion 17. The dielectric layer on the first portion 16 is opened to obtain a window 18, and the ohmic contact layer 7 of the ridge waveguide structure 14 is exposed.

[0106] Step S5. Prepare a conductive structure 8 in the window 18, and the conductive structure 8 is connected to the ohmic contact layer 7; prepare a heat dissipation structure 9 on the thinned dielectric layer, and the thermal conductivity of the heat dissipation structure 9 is higher than the thermal conductivity of the dielectric layer; in the second direction, the heat dissipation structure 9 completely covers the ridge waveguide structure 14, and at least one of the two outer side walls separated by the heat dissipation structure 9 is located on the outside of the ridge waveguide structure 14; the second direction is perpendicular to the first direction and the stacking direction of the semiconductor layer structure 15 respectively; in the first direction, there is a thermal insulation gap between the conductive structure 8 and the heat dissipation structure 9.

[0107] The conductive structure 8 covers the window 18, and the conductive structure 8 forms an ohmic contact with the ohmic contact layer 7 through annealing. The conductive structure 8 and the heat dissipation structure 9 are made of different materials and are prepared in steps. The heat dissipation structure 9 in this embodiment is made of a conductive material, such as Au, and the thermal conductivity of the heat dissipation structure 9 is higher than that of the dielectric layer, which can improve the heat dissipation effect.

[0108] Along the first direction, the conductive structure 8 and the heat dissipation structure 9 are spaced apart to form a thermal insulation gap, that is, the distance between the conductive structure 8 and the front cavity surface is relatively far, and there is also a thermal insulation gap between the conductive structure 8 and the heat dissipation structure 9, so that heat is difficult to be transferred laterally to the front cavity surface. In the second direction, the heat dissipation structure 9 completely covers the ridge waveguide structure 14, and at least one of the two outer side walls spaced apart by the heat dissipation structure 9 is located outside the ridge waveguide structure 14; the second direction is perpendicular to the first direction and the stacking direction of the semiconductor layer structure 15, respectively. In this embodiment, the two outer side walls spaced apart by the heat dissipation structure 9 are both located outside the opposite side walls of the ridge waveguide structure 14, and the heat dissipation structure 9 can conduct the heat generated by the ridge waveguide structure 14 located in the middle of the heat dissipation structure 9 to the two ends of the second direction of the heat dissipation structure 9.

[0109] The conductive structure 8 is connected to the ridge waveguide structure 14 through the window 18, and the conductive structure 8 is used to connect to an external power supply. In the first direction, the heat dissipation structure 9 is spaced apart from the conductive structure 8, so that the conductive structure 8 is away from the front cavity surface, reducing the heat conduction of the conductive structure 8 to the front cavity surface, and at the same time, also reducing the heat conduction of the conductive structure 8 to the front cavity surface through the heat dissipation structure 9. The thickness h1 of the first dielectric layer 12 is set to be smaller than the thickness h2 of the second dielectric layer 13, and the thermal conductivity of the heat dissipation structure 9 is higher than the thermal conductivity of the dielectric layer. Therefore, the heat dissipation structure 9 with high thermal conductivity dissipates heat efficiently; at the same time, in the second direction, the heat dissipation structure 9 is wider than the ridge waveguide structure 14. Therefore, the heat generated by the ridge waveguide structure 14 can be conducted to the two ends of the heat dissipation structure 9 along the second direction to reduce the temperature at the position of the ridge waveguide structure 14, achieve better heat dissipation effect, avoid overheating of the front cavity surface and cause cavity surface damage, and improve the reliability of the cavity surface.

[0110] Example 5

[0111] like Fig.12 As shown, in step S4, when the portion of the dielectric layer close to the front cavity surface is thinned, it is thinned to zero thickness to form a notch 21 on the dielectric layer, and the notch 21 is closer to the front cavity surface than the window 18; in step S5, the step of preparing the heat dissipation structure 9 on the thinned dielectric layer is replaced by preparing the heat dissipation structure 9 of non-conductive material on the ohmic contact layer 7 through the notch 21.

[0112] The first dielectric layer 12 may be completely removed to form a larger notch 21. Alternatively, only the dielectric layer below the heat dissipation structure 9 may be removed to form a smaller notch 21.

[0113] The difference from Example 4 is that in this embodiment, the dielectric layer above the ridge waveguide structure 14 is thinned to zero thickness, that is, the thinned portion in Example 4 can be completely removed to form a notch 21 on the dielectric layer, and the notch 21 is closer to the front cavity surface than the window 18. Then, a heat dissipation structure 9 made of a non-conductive material is prepared on the ohmic contact layer 7 directly opposite to the notch 21.

[0114] The material of the heat dissipation structure 9 in this embodiment is a non-conductive material, such as diamond or silicon carbide. Therefore, there is no need to set a dielectric layer in the first part 16. That is, in the first part 16, the part of the dielectric layer directly below the heat dissipation structure 9 is removed, and the heat dissipation structure 9 is directly connected to the top surface of the ohmic contact layer 7. Heat conduction and heat dissipation are completely performed through the heat dissipation structure 9, and the heat dissipation effect is better.

[0115] Example 6

[0116] like Figure 5-Figure 8As shown, in step S4, when the portion of the dielectric layer close to the front cavity surface is thinned, it is thinned to zero thickness to form a notch 21 on the dielectric layer, and the notch 21 is closer to the front cavity surface than the window 18; step S4 also includes: a step performed after the step of thinning the portion of the dielectric layer close to the front cavity surface: forming a recess 22 extending to the P cladding on the top surface of the ridge waveguide structure 14; in step S5, the step of preparing the heat dissipation structure 9 on the thinned dielectric layer is replaced by preparing the heat dissipation structure 9 on the bottom surface of the recess 22 through the notch 21.

[0117] The difference from Example 4 is that in this embodiment, the dielectric layer above the ridge waveguide structure 14 is thinned to zero thickness, that is, the thinned portion in Example 4 can be completely removed to form a notch 21 on the dielectric layer, and the notch 21 is closer to the front cavity surface than the window 18. Then, a concave portion 22 is formed on the top surface of the ridge waveguide structure 14 to face the notch 21, wherein the notch 21 and the concave portion 22 can be obtained by etching once. Finally, a heat dissipation structure 9 is prepared on the bottom surface of the concave portion 22, and the material of the heat dissipation structure 9 can be a conductive material or a non-conductive material.

[0118] When the material of the heat dissipation structure 9 is a conductive material, the dielectric layer, the ohmic contact layer 7 and part of the P-type cladding layer 6 are gradually etched away from top to bottom. From bottom to top, the doping concentration of the P-type cladding layer 6 gradually increases, and the concave portion 22 can be formed by etching. 18 cm -3 The heat dissipation structure 9 is connected to the region with lower doping concentration in the P-type cladding layer 6, thereby preventing the semiconductor layer structure 15 from leaking electricity and causing the heat dissipation structure 9 to heat up.

[0119] like Figure 7 As shown, the chip preparation method also includes a step performed after step S2: etching the ridge waveguide structure 14 from top to bottom to form a groove 11, wherein the groove 11 is located at the thermal insulation gap between the preset conductive structure 8 position and the preset heat dissipation structure 9 position.

[0120] After the semiconductor layer structure 15 forms the ridge waveguide structure 14, after etching downward through the ohmic contact layer 7 at the preset insulation gap position, the P-type cladding layer 6 is further etched downward to obtain the groove 11. When the subsequent dielectric layer is prepared, the dielectric layer material will fill and cover the groove 11, thereby increasing the resistance in the first direction. The dielectric layer material located in the groove 11 can also be removed to form an air gap with greater resistance. Furthermore, in the first direction, the groove 11 and the concave portion 22 can be connected, that is, a complete groove structure is formed, which can be obtained by one etching.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip, characterized in that: include: A semiconductor layer structure (15), a dielectric layer, a conductive structure (8) and a heat dissipation structure (9); the top layer of the semiconductor layer structure (15) is an ohmic contact layer (7); The top surface of the semiconductor layer structure (15) has a ridge waveguide structure (14); The dielectric layer covers the top surface of the semiconductor layer structure (15); Along a first direction, the chip comprises a first portion (16) close to the front cavity surface and a second portion (17) far from the front cavity surface; the dielectric layer comprises a first dielectric layer (12) belonging to the first portion (16), and a second dielectric layer (13) belonging to the second portion (17); The second dielectric layer (13) has a window (18) corresponding to the position of the ridge waveguide structure (14); the conductive structure (8) is connected to the top surface of the ohmic contact layer (7) of the second part (17) through the window (18); the first direction is perpendicular to the front cavity surface; The thickness h1 of the first dielectric layer (12) is smaller than the thickness h2 of the second dielectric layer (13); The heat dissipation structure (9) is arranged on the top surface of the first dielectric layer (12), and the thermal conductivity of the heat dissipation structure (9) is higher than the thermal conductivity of the dielectric layer; in the second direction, the heat dissipation structure (9) completely covers the ridge waveguide structure (14), and at least one of the two outer side walls separated by the heat dissipation structure (9) is located outside the ridge waveguide structure (14); the second direction is perpendicular to the first direction and the stacking direction of the semiconductor layer structure (15); Along the first direction, the conductive structure (8) and the heat dissipation structure (9) are arranged at intervals to form a heat insulation gap.

2. The chip according to claim 1, characterized in that: The second top layer of the semiconductor layer structure (15) is a P-type cladding layer (6); the portion of the first dielectric layer (12) located below the heat dissipation structure (9) is removed and a notch (21) is formed on the first dielectric layer (12); the top surface of the ridge waveguide structure (14) is provided with a recess (22) that is recessed downward to the P-type cladding layer (6); the heat dissipation structure (9) passes through the notch (21) and is connected to the bottom surface of the recess (22).

3. The chip according to claim 2, characterized in that: The material of the heat dissipation structure (9) is a conductive material; The doping concentration of the ohmic contact layer (7) is greater than 1×10 19 cm -3 ; The doping concentration of the bottom surface of the recess (22) is less than 5×10 18 cm -3 .

4. The chip according to claim 2 or 3, characterized in that: A downwardly recessed groove (11) is provided in the top surface of the ridge waveguide structure (14), at a portion directly below the thermal insulation gap.

5. The chip according to claim 4, characterized in that: The groove (11) comprises a first groove wall (20) and a second groove wall (19) arranged along a first direction, the first groove wall (20) being close to the conductive structure (8), and the second groove wall (19) being close to the heat dissipation structure (9); the second groove wall (19) extending in an up-down direction; From top to bottom, there are at least two positions, wherein at the upper position, the distance between the second groove wall (19) and the first groove wall (20) is L1; at the lower position, the distance between the second groove wall (19) and the first groove wall (20) is L2, and L1 is greater than L2.

6. The chip according to claim 5, characterized in that: From top to bottom, the first groove wall (20) is inclined toward the second groove wall (19); Alternatively, the first groove wall (20) comprises a first side wall and a second side wall connected in sequence from top to bottom, the first side wall and the second side wall both extend in the up-down direction, and the distance between the first side wall and the second groove wall (19) is greater than the distance between the second side wall and the second groove wall (19).

7. The chip according to claim 1, characterized in that: The material of the heat dissipation structure (9) is a non-conductive material; The portion of the first dielectric layer (12) located below the heat dissipation structure (9) is removed and a notch (21) is formed on the first dielectric layer (12); the heat dissipation structure (9) is connected to the top surface of the ohmic contact layer (7) through the notch (21).

8. The chip according to claim 1, characterized in that: The thickness h1 of the first dielectric layer (12) has a value ranging from 5 nm to 30 nm; The thickness h2 of the second dielectric layer (13) has a value ranging from 80 nm to 300 nm.

9. A chip preparation method, characterized in that: Includes steps: Step S1. Providing a semiconductor layer structure (15) whose top layer is an ohmic contact layer (7); Step S2. Etching the semiconductor layer structure (15) to obtain a ridge waveguide structure (14); Step S3. forming a dielectric layer covering the top surface of the semiconductor layer structure (15); Step S4. Thinning a portion of the dielectric layer close to the front cavity surface in the first direction; forming a window (18) on the dielectric layer that is away from the front cavity surface and has not been thinned, so as to expose a portion of the ohmic contact layer (7); Wherein, the first direction is perpendicular to the anterior cavity surface; Step S5. preparing a conductive structure (8) in the window (18), wherein the conductive structure (8) is connected to the ohmic contact layer (7); preparing a heat dissipation structure (9) on the thinned dielectric layer, wherein the thermal conductivity of the heat dissipation structure (9) is higher than the thermal conductivity of the dielectric layer; in a second direction, the heat dissipation structure (9) completely covers the ridge waveguide structure (14), and at least one of the two outer side walls separated by the heat dissipation structure (9) is located outside the ridge waveguide structure (14); the second direction is perpendicular to the first direction and the stacking direction of the semiconductor layer structure (15); In the first direction, a thermal insulation gap is provided between the conductive structure (8) and the heat dissipation structure (9).

10. The chip preparation method according to claim 9, characterized in that: In the step S4, when the portion of the dielectric layer close to the front cavity surface is thinned to zero thickness, a notch (21) is formed on the dielectric layer, and the notch (21) is closer to the front cavity surface than the window (18); In the step S5, the step of preparing the heat dissipation structure (9) on the thinned dielectric layer is replaced by preparing the heat dissipation structure (9) of non-conductive material on the ohmic contact layer (7) through the notch (21).

11. The chip preparation method according to claim 9, characterized in that: The second top layer of the semiconductor layer structure (15) is a P-type cladding layer (6); In the step S4, when the portion of the dielectric layer close to the front cavity surface is thinned to zero thickness, a notch (21) is formed on the dielectric layer, and the notch (21) is closer to the front cavity surface than the window (18); The step S4 further comprises: after the step of thinning the portion of the dielectric layer close to the front cavity surface, a step of forming a concave portion (22) extending to the P cladding layer on the top surface of the ridge waveguide structure (14); In the step S5, the step of preparing the heat dissipation structure (9) on the dielectric layer after the thinning process is replaced by preparing the heat dissipation structure (9) on the bottom surface of the recess (22) through the notch (21).

12. The chip preparation method according to any one of claims 9 to 11, characterized in that: The chip preparation method further comprises the following steps after step S2: From top to bottom, the ridge waveguide structure (14) is etched to form a groove (11), wherein the groove (11) is located at a heat-insulating gap between a preset conductive structure (8) position and a preset heat dissipation structure (9) position.

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