A method for preparing an inverted light emitting diode and an inverted light emitting diode

Abstract

The present invention provides a method for preparing an inverted light-emitting diode and an inverted light-emitting diode, the preparation method comprising: providing a substrate, depositing an epitaxial layer on the surface of the substrate, forming an N-type semiconductor layer conductive step in a partial area of ​​the epitaxial layer surface, and preparing a current expansion layer in a partial area; sequentially preparing a first insulating layer and a Bragg reflection layer on the surface of the N-type semiconductor layer conductive step and the current expansion layer, forming a Bragg reflection layer through hole with inclined side walls on the Bragg reflection layer, the inclined side walls including a straight line segment and an arc segment; forming a first insulating layer through hole with straight inclined side walls in the Bragg reflection layer through hole; finally, sequentially depositing a metal reflection layer, a second insulating layer, a connecting metal layer, a third insulating layer and a pad layer on the epitaxial layer after the first insulating layer through hole is formed, so as to obtain a target inverted light-emitting diode. The inverted light-emitting diode prepared by the present application reduces the agglomeration of Ag metal in the reflection layer and improves the product quality.

Description

Technical Field

[0001] The invention relates to the field of optoelectronic technology, and in particular to a method for preparing an inverted light emitting diode and the inverted light emitting diode. Background Art

[0002] Flip-chip LED chips are widely used due to their advantages such as back-emitting light, strong heat dissipation, good weldability, large thrust, and strong reliability. Initially, people used Bragg reflectors as reflectors to enable flip-chip LEDs to emit light from the back. In recent years, people have begun to add Bragg reflector layers to the Bragg reflectors to improve the reflection effect of the reflectors, and ultimately improve the external quantum efficiency of flip-chip LED chips.

[0003] After the silver reflector is prepared, the existing flip-chip silver mirror reflective diode chip needs to use the PECVD (plasma enhanced chemical vapor deposition) process to prepare a SiO2 film layer on the silver reflector as an insulating layer. However, during the preparation of the insulating layer, Ag metal is easily oxidized and agglomerated in the Bragg reflector layer through-holes and the insulating layer through-holes below, affecting product quality. Summary of the invention

[0004] Based on this, the purpose of the present invention is to provide a method for preparing a flip-chip light emitting diode and a flip-chip light emitting diode to solve the problems existing in the prior art.

[0005] The present invention provides a method for preparing a flip-chip light-emitting diode, comprising the following steps:

[0006] S10, providing a substrate, and depositing an epitaxial layer on a surface of the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially deposited on the substrate;

[0007] S20, etching a partial area of ​​the surface of the epitaxial layer to a depth down to the N-type semiconductor layer to form a conductive step of the N-type semiconductor layer, and preparing a current spreading layer on other unetched areas of the surface of the epitaxial layer;

[0008] S30, sequentially preparing a first insulating layer and a Bragg reflection layer on the surface of the N-type semiconductor layer conductive step and the current spreading layer, wherein the first insulating layer is a SiO2 insulating layer generated using SiH4 and N2O as raw materials, and during the deposition of the SiO2 insulating layer, the SiH4 flow rate increases linearly with the deposition time, and the N2O flow rate decreases linearly with the deposition time;

[0009] S40, forming a Bragg reflector through hole on the Bragg reflector layer by using an inductively coupled plasma etching process, wherein the sidewall of the Bragg reflector through hole is an inclined sidewall, and the inclined sidewall includes a straight line segment connected to the bottom of the Bragg reflector through hole and an arc segment connected to the top of the Bragg reflector through hole;

[0010] S50, removing the first insulating layer at the bottom of the Bragg reflective layer through hole to form a first insulating layer through hole on the first insulating layer, wherein the size of the first insulating layer through hole is smaller than the size of the Bragg reflective layer through hole, and the sidewall of the first insulating layer through hole is a linear inclined sidewall;

[0011] S60, depositing a metal reflective layer, a second insulating layer, a connecting metal layer, a third insulating layer and a pad layer in sequence on the epitaxial layer after forming the through hole of the first insulating layer, so as to obtain a target flip-chip light emitting diode.

[0012] Preferably, the step of etching a partial area of ​​the surface of the epitaxial layer to a depth up to the N-type semiconductor layer to form a conductive step of the N-type semiconductor layer, and preparing a current spreading layer on other unetched areas of the surface of the epitaxial layer comprises:

[0013] Coating a photoresist on the surface of the P-type semiconductor layer, then exposing and developing to remove a portion of the photoresist and expose a portion of the P-type semiconductor layer;

[0014] Performing inductively coupled plasma etching on the exposed P-type semiconductor layer, removing the exposed P-type semiconductor layer and the active light-emitting layer at the bottom thereof in sequence, and then removing the remaining photoresist on the P-type semiconductor layer to obtain a conductive step of the N-type semiconductor layer;

[0015] Depositing an indium tin oxide layer on the surface of the conductive step of the N-type semiconductor layer and the remaining P-type semiconductor layer by a magnetron sputtering process, coating the indium tin oxide layer with a photoresist, exposing and developing to remove a portion of the photoresist, and exposing a portion of the indium tin oxide layer;

[0016] An indium tin oxide etching solution is used to remove the exposed indium tin oxide layer, and then the remaining photoresist on the indium tin oxide layer is removed to prepare a current spreading layer on the P-type semiconductor layer.

[0017] Preferably, the step of sequentially preparing a first insulating layer and a Bragg reflection layer on the surface of the N-type semiconductor layer conductive step and the current spreading layer comprises:

[0018] Depositing SiO2 as a first insulating layer on the surface of the N-type semiconductor layer conductive step and the current spreading layer by using a PECVD process;

[0019] In the process of preparing the SiO2 insulating layer, the SiH4 flow rate is 150sccm-300sccm, and the SiH4 flow rate increases linearly with the deposition time, with an increase rate of 1sccm / min-2sccm / min;

[0020] The N2O flow rate is 1500sccm-3000sccm, and the N2O flow rate decreases linearly with the deposition time, and the decrease rate is 5sccm / min-10sccm / min;

[0021] The deposition temperature decreases linearly with the deposition time, and the decrease rate is 0.5 ℃ / min-1 ℃ / min;

[0022] A plurality of cycles of TiO2 and SiO2 stacking layers are alternately evaporated on the surface of the first insulating layer by electron beam evaporation process as a Bragg reflection layer, and the cycle of the alternate evaporation of TiO2 and SiO2 is 2-10.

[0023] Preferably, the step of forming a Bragg reflector through hole on the Bragg reflector by using an inductively coupled plasma etching process comprises:

[0024] Coating a photoresist on the surface of the Bragg reflection layer, and then removing a portion of the photoresist on the Bragg reflection layer by exposure and development;

[0025] Open the upper electrode of the inductively coupled plasma etching chamber, introduce Ar2 and CF4 to perform the first etching, the first etching time is 5s-10s;

[0026] The upper electrode and the lower electrode are turned on at the same time, and Ar2 and CF4 are introduced to perform the second etching. During the second etching process, the Ar2 flow rate is a constant value, and the CF4 flow rate decreases linearly with the etching time;

[0027] Keeping the upper electrode and the lower electrode open, passing Ar2, CF4 and Cl2 to perform the third etching, during which the Ar2 flow rate is a constant value, the CF4 flow rate decreases linearly with the etching time, and the Cl2 flow rate increases linearly with the etching time;

[0028] Keep the upper electrode and the lower electrode open, and introduce Ar2, CF4, Cl2 and O2 to perform the fourth etching. During the fourth etching process, the Ar2 flow rate, CF4 flow rate and Cl2 flow rate are consistent with the flow rate at the end of the third etching, and the O2 flow rate decreases linearly with the etching time.

[0029] Preferably, during the first etching process, the Ar2 flow rate is 15 sccm-25 sccm, and the CF4 flow rate is 50 sccm-200 sccm;

[0030] In the second etching process, the Ar2 flow rate is 15sccm-25sccm, and the CF4 flow rate is 10sccm-200sccm;

[0031] In the third etching process, the Ar2 flow rate is 15 sccm-25 sccm, the CF4 flow rate is 50 sccm-100 sccm, and the Cl2 flow rate is 100 sccm-150 sccm;

[0032] During the fourth etching process, the O2 flow rate is 2 sccm-10 sccm.

[0033] Preferably, during the first etching process, the power of the upper electrode is 200W-600W;

[0034] In the second etching process, the power of the upper electrode increases linearly with the etching time, and the power of the lower electrode decreases linearly with the etching time. The power of the upper electrode is 200W-600W, and the power of the lower electrode is 150W-300W.

[0035] In the third etching process, the power of the upper electrode is greater than the power of the upper electrode in the second etching and increases linearly with the etching time, the power of the lower electrode is less than the power of the lower electrode in the second etching and decreases linearly with the etching time, the power of the upper electrode is 600W-1000W, and the power of the lower electrode is 50W-300W;

[0036] During the fourth etching process, the power of the upper electrode and the power of the lower electrode remain consistent with the power at the end of the third etching and are constant values.

[0037] Preferably, before the step of opening the upper electrode of the inductively coupled plasma etching chamber, introducing Ar2 and CF4 for the first etching, wherein the first etching time is 5s-10s, the method further comprises: introducing N2 into the inductively coupled plasma etching chamber for a purge cleaning, wherein the N2 flow rate is 150sccm-300sccm, and the purge time is 60s-90s;

[0038] While keeping the upper electrode and the lower electrode open, Ar2, CF4, Cl2 and O2 are introduced to perform the fourth etching. During the fourth etching process, the Ar2 flow rate, the CF4 flow rate and the Cl2 flow rate are consistent with the flow rate at the end of the third etching, and the O2 flow rate decreases linearly with the etching time. It also includes: closing the upper electrode and the lower electrode, and introducing N2 into the inductively coupled plasma etching chamber for secondary purge cleaning. During the secondary purge cleaning process, the N2 flow rate is 150sccm-300sccm, and the purge time is 60s-90s.

[0039] Preferably, a first angle between the straight section of the inclined side wall of the Bragg reflector layer through hole and its bottom is 10°-25°, and a second angle between the side wall of the first insulating layer through hole and its bottom is 20°-35°, the first angle is smaller than the second angle, and the difference between the two is greater than 10°.

[0040] Preferably, the distance between the top edge of the through hole in the first insulating layer and the bottom edge of the through hole in the Bragg reflective layer is greater than 3 μm.

[0041] The present application also provides a flip-chip light emitting diode, which is prepared using the above-mentioned flip-chip light emitting diode preparation method.

[0042] The beneficial effects of the present invention are as follows: the method for preparing a flip-chip light-emitting diode provided by the present application first provides a substrate, and deposits an epitaxial layer on the surface of the substrate; prepares an N-type semiconductor layer conductive step and a current spreading layer on the surface of the epitaxial layer; prepares a first insulating layer on the surface of the epitaxial layer based on a specific PECVD process, and then prepares a Bragg reflective layer on the first insulating layer; etches a Bragg reflective layer through hole on the Bragg reflective layer based on a specific inductively coupled plasma etching process, wherein the side wall of the Bragg reflective layer through hole is an inclined side wall, and the inclined side wall includes a straight line segment connected to the bottom of the Bragg reflective layer through hole and an arc segment connected to the top of the Bragg reflective layer through hole; a first insulating layer through hole is formed on the first insulating layer The size of the through hole of the first insulating layer is smaller than that of the through hole of the Bragg reflector layer, and the side wall of the through hole of the first insulating layer is a straight inclined side wall; then a metal reflector layer, a second insulating layer, a connecting metal layer, a third insulating layer and a pad layer are prepared on the surface of the epitaxial layer to obtain a target flip-chip light-emitting diode; in the present application, the inclined side wall of the through hole of the Bragg reflector layer formed includes a straight line segment and an arc segment, and the side wall of the through hole of the first insulating layer formed is a straight inclined side wall; so that in the subsequent deposition of SiO2 film layer on the metal reflector layer by PECVD process to form the second insulating layer, it is not easy for Ag metal to be oxidized and agglomerated in the Bragg reflector layer through hole and the insulating layer through hole below, thereby improving product quality.

[0043] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A flow chart of the method for preparing a flip-chip light-emitting diode provided by the present invention;

[0045] Figure 2 A schematic diagram of the cross-sectional structure of a flip-chip light-emitting diode prepared by the present invention;

[0046] Figure 3It is a schematic diagram of the enlarged structure of the first insulating layer through hole and the Bragg reflection layer through hole of the flip-chip light emitting diode prepared by the present invention.

[0047] Description of main component symbols:

[0048] 10. Substrate; 111. N-type semiconductor layer; 112. Active light-emitting layer; 113. P-type semiconductor layer; 114. N-type semiconductor layer conductive step; 12. Current spreading layer; 13. First insulating layer; 131. First insulating layer through hole; 14. Bragg reflection layer; 141. Bragg reflection layer through hole; 15. Metal reflection layer; 16. Second insulating layer; 17. Connecting metal layer; 18. Third insulating layer; 19. Pad layer.

[0049] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0050] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0051] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing optional embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0053] Example 1

[0054] The present invention provides a method for preparing a flip-chip light-emitting diode, such as Figure 1 As shown, the method for preparing a flip-chip light-emitting diode includes S10 to S60:

[0055] S10, providing a substrate, and depositing an epitaxial layer on a surface of the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially deposited on the substrate;

[0056] In a specific implementation, an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 are sequentially prepared on a substrate 10, and the substrate may be one of GaN, Al2O3, and Si.

[0057] S20, etching a partial area of ​​the surface of the epitaxial layer to a depth down to the N-type semiconductor layer to form a conductive step of the N-type semiconductor layer, and preparing a current spreading layer on other unetched areas of the surface of the epitaxial layer;

[0058] Optionally, S20 specifically includes:

[0059] Coating a photoresist on the surface of the P-type semiconductor layer, then exposing and developing to remove a portion of the photoresist and expose a portion of the P-type semiconductor layer;

[0060] Performing inductively coupled plasma etching on the exposed P-type semiconductor layer to sequentially remove the exposed P-type semiconductor layer and the active light-emitting layer at the bottom thereof, and then removing the remaining photoresist on the P-type semiconductor layer to obtain an N-type semiconductor layer conductive step 114;

[0061] Depositing an indium tin oxide layer on the surface of the conductive step of the N-type semiconductor layer and the remaining P-type semiconductor layer by a magnetron sputtering process, coating the indium tin oxide layer with a photoresist, exposing and developing to remove a portion of the photoresist, and exposing a portion of the indium tin oxide layer;

[0062] An indium tin oxide etching solution is used to remove the exposed indium tin oxide layer, and then the remaining photoresist on the indium tin oxide layer is removed to prepare a current spreading layer 12 on the P-type semiconductor layer.

[0063] S30, sequentially preparing a first insulating layer and a Bragg reflection layer on the surface of the N-type semiconductor layer conductive step and the current spreading layer, wherein the first insulating layer is a SiO2 insulating layer generated using SiH4 and N2O as raw materials, and during the deposition of the SiO2 insulating layer, the SiH4 flow rate increases linearly with the deposition time, and the N2O flow rate decreases linearly with the deposition time;

[0064] Optionally, S30 specifically includes:

[0065] Depositing SiO2 as a first insulating layer 13 on the surface of the N-type semiconductor layer conductive step and the current spreading layer by using a PECVD process;

[0066] In the process of preparing the SiO2 insulating layer, the SiH4 flow rate is 150sccm-300sccm, and the SiH4 flow rate increases linearly with the deposition time, with an increase rate of 1sccm / min-2sccm / min;

[0067] The N2O flow rate is 1500sccm-3000sccm, and the N2O flow rate decreases linearly with the deposition time, and the decrease rate is 5sccm / min-10sccm / min;

[0068] The deposition temperature decreases linearly with the deposition time, and the decrease rate is 0.5 ℃ / min-1 ℃ / min;

[0069] A plurality of cycles of TiO2 and SiO2 stacking layers are alternately evaporated on the surface of the first insulating layer by electron beam evaporation process as a Bragg reflection layer, and the cycle of the alternate evaporation of TiO2 and SiO2 is 2-10.

[0070] In this embodiment, by adjusting the coating parameters for preparing the first insulating layer 13 , the through hole angle of the first insulating layer subsequently prepared by using BOE (Buffered Oxide Etch) etching solution can be between 20° and 35°.

[0071] S40, forming a Bragg reflector through hole on the Bragg reflector layer by using an inductively coupled plasma etching process, wherein the sidewall of the Bragg reflector through hole is an inclined sidewall, and the inclined sidewall includes a straight line segment connected to the bottom of the Bragg reflector through hole and an arc segment connected to the top of the Bragg reflector through hole;

[0072] Optionally, S40 specifically includes:

[0073] Coating a photoresist on the surface of the Bragg reflection layer, and then removing a portion of the photoresist on the Bragg reflection layer by exposure and development;

[0074] The upper electrode of the inductively coupled plasma etching chamber is turned on, and Ar2 and CF4 are introduced for the first etching. The first etching time is 5s-10s, the Ar2 flow rate is 15sccm-25sccm, the CF4 flow rate is 50sccm-200sccm, and the power of the upper electrode is 200W-600W.

[0075] The upper electrode and the lower electrode are opened at the same time, and Ar2 and CF4 are introduced for the second etching. During the second etching process, the Ar2 flow rate is a constant, and the CF4 flow rate decreases linearly with the etching time; the Ar2 flow rate is 15sccm-25sccm, and the CF4 flow rate is 10sccm-200sccm; the power of the upper electrode increases linearly with the etching time, and the power of the lower electrode decreases linearly with the etching time, the power of the upper electrode is 200W-600W, and the power of the lower electrode is 150W-300W; through the above-mentioned first etching and second etching, a straight line segment of the side wall of the Bragg reflection layer through hole is etched.

[0076] Keep the upper electrode and the lower electrode open, introduce Ar2, CF4 and Cl2 to perform the third etching. During the third etching process, the Ar2 flow rate is a constant value, the CF4 flow rate decreases linearly with the etching time, and the Cl2 flow rate increases linearly with the etching time; the Ar2 flow rate is 15sccm-25sccm, the CF4 flow rate is 50sccm-100sccm, and the Cl2 flow rate is 100sccm-150sccm; the power of the upper electrode is greater than the power of the upper electrode in the second etching and increases linearly with the etching time, the power of the lower electrode is less than the power of the lower electrode in the second etching and decreases linearly with the etching time, the power of the upper electrode is 600W-1000W, and the power of the lower electrode is 50W-300W;

[0077] The upper electrode and the lower electrode are kept open, and Ar2, CF4, Cl2 and O2 are introduced to perform the fourth etching. During the fourth etching process, the Ar2 flow rate, the CF4 flow rate and the Cl2 flow rate are consistent with the flow rate at the end of the third etching, and the O2 flow rate decreases linearly with the etching time; the O2 flow rate is 2sccm-10sccm; the power of the upper electrode and the power of the lower electrode are consistent with the power at the end of the third etching and are constant. Through the third etching and the fourth etching, the arc segment of the side wall of the Bragg reflector layer through hole is etched.

[0078] After the first etching, the second etching, the third etching and the fourth etching are completed, a Bragg reflection layer through hole 141 is formed on the Bragg reflection layer 14, the first insulating layer under the Bragg reflection layer through hole is exposed, and then the remaining photoresist is removed.

[0079] In some optional embodiments, before performing the first etching, the method for preparing a flip-chip light-emitting diode further includes: introducing N2 into the inductively coupled plasma etching chamber for a purge cleaning, during which the flow rate of N2 is 150sccm-300sccm, and the purge time is 60s-90s; after performing the fourth etching, the method for preparing a flip-chip light-emitting diode further includes: closing the upper electrode and the lower electrode, introducing N2 into the inductively coupled plasma etching chamber for a second purge cleaning, during which the flow rate of N2 is 150sccm-300sccm, and the purge time is 60s-90s. Through two purge cleanings, impurities in the inductively coupled plasma etching chamber are reduced, and contamination is prevented during the etching process, which affects product quality.

[0080] S50, removing the first insulating layer at the bottom of the Bragg reflective layer through hole to form a first insulating layer through hole on the first insulating layer, wherein the size of the first insulating layer through hole is smaller than the size of the Bragg reflective layer through hole, and the sidewall of the first insulating layer through hole is a linear inclined sidewall;

[0081] Optionally, S50 specifically includes:

[0082] Photoresist is coated on the surface of the Bragg reflective layer and the through hole of the Bragg reflective layer, and then the photoresist in the through hole of the Bragg reflective layer is partially removed by exposure and development to expose the first insulating layer under the through hole of the Bragg reflective layer, and then the exposed first insulating layer is removed by BOE etching solution to form the first insulating layer through hole 131, and then the remaining photoresist is removed.

[0083] Optionally, in this embodiment, if Figure 2 and Figure 3 As shown, a first angle between the straight section of the inclined side wall of the Bragg reflector layer through hole and its bottom is 10°-25°, a second angle between the side wall of the first insulating layer through hole and its bottom is 20°-35°, the first angle is smaller than the second angle, and the difference between the two is greater than 10°; the top edge of the first insulating layer through hole is greater than 3 μm away from the bottom edge of the Bragg reflector layer through hole.

[0084] S60, depositing a metal reflective layer, a second insulating layer, a connecting metal layer, a third insulating layer and a pad layer in sequence on the epitaxial layer after forming the through hole of the first insulating layer, so as to obtain a target flip-chip light emitting diode.

[0085] Optionally, S60 specifically includes:

[0086] Apply photoresist on the epitaxial layer after step S50, then remove part of the photoresist by exposure and development, use electron beam evaporation process to sequentially evaporate Ag / Ni / Ti / Ni / Ti / Ni / Ti / Ni / Ti metal as the metal reflective layer 15, then use blue film stripping process to remove the metal on the photoresist, and then remove the photoresist;

[0087] Next, a SiO2 film layer is deposited on the metal reflective layer 15 by using a PECVD process to form a second insulating layer 16, and then a photoresist is coated on the surface of the second insulating layer, and a portion of the photoresist is removed by exposure and development to expose a portion of the second insulating layer, and then a BOE etching solution is used to remove the exposed second insulating layer, and then the photoresist is removed to form a second insulating layer through hole;

[0088] Apply photoresist on the second insulating layer and the surface of the through hole of the second insulating layer, expose and develop to remove part of the photoresist, then use electron beam evaporation process to sequentially evaporate Al / Ti / Al / Ti / Al / Ti / Pt / Ti metals to form a connecting metal layer 17, use a blue film stripping process to remove the metal on the photoresist, and remove the photoresist;

[0089] Next, SiO2 is deposited as a third insulating layer 18 on the connection metal layer 17 and the surface of the second insulating layer not covered by the connection metal layer by using a PECVD process, a photoresist is coated on the third insulating layer, and then a portion of the photoresist is removed by exposure and development to expose a portion of the third insulating layer, and then a BOE etching solution is used to remove the exposed third insulating layer to form a third insulating layer through hole, and the photoresist is removed;

[0090] Photoresist is coated on the surface of the third insulating layer and the through hole of the third insulating layer, and part of the photoresist is removed by exposure and development. Al / Ti / Al / Ti / Ni / Ti / Ni / Ti / Ni / AuSn metals are sequentially evaporated by electron beam evaporation process as pad layer 19, and the metal on the photoresist is removed by blue film stripping process. The photoresist is removed to obtain the target flip-chip light-emitting diode.

[0091] In summary, the method for preparing a flip-chip light-emitting diode provided in the present application first provides a substrate, and deposits an epitaxial layer on the surface of the substrate; prepares an N-type semiconductor layer conductive step and a current spreading layer on the surface of the epitaxial layer; prepares a first insulating layer on the surface of the epitaxial layer based on a specific PECVD process, and then prepares a Bragg reflective layer on the first insulating layer; etches a Bragg reflective layer through hole on the Bragg reflective layer based on a specific inductively coupled plasma etching process, wherein the side wall of the Bragg reflective layer through hole is an inclined side wall, and the inclined side wall includes a straight line segment connected to the bottom of the Bragg reflective layer through hole and an arc segment connected to the top of the Bragg reflective layer through hole; forms a first insulating layer through hole in the Bragg reflective layer through hole, and a first insulating layer through hole is formed in the Bragg reflective layer through hole. The size of an insulating layer through hole is smaller than that of a Bragg reflective layer through hole, and the side wall of the first insulating layer through hole is a straight inclined side wall; then a metal reflective layer, a second insulating layer, a connecting metal layer, a third insulating layer and a pad layer are prepared on the surface of the epitaxial layer to obtain a target flip-chip light-emitting diode; in the present application, the inclined side wall of the formed Bragg reflective layer through hole includes a straight line segment and an arc segment, and the side wall of the formed first insulating layer through hole is a straight inclined side wall; so that in the subsequent process of depositing a SiO2 film layer on the metal reflective layer by a PECVD process to form a second insulating layer, oxidation and agglomeration of Ag metal are not likely to occur at the lower Bragg reflective layer through hole and the insulating layer through hole, thereby improving product quality.

[0092] Example 2

[0093] The present application also provides a flip-chip light emitting diode, which is manufactured using the above-mentioned flip-chip light emitting diode manufacturing method.

[0094] It should be noted that the above implementation process is only to illustrate the feasibility of the present application, but it does not mean that the flip-chip light-emitting diode of the present application has only the above-mentioned implementation processes. On the contrary, as long as the flip-chip light-emitting diode of the present application can be implemented, it can be included in the feasible implementation scheme of the present application. In addition, the structural part in the embodiment of the present invention corresponds to the preparation method part of the present invention, and the specific implementation details are also the same, which will not be repeated here.

[0095] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0096] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the attached claims.

Claims

1. A method for preparing a flip-chip light-emitting diode, characterized in that: The following steps are involved: S10, providing a substrate, and depositing an epitaxial layer on a surface of the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer sequentially deposited on the substrate; S20, etching a partial area of ​​the surface of the epitaxial layer to a depth down to the N-type semiconductor layer to form a conductive step of the N-type semiconductor layer, and preparing a current spreading layer on other unetched areas of the surface of the epitaxial layer; S30, sequentially preparing a first insulating layer and a Bragg reflection layer on the surface of the N-type semiconductor layer conductive step and the current spreading layer, wherein the first insulating layer is a SiO2 insulating layer generated using SiH4 and N2O as raw materials, and during the deposition of the SiO2 insulating layer, the SiH4 flow rate increases linearly with the deposition time, and the N2O flow rate decreases linearly with the deposition time; S40, forming a Bragg reflector through hole on the Bragg reflector layer by using an inductively coupled plasma etching process, wherein the sidewall of the Bragg reflector through hole is an inclined sidewall, and the inclined sidewall includes a straight line segment connected to the bottom of the Bragg reflector through hole and an arc segment connected to the top of the Bragg reflector through hole; S50, removing the first insulating layer at the bottom of the Bragg reflective layer through hole to form a first insulating layer through hole on the first insulating layer, wherein the size of the first insulating layer through hole is smaller than the size of the Bragg reflective layer through hole, and the sidewall of the first insulating layer through hole is a linear inclined sidewall; S60, sequentially depositing a metal reflective layer, a second insulating layer, a connecting metal layer, a third insulating layer and a pad layer on the epitaxial layer after forming the through hole of the first insulating layer, so as to obtain a target flip-chip light-emitting diode; A first angle between the straight line segment of the inclined side wall of the Bragg reflection layer through hole and its bottom is 10°-25°, and a second angle between the side wall of the first insulation layer through hole and its bottom is 20°-35°. The first angle is smaller than the second angle, and the difference between the two is greater than 10°.

2. The method for preparing a flip-chip light-emitting diode according to claim 1, characterized in that: The step of etching a partial area of ​​the surface of the epitaxial layer to a depth of the N-type semiconductor layer to form a conductive step of the N-type semiconductor layer, and preparing a current spreading layer on other unetched areas of the surface of the epitaxial layer comprises: Coating a photoresist on the surface of the P-type semiconductor layer, then exposing and developing to remove a portion of the photoresist and expose a portion of the P-type semiconductor layer; Performing inductively coupled plasma etching on the exposed P-type semiconductor layer, removing the exposed P-type semiconductor layer and the active light-emitting layer at the bottom thereof in sequence, and then removing the remaining photoresist on the P-type semiconductor layer to obtain a conductive step of the N-type semiconductor layer; Depositing an indium tin oxide layer on the surface of the conductive step of the N-type semiconductor layer and the remaining P-type semiconductor layer by a magnetron sputtering process, coating the indium tin oxide layer with a photoresist, exposing and developing to remove a portion of the photoresist, and exposing a portion of the indium tin oxide layer; An indium tin oxide etching solution is used to remove the exposed indium tin oxide layer, and then the remaining photoresist on the indium tin oxide layer is removed to prepare a current spreading layer on the P-type semiconductor layer.

3. The method for preparing a flip-chip light-emitting diode according to claim 1, characterized in that: The step of sequentially preparing a first insulating layer and a Bragg reflection layer on the surface of the N-type semiconductor layer conductive step and the current spreading layer comprises: Depositing SiO2 as a first insulating layer on the surface of the N-type semiconductor layer conductive step and the current spreading layer by using a PECVD process; In the process of preparing the SiO2 insulating layer, the SiH4 flow rate is 150sccm-300sccm, and the SiH4 flow rate increases linearly with the deposition time, with an increase rate of 1sccm / min-2sccm / min; The N2O flow rate is 1500sccm-3000sccm, and the N2O flow rate decreases linearly with the deposition time, and the decrease rate is 5sccm / min-10sccm / min; The deposition temperature decreases linearly with the deposition time, and the decrease rate is 0.5 ℃ / min-1 ℃ / min; A plurality of cycles of TiO2 and SiO2 stacking layers are alternately evaporated on the surface of the first insulating layer by electron beam evaporation process as a Bragg reflection layer, and the cycle of the alternate evaporation of TiO2 and SiO2 is 2-10.

4. The method for preparing a flip-chip light-emitting diode according to claim 1, characterized in that: The step of forming a Bragg reflection layer through hole on the Bragg reflection layer by using an inductively coupled plasma etching process comprises: Coating a photoresist on the surface of the Bragg reflection layer, and then removing a portion of the photoresist on the Bragg reflection layer by exposure and development; Open the upper electrode of the inductively coupled plasma etching chamber, introduce Ar2 and CF4 to perform the first etching, the first etching time is 5s-10s; The upper electrode and the lower electrode are turned on at the same time, and Ar2 and CF4 are introduced to perform the second etching. During the second etching process, the Ar2 flow rate is a constant value, and the CF4 flow rate decreases linearly with the etching time; Keeping the upper electrode and the lower electrode open, passing Ar2, CF4 and Cl2 to perform the third etching, during which the Ar2 flow rate is a constant value, the CF4 flow rate decreases linearly with the etching time, and the Cl2 flow rate increases linearly with the etching time; Keep the upper electrode and the lower electrode open, and introduce Ar2, CF4, Cl2 and O2 to perform the fourth etching. During the fourth etching process, the Ar2 flow rate, CF4 flow rate and Cl2 flow rate are consistent with the flow rate at the end of the third etching, and the O2 flow rate decreases linearly with the etching time.

5. The method for preparing a flip-chip light-emitting diode according to claim 4, characterized in that: In the first etching process, the Ar2 flow rate is 15sccm-25sccm, and the CF4 flow rate is 50sccm-200sccm; In the second etching process, the Ar2 flow rate is 15sccm-25sccm, and the CF4 flow rate is 10sccm-200sccm; In the third etching process, the Ar2 flow rate is 15 sccm-25 sccm, the CF4 flow rate is 50 sccm-100 sccm, and the Cl2 flow rate is 100 sccm-150 sccm; During the fourth etching process, the O2 flow rate is 2 sccm-10 sccm.

6. The method for preparing a flip-chip light-emitting diode according to claim 4, characterized in that: During the first etching process, the power of the upper electrode is 200W-600W; In the second etching process, the power of the upper electrode increases linearly with the etching time, and the power of the lower electrode decreases linearly with the etching time. The power of the upper electrode is 200W-600W, and the power of the lower electrode is 150W-300W. In the third etching process, the power of the upper electrode is greater than the power of the upper electrode in the second etching and increases linearly with the etching time, the power of the lower electrode is less than the power of the lower electrode in the second etching and decreases linearly with the etching time, the power of the upper electrode is 600W-1000W, and the power of the lower electrode is 50W-300W; During the fourth etching process, the power of the upper electrode and the power of the lower electrode remain consistent with the power at the end of the third etching and are constant values.

7. The method for preparing a flip-chip light-emitting diode according to claim 4, characterized in that: Before the step of opening the upper electrode of the inductively coupled plasma etching chamber, introducing Ar2 and CF4 to perform a first etching, wherein the first etching time is 5s-10s, the step further includes: introducing N2 into the inductively coupled plasma etching chamber for a purge cleaning, wherein the N2 flow rate is 150sccm-300sccm, and the purge time is 60s-90s; While keeping the upper electrode and the lower electrode open, Ar2, CF4, Cl2 and O2 are introduced to perform the fourth etching. During the fourth etching process, the Ar2 flow rate, the CF4 flow rate and the Cl2 flow rate are consistent with the flow rate at the end of the third etching, and the O2 flow rate decreases linearly with the etching time. It also includes: closing the upper electrode and the lower electrode, and introducing N2 into the inductively coupled plasma etching chamber for secondary purge cleaning. During the secondary purge cleaning process, the N2 flow rate is 150sccm-300sccm, and the purge time is 60s-90s.

8. The method for preparing a flip-chip light-emitting diode according to claim 1, characterized in that: The distance between the top edge of the first insulating layer through hole and the bottom edge of the Bragg reflective layer through hole is greater than 3 μm.

9. A flip-chip light emitting diode, characterized in that: The flip-chip light-emitting diode is prepared according to any one of claims 1 to 8.

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