Layout design method and system for integrated circuits

Abstract

The present invention discloses a layout design method and system for integrated circuits, and relates to the technical field of circuit design. The system significantly optimizes the integrated circuit design process through partitioning algorithms, layout optimization techniques and detailed routing strategies. The circuit module partitioning module uses heuristic methods and Kernighan-Lin algorithms to effectively divide the circuit into multiple regions, and determines the area configuration of each module through linear programming to ensure that the function and physical characteristics of each region are optimally matched. The preliminary layout planning module performs preliminary layout through a heuristic algorithm, and adopts a simulated annealing algorithm, combined with a cost function algorithm to optimize the initial position of the circuit module to minimize the total layout cost C. In addition, the global routing module uses the MazeRouting algorithm to optimize the routing path, avoid conflicts and reduce the routing length L, thereby improving manufacturing efficiency and cost control capabilities while ensuring circuit performance.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a layout design method and system for integrated circuits. Background Art

[0002] Integrated circuit layout refers to the process of arranging and connecting various electronic devices on silicon wafers or other semiconductor materials according to specific circuit patterns when designing and manufacturing integrated circuits IC. This process determines the relative position, spacing and connection method between electronic components, which directly affects the performance, power consumption, stability and manufacturing cost of the circuit. The main goal of integrated circuit layout design is to achieve the most complex and precise circuit functions within the limited silicon wafer area. Layout design needs to take into account factors such as signal transmission path, power distribution, heat dissipation requirements, and interconnection line length to ensure that the circuit can work stably and reliably, and can be implemented efficiently during the manufacturing process.

[0003] At present, integrated circuit design is becoming more and more complex, and layout systems need to effectively manage the complexity of large-scale circuits. With the increase in chip functions and integration, layout systems may face challenges in dealing with a large number of logic units, timing and power constraints, making layout optimization and adjustment difficult. At the same time, current layout systems may not fully consider the interaction of all rules when dealing with rule conflicts and optimizations. Designers need to repeatedly optimize layouts, which prolongs the design cycle and wastes resources, leading to the risk of potential layout defects and unstable circuit performance in the design. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present invention provides a layout design method and system for an integrated circuit, which solves the problems mentioned in the background technology.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: including a circuit table net input module, a circuit module division module, a preliminary layout planning module, a global routing module and an evaluation optimization module;

[0006] The circuit netlist input module is used to input the circuit netlist design tool in the integrated circuit layout design system, and to extract the required circuit description information from the output circuit description file;

[0007] The circuit module division module divides the circuit into multiple modules based on the circuit function and the circuit physical characteristics, and pre-processes the modules to calculate the initial area and shape of the modules;

[0008] The preliminary layout planning module is used to construct a cost function algorithm for the initial layout, calculate the initial position of the module, obtain the total layout cost C, and then perform a simulated annealing algorithm to calculate the probability P(E), and evaluate the acceptability of the new layout;

[0009] The global routing module is used to determine the main connection path optimization routing conflict, and use the detailed routing algorithm to calculate the total routing length L, and verify the circuit physical image and electrical rules of the layout to obtain the inspection results;

[0010] The evaluation and optimization module is used to combine the total layout cost C and the total wiring length L of the layout plan, perform associated calculations to obtain a comprehensive layout quality coefficient Z, and preset a layout quality threshold F1 and the obtained comprehensive layout quality coefficient Z for preliminary evaluation, and then input the total layout cost C and the total wiring length L into the design rule checking tool, output the rule checking result R, and perform an evaluation.

[0011] Preferably, the circuit table netlist input module extracts netlist information from the circuit description file through parsing tools EDIF and Verilog Netlist, and converts the circuit design data in the file into an internal data structure, wherein the netlist information includes circuit module information, circuit port definition and circuit connection relationship;

[0012] The circuit module information is used to identify and record the name, type and attributes of each circuit module;

[0013] The circuit port definition is used to extract the module's input and output port lists and their attributes;

[0014] The circuit connection relationship is used to establish a connection relationship between modules, including internal connections and interface connections between modules.

[0015] Preferably, the circuit module division module includes a module division unit and a preprocessing unit;

[0016] The module division unit is used to divide the circuit into several initial regions according to a certain heuristic method in the integrated circuit layout design, and iteratively improve the division using the Kernighan-Lin algorithm until a preset optimization goal is reached, and then the number of connections between the divided circuit modules is used to evaluate the boundary clarity and overlap of the divided circuit modules;

[0017] The preprocessing unit is used to determine the area configuration of each circuit module through a linear programming method and design constraints, wherein the design constraints include the circuit function and circuit physical characteristics of the circuit module, and calculate the initial shape of the circuit module using a CAD tool based on the circuit function and circuit physical characteristics of the circuit module.

[0018] Preferably, the preliminary layout planning module includes a preliminary layout generating unit and an optimized layout unit;

[0019] The preliminary layout generating unit is used to generate a preliminary layout using a heuristic algorithm, calculate the initial position of the circuit module by constructing a cost function of the initial layout, and obtain a total layout cost C;

[0020] The total layout cost C is obtained by the following algorithm formula;

[0021]

[0022] Where N represents the total number of circuit modules, wi represents the weight value of module i, and distance(m i ) represents the distance between circuit module i and the target position.

[0023] Preferably, the layout optimization unit includes an annealing optimization unit and a layout cost evaluation unit;

[0024] The annealing algorithm unit is used to perform difference processing based on the total cost C of the new and old layouts to obtain the cost difference △C, and then combine it with the current temperature T. The probability calculation formula in the simulated annealing algorithm is Boltzmann distribution, and obtain the probability P(E) to determine the probability of accepting the new layout;

[0025] The probability P(E) is obtained by the following algorithm formula:

[0026]

[0027] In the formula, P(E) is the probability of accepting the new layout, ΔC represents the cost difference between the new and old layouts, and the algorithm formula is: ΔC = C new (Total cost of new layout) - C current (total cost of old layout), T represents the current temperature, which is used to adjust the probability of the algorithm accepting a worse solution during the optimization process and is obtained through the cooling plan, and exp represents the exponential function;

[0028] The layout cost evaluation unit is used to preset a layout threshold r, and then evaluate the obtained probability P(E) and the layout threshold r to analyze the acceptability of the new layout. The specific evaluation method is as follows;

[0029] When the probability P(E)>layout threshold r, the new layout is rejected and the current layout remains unchanged;

[0030] When the probability P(E) ≤ the layout threshold r, the new layout is accepted.

[0031] Preferably, the global routing module includes a global routing unit and a detailed routing unit;

[0032] The global routing unit is used to optimize the layout of the circuit module through the optimization layout unit, and then use the global routing algorithm based on MazeRouting to further divide the divided circuit module area into grids, apply breadth-first search on the grids to find the path from the output end of the circuit module to the input end of another circuit module, and mark the used grid units to avoid conflicts;

[0033] The detailed routing unit is used to further optimize each routing path based on the global routing, and to quantify the quality of the routing by optimizing the objective function, including the routing length, delay and power consumption, and then to summarize and calculate the length of each path through the detailed routing algorithm to obtain the total routing length L;

[0034] The total wiring length L is obtained by the following algorithm unit;

[0035]

[0036] Where M represents the number of wiring paths, e represents the wiring edge, and the wiring edge e refers to the wire portion connecting the two endpoints. i ) represents the length of the i-th wiring.

[0037] Preferably, the evaluation and optimization module includes a preliminary evaluation and optimization unit and a rule detection unit;

[0038] The preliminary evaluation and optimization unit includes a comprehensive algorithm unit and an evaluation and optimization unit;

[0039] The comprehensive algorithm unit is used to perform dimensionless processing on the total layout cost C and the total wiring length L optimized by the simulated annealing algorithm, and then perform correlation calculation to obtain a comprehensive layout quality coefficient Z;

[0040] The comprehensive layout quality coefficient Z is obtained by the following algorithm formula:

[0041] Z=(a1*C)+(a2*L)+A;

[0042] In the formula, a1 and a2 represent the weight values ​​of the optimized layout total cost C and the total wiring length L, respectively, and a1+a2=1, the specific value of which is set by the user, and A represents the correction parameter.

[0043] Preferably, the evaluation and optimization unit is used to preset the layout quality threshold F1 according to the obtained comprehensive layout quality coefficient Z, perform preliminary comparative evaluation, and perform further optimization according to the evaluation result. The specific evaluation scheme is as follows;

[0044] When the comprehensive layout quality coefficient Z ≥ the layout quality threshold F1, it means that the layout of the current integrated circuit is normal, and then further circuit rule checking is performed;

[0045] When the comprehensive layout quality coefficient Z is less than the layout quality threshold F1, it indicates that the layout of the current integrated circuit is abnormal. At this time, the annealing algorithm and the detailed wiring algorithm are re-executed to iteratively optimize the layout quality.

[0046] Preferably, the rule detection unit is used to be triggered when the layout of the integrated circuit is normal, and further import the current layout total cost C and total wiring length L into the rule detection tool through the design rule detection tools Cadence, DRC, Synopsys and ICValidator. The tool automatically checks each physical object in the layout according to the rule base, and checks according to the rule set set by the user, and generates a rule check result R. If a place that does not meet the rules is detected, the tool will generate a conflict report to indicate the specific rule conflict and location;

[0047] The rule checking result R is as follows:

[0048] When the rule check result R=0, it means that the layout complies with all physical and electrical rules and enters the next stage of manufacturing preparation;

[0049] When the rule check result R=1, it means that the layout quality of the current integrated circuit is normal, but there is a rule conflict in the layout, and the designer needs to further adjust the layout.

[0050] A layout method for an integrated circuit, comprising the following steps:

[0051] S1. First, use EDIF and VerilogNetlist parsing tools to input the circuit netlist design tool, then extract the netlist information from the circuit description file and convert it into an internal data structure;

[0052] S2, using heuristic methods and Kernighan-Lin algorithm, divide the circuit into initial regions, evaluate the boundary clarity and overlap of the modules, determine the module area through linear programming, and calculate the initial shape using CAD tools;

[0053] S3. Use the heuristic algorithm to calculate the initial position of the module, obtain the total layout cost C, calculate the probability P(E) of accepting the new layout based on the cost difference △C and the current temperature T through the Boltzmann distribution in the annealing algorithm, and determine the acceptability of the new layout based on the layout threshold r;

[0054] S4. Use the MazeRouting algorithm to divide the module area into grids, find paths and avoid conflicts, optimize each routing path, quantify the routing quality, and calculate the total routing length L;

[0055] S5. Finally, calculate the comprehensive layout quality coefficient Z of the total layout cost C and the total wiring length L, evaluate whether it reaches the preset threshold F1, use the tool to check the layout, generate the rule check result R, and decide whether to make adjustments.

[0056] The present invention provides a layout design method and system for integrated circuits, which have the following beneficial effects:

[0057] (1) The system significantly optimizes the integrated circuit design process through partitioning algorithms, layout optimization techniques, and detailed routing strategies. The circuit module partitioning module uses heuristic methods and the Kernighan-Lin algorithm to effectively divide the circuit into multiple regions, and determines the area configuration of each module through linear programming to ensure that the function and physical characteristics of each region are optimally matched. The preliminary layout planning module uses a simulated annealing algorithm combined with a cost function algorithm to accurately calculate the initial position of the module to minimize the total layout cost C. In addition, the global routing module uses the MazeRouting algorithm to optimize the routing path, avoid conflicts, and reduce the routing length L, thereby improving manufacturing efficiency and cost control capabilities while ensuring circuit performance.

[0058] (2) The system uses EDIF and VerilogNetlist parsing tools to accurately extract netlist information from circuit description files, including circuit module information, port definitions, and connection relationships, to ensure data accuracy and integrity during the layout process. The circuit module partitioning module uses the module partitioning unit and the preprocessing unit to iteratively optimize the module partitioning through the Kernighan-Lin algorithm to ensure clear boundaries and minimal overlap between circuit modules. The evaluation and optimization module combines the comprehensive layout quality coefficient Z and the rule check result R to conduct a comprehensive evaluation of the layout, effectively identify and solve potential physical and electrical rule problems in the layout, and improve the reliability and manufacturability of the overall design.

[0059] (3) The system improves design efficiency and flexibility through detailed routing units and optimized layout units. The preliminary layout generation unit uses a heuristic algorithm to generate an initial layout, calculates the initial position of the module by constructing a cost function algorithm, and optimizes the layout based on a simulated annealing algorithm, making the design process more efficient and automated. The global routing unit uses an algorithm based on MazeRouting to optimize the routing path, reduce routing length and delay, and optimizes each path through a detailed routing algorithm, further improving routing quality and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a schematic diagram of the flow of the layout system for integrated circuits of the present invention;

[0061] Figure 2It is a schematic diagram of the steps of the layout method for integrated circuits of the present invention. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] Example 1

[0064] See also Figure 1 The present invention provides a layout system for integrated circuits. To achieve the above purpose, the present invention is implemented through the following technical solutions: including a circuit table net input module, a circuit module division module, a preliminary layout planning module, a global routing module and an evaluation optimization module;

[0065] The circuit netlist input module is used to input the circuit netlist design tool in the integrated circuit layout design system and extract the required circuit description information from the output circuit description file;

[0066] The circuit module division module divides the circuit into multiple modules based on the circuit function and circuit physical characteristics, and pre-processes the modules to calculate the initial area and shape of the modules;

[0067] The preliminary layout planning module is used to construct the cost function algorithm of the initial layout, calculate the initial position of the module, obtain the total layout cost C, and then use the simulated annealing algorithm to calculate the probability P(E), and evaluate the acceptability of the new layout;

[0068] The global routing module is used to determine the main connection path optimization routing conflicts, and use the detailed routing algorithm to calculate the total routing length L, and verify the layout circuit physical image and electrical rules to obtain the inspection results;

[0069] The evaluation and optimization module is used to combine the total layout cost C and the total wiring length L of the layout plan, perform associated calculations to obtain the comprehensive layout quality coefficient Z, and preset the layout quality threshold F1 and the obtained comprehensive layout quality coefficient Z for preliminary evaluation, and then input the total layout cost C and the total wiring length L into the design rule checking tool, output the rule checking result R, and perform an evaluation.

[0070] In this embodiment, the system provides accurate input data for the subsequent integrated circuit layout design process by efficiently extracting circuit description information through the circuit table network input module, avoiding manual input errors and duplication of work. Secondly, the circuit module division module effectively manages complex circuit structures through intelligent module division and preprocessing, allowing designers to focus on the optimization of the module rather than the overall complexity, thereby accelerating the design process. With the support of the preliminary layout planning module, the system optimizes the layout using the cost function algorithm and the simulated annealing algorithm to achieve faster and more cost-effective design solution generation. The global routing module further optimizes the circuit routing, reduces the conflict of the connection path, and ensures the physical and electrical rule compliance of the layout, thereby improving the reliability and stability of the design. Compared with traditional methods, these technical means greatly reduce the number of iterations and error rates of the design, and significantly improve the efficiency and quality level of the design. As a key link in the design process, the evaluation and optimization module realizes a comprehensive evaluation and optimization of the design solution through the calculation of the comprehensive layout quality coefficient and the application of the rule checking tool. This method of comprehensively considering the total layout cost and wiring length not only ensures the economic and functional requirements of the design, but also can predict potential problems in the early stage of the design, further reducing the risk of the design and the cost of subsequent corrections.

[0071] Example 2

[0072] This embodiment is explained in Example 1, please refer to Figure 1 ,Specifically: The circuit table input module extracts the ,netlist information from the circuit description file through the ,analysis tools EDIF and Verilog Netlist, and converts the circuit design data in the ,file into an internal data structure. The netlist information includes circuit module information, ,circuit port definitions and circuit connection relationships;

[0073] The circuit module information is used to identify and record the name, type and attributes of each circuit module;

[0074] Circuit port definition is used to extract the module's input and output port lists and their properties;

[0075] Circuit connection relationships are used to establish connections between modules, including internal connections and interface connections between modules.

[0076] The circuit module division module includes a module division unit and a preprocessing unit;

[0077] The module partitioning unit is used to divide the circuit into several initial regions according to a certain heuristic method in the integrated circuit layout design, and use the Kernighan-Lin algorithm to iteratively improve the partitioning until the preset optimization goal is reached, and then the number of connections between the divided circuit modules is evaluated to evaluate the boundary clarity and overlap of the divided circuit modules;

[0078] The preprocessing unit is used to determine the area configuration of each circuit module through a linear programming method and design constraints, the design constraints include circuit functions and circuit physical characteristics of the circuit module, and use CAD tools to calculate the initial shape of the circuit module based on the circuit functions and circuit physical characteristics of the circuit module.

[0079] In this embodiment, the system can efficiently extract netlist information from the circuit description file, including circuit module information, circuit port definition and connection relationship, by using parsing tools such as EDIF and Verilog Netlist through the circuit table net input module. This enables the system to accurately understand and process complex circuit structures, and provides accurate basic data for subsequent layout and optimization processes. Through circuit module information and port definition, designers can quickly identify and manage the functions and interfaces of each module, which is helpful for the subsequent refinement of module division and layout. Secondly, the circuit module division module plays a key role in the system, and effectively manages and optimizes the circuit layout through the collaborative work of the module division unit and the pre-processing unit. The module division unit uses heuristic methods such as Kernighan-Lin algorithm to divide the circuit into several initial areas, and iteratively improves the division results to achieve the preset optimization goals. This method not only improves the boundary clarity and reduces overlap between circuit modules, but also optimizes the structure of the internal connection of the circuit, which is conducive to the smooth progress of subsequent layout planning and wiring. The pre-processing unit accurately determines the area configuration and initial shape of each circuit module through linear programming and CAD tools, ensuring the physical feasibility and optimization effect of the layout.

[0080] Example 3

[0081] This embodiment is explained in Example 2. Please refer to Figure 1 ,Specifically: the preliminary layout planning module includes a preliminary layout ,generation unit and an optimization layout unit;

[0082] The preliminary layout generation unit is used to generate a preliminary layout using a heuristic algorithm, calculate the initial position of the circuit module by constructing a cost function of the initial layout, and obtain the total layout cost C;

[0083] The total layout cost C is obtained by the following algorithm formula;

[0084]

[0085] Where N represents the total number of circuit modules, wi represents the weight value of module i, and distance(m i ) represents the distance between circuit module i and the target position.

[0086] The layout optimization unit includes an annealing optimization unit and a layout cost evaluation unit;

[0087] The annealing algorithm unit is used to perform difference processing based on the total cost C of the new and old layouts to obtain the cost difference △C, and then combine it with the current temperature T. The probability calculation formula in the simulated annealing algorithm is Boltzmann distribution, and obtain the probability P(E) to determine the probability of accepting the new layout;

[0088] The probability P(E) is obtained by the following algorithm formula;

[0089]

[0090] In the formula, P(E) is the probability of accepting the new layout, ΔC represents the cost difference between the new and old layouts, and the algorithm formula is: ΔC = C new (Total cost of new layout) - C current (total cost of old layout), T represents the current temperature, which is used to adjust the probability of the algorithm accepting a worse solution during the optimization process and is obtained through the cooling plan, and exp represents the exponential function;

[0091] The layout cost evaluation unit is used to preset the layout threshold r, and then evaluate the obtained probability P(E) and the layout threshold r to analyze the acceptability of the new layout. The specific evaluation method is as follows;

[0092] When the probability P(E)>layout threshold r, the new layout is rejected and the current layout remains unchanged;

[0093] When the probability P(E) ≤ the layout threshold r, the new layout is accepted.

[0094] In this embodiment, the system uses a heuristic algorithm to quickly generate a preliminary layout through a preliminary layout generation unit, and accurately calculates the initial position and overall layout of each circuit module through a cost function algorithm to obtain a total layout cost C, where the total layout cost C is a quantitative indicator used to evaluate the quality and efficiency of the layout. Specifically, the total layout cost C can be expressed as a cost function that comprehensively considers multiple factors. This process not only improves the efficiency of the layout, but also ensures the rationality and economy of the layout, providing a good starting point for subsequent optimization. Secondly, the layout optimization unit includes an annealing optimization unit and a layout cost evaluation unit, which further improves the layout quality and reliability. The annealing optimization unit uses a simulated annealing algorithm to calculate the probability P(E) of accepting a new layout based on the cost difference △C and temperature T of the current layout, thereby exploring a better layout solution in the search space. This probability-based optimization method effectively avoids the problem of falling into a local optimal solution and improves the possibility and effect of global optimization. The layout cost evaluation unit uses a preset layout threshold r to comprehensively evaluate the probability P(E) and the threshold. When P(E) exceeds the layout threshold r, the system will retain the current layout to avoid unnecessary layout changes; conversely, when P(E) is lower than the threshold r, the system will accept the new layout plan to achieve effective control and adjustment of the layout quality.

[0095] Example 4

[0096] This embodiment is explained in Example 3, please refer to Figure 1 ,Specifically: the global routing module includes a global routing unit and a detailed routing unit;

[0097] The global routing unit is used to optimize the layout of the circuit module through the optimization layout unit, and then use the global routing algorithm based on MazeRouting to further divide the divided circuit module area into grids, apply breadth-first search on the grid to find the path from the output end of the circuit module to the input end of another circuit module, and mark the used grid cells to avoid conflicts;

[0098] The detailed routing unit is used to further optimize each routing path based on the global routing. The objective function is optimized to quantify the quality of routing, including routing length, delay, and power consumption. The length of each path is then summarized and calculated through the detailed routing algorithm to obtain the total routing length L.

[0099] The total wiring length L is obtained by the following algorithm unit;

[0100]

[0101] Where M represents the number of wiring paths, e represents the wiring edge, and the wiring edge e refers to the wire portion connecting the two endpoints. i) represents the length of the i-th wiring.

[0102] In this embodiment, the global wiring unit grids the optimized circuit module area through an algorithm based on MazeRouting, and applies a breadth-first search algorithm to find the best path from the output end to the input end of the circuit module. This process not only effectively avoids wiring conflicts, but also optimizes the selection and use of wiring paths to the greatest extent, ensuring the stability and performance of circuit wiring. Secondly, the detailed wiring unit further optimizes each wiring path on the basis of global wiring. By optimizing the objective function, such as the quantification of factors such as wiring length, delay and power consumption, the detailed wiring algorithm can accurately calculate the actual length of each path. This refined wiring optimization not only improves the overall performance of the circuit, but also reduces the delay and energy consumption of signal transmission, thereby improving the reliability and efficiency of circuit design. The calculation process of the total wiring length L is shown in the above formula, taking into account factors such as the number of wiring paths and the length of each path. Through this systematic wiring length calculation method, designers can have a clear control of the complexity and resource consumption of wiring in the early stage of design, which helps to make more refined optimization and adjustments in subsequent design stages.

[0103] Example 5

[0104] This embodiment is explained in Example 1, please refer to Figure 1 ,Specifically: the evaluation and optimization module includes a preliminary evaluation and ,optimization unit and a rule detection unit;

[0105] The preliminary evaluation and optimization unit includes the comprehensive algorithm unit and the evaluation and optimization unit;

[0106] The comprehensive algorithm unit is used to perform dimensionless processing on the total layout cost C and the total wiring length L optimized by the simulated annealing algorithm, and then perform correlation calculation to obtain a comprehensive layout quality coefficient Z;

[0107] The comprehensive layout quality coefficient Z is obtained by the following algorithm formula;

[0108] Z=(a1*C)+(a2*L)+A;

[0109] In the formula, a1 and a2 represent the weight values ​​of the optimized layout total cost C and the total wiring length L, respectively, and a1+a2=1, the specific value of which is set by the user, and A represents the correction parameter.

[0110] The evaluation and optimization unit is used to preset the layout quality threshold F1 according to the obtained comprehensive layout quality coefficient Z, perform preliminary comparative evaluation, and perform further optimization according to the evaluation results. The specific evaluation scheme is as follows;

[0111] When the comprehensive layout quality coefficient Z ≥ the layout quality threshold F1, it means that the layout of the current integrated circuit is normal, and then further circuit rule checking is performed;

[0112] When the comprehensive layout quality coefficient Z is less than the layout quality threshold F1, it indicates that the layout of the current integrated circuit is abnormal. At this time, the annealing algorithm and the detailed wiring algorithm are re-executed to iteratively optimize the layout quality.

[0113] The rule detection unit is used to be triggered when the layout of the integrated circuit is normal. Further, through the design rule detection tools Cadence, DRC, Synopsys and ICValidator, the current total layout cost C and total wiring length L are imported into the rule detection tool. The tool automatically checks each physical object in the layout according to the rule library and checks it according to the rule set set by the user, and generates a rule check result R. If it detects places that do not meet the rules, the tool will generate a conflict report to point out the specific rule conflicts and locations;

[0114] The rule checking result R is as follows;

[0115] When the rule check result R=0, it means that the layout complies with all physical and electrical rules and enters the next stage of manufacturing preparation;

[0116] When the rule check result R=1, it means that the layout quality of the current integrated circuit is normal, but there is a rule conflict in the layout, and the designer needs to further adjust the layout.

[0117] In this embodiment, the system performs dimensionless processing on the optimized total layout cost C and total wiring length L through the comprehensive algorithm unit through the preliminary evaluation optimization unit, and calculates the comprehensive layout quality coefficient Z. The comprehensive layout quality coefficient Z comprehensively considers the weight distribution of layout cost and wiring length. The user can adjust the weight value according to specific needs, so as to accurately evaluate the overall quality of the layout scheme. In the calculation formula of the comprehensive layout quality coefficient Z, through this comprehensive evaluation, the designer can quickly understand the economy and performance of the layout, and provide a basis for subsequent optimization decisions. Then, the evaluation optimization unit performs a preliminary comparative evaluation of the comprehensive layout quality coefficient Z according to the preset layout quality threshold F1. When the Z value reaches or exceeds the threshold F1, the system determines that the current layout is normal, and then performs a circuit rule check. On the contrary, if the Z value is lower than F1, the system triggers further annealing algorithms and detailed wiring algorithms for iterative optimization to improve the quality and compliance of the layout. Finally, the rule detection unit is started when the layout is evaluated as normal, and the layout is automatically checked for physical and electrical rules through the design rule detection tool. The tool can quickly identify and report the existence of any rule conflicts, thereby helping designers to accurately locate and solve problems in the layout. This systematic rule detection mechanism not only improves the reliability and stability of the design, but also effectively reduces the error rate and cost in the subsequent manufacturing process.

[0118] Example 6

[0119] See also Figure 1 and Figure 2 , a layout method for an integrated circuit, comprising the following steps:

[0120] S1. First, use EDIF and VerilogNetlist parsing tools to input the circuit netlist design tool, then extract the netlist information from the circuit description file and convert it into an internal data structure;

[0121] S2, using heuristic methods and Kernighan-Lin algorithm, divide the circuit into initial regions, evaluate the boundary clarity and overlap of the modules, determine the module area through linear programming, and calculate the initial shape using CAD tools;

[0122] S3. Use the heuristic algorithm to calculate the initial position of the module, obtain the total layout cost C, calculate the probability P(E) of accepting the new layout based on the cost difference △C and the current temperature T through the Boltzmann distribution in the annealing algorithm, and determine the acceptability of the new layout based on the layout threshold r;

[0123] S4. Use the MazeRouting algorithm to divide the module area into grids, find paths and avoid conflicts, optimize each routing path, quantify the routing quality, and calculate the total routing length L;

[0124] S5. Finally, calculate the comprehensive layout quality coefficient Z of the total layout cost C and the total wiring length L, evaluate whether it reaches the preset threshold F1, use the tool to check the layout, generate the rule check result R, and decide whether to make adjustments.

[0125] While the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that many changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the invention.

Claims

1. A layout system for an integrated circuit, characterized in that: It includes circuit table net input module, circuit module division module, preliminary layout planning module, global routing module and evaluation optimization module; The circuit netlist input module is used to input the circuit netlist design tool in the integrated circuit layout design system, and to extract the required circuit description information from the output circuit description file; The circuit module division module divides the circuit into multiple modules based on the circuit function and the circuit physical characteristics, and pre-processes the modules to calculate the initial area and shape of the modules; The preliminary layout planning module is used to construct a cost function algorithm for the initial layout, calculate the initial position of the module, obtain the total layout cost C, and then perform a simulated annealing algorithm to calculate the probability P(E), and evaluate the acceptability of the new layout; The global routing module is used to determine the main connection path optimization routing conflict, and use the detailed routing algorithm to calculate the total routing length L, and verify the circuit physical image and electrical rules of the layout to obtain the inspection results; The evaluation and optimization module is used to combine the total layout cost C and the total wiring length L of the layout plan, perform associated calculations to obtain a comprehensive layout quality coefficient Z, and preset a layout quality threshold F1 and the obtained comprehensive layout quality coefficient Z for preliminary evaluation, and then input the total layout cost C and the total wiring length L into the design rule checking tool, output the rule checking result R, and perform an evaluation.

2. The layout system for an integrated circuit according to claim 1, wherein: The circuit table net input module extracts net table information from the circuit description file through parsing tools EDIF and Verilog Netlist, and converts the circuit design data in the file into an internal data structure. The net table information includes circuit module information, circuit port definition and circuit connection relationship; The circuit module information is used to identify and record the name, type and attributes of each circuit module; The circuit port definition is used to extract the module's input and output port lists and their attributes; The circuit connection relationship is used to establish a connection relationship between modules, including internal connections and interface connections between circuit modules.

3. The layout system for an integrated circuit according to claim 2, wherein: The circuit module division module includes a module division unit and a preprocessing unit; The module division unit is used to divide the circuit into several initial regions according to a certain heuristic method in the integrated circuit layout design, and iteratively improve the division using the Kernighan-Lin algorithm until a preset optimization goal is reached, and then the number of connections between the divided circuit modules is used to evaluate the boundary clarity and overlap of the divided circuit modules; The preprocessing unit is used to determine the area configuration of each circuit module through a linear programming method and design constraints, wherein the design constraints include the circuit function and circuit physical characteristics of the circuit module, and calculate the initial shape of the circuit module using a CAD tool based on the circuit function and circuit physical characteristics of the circuit module.

4. The layout system for an integrated circuit according to claim 3, wherein: The preliminary layout planning module includes a preliminary layout generation unit and an optimization layout unit; The preliminary layout generating unit is used to generate a preliminary layout using a heuristic algorithm, calculate the initial position of the circuit module by constructing a cost function of the initial layout, and obtain a total layout cost C; The total layout cost C is obtained by the following algorithm formula; Where N represents the total number of circuit modules, wi represents the weight value of module i, and distance(m i ) represents the distance between circuit module i and the target position.

5. The layout system for an integrated circuit according to claim 4, wherein: The layout optimization unit includes an annealing optimization unit and a layout cost evaluation unit; The annealing algorithm unit is used to perform difference processing based on the total cost C of the new and old layouts to obtain the cost difference △C, and then combine it with the current temperature T. The probability calculation formula in the simulated annealing algorithm is Boltzmann distribution, and obtain the probability P(E) to determine the probability of accepting the new layout; The probability P(E) is obtained by the following algorithm formula: In the formula, P(E) is the probability of accepting the new layout, ΔC represents the cost difference between the new and old layouts, and the algorithm formula is: ΔC = C new (Total cost of new layout) - C current (total cost of old layout), T represents the current temperature, and exp represents the exponential function; The layout cost evaluation unit is used to preset a layout threshold r, and then evaluate the obtained probability P(E) and the layout threshold r to analyze the acceptability of the new layout. The specific evaluation method is as follows; When the probability P(E)>layout threshold r, the new layout is rejected and the current layout remains unchanged; When the probability P(E) ≤ the layout threshold r, the new layout is accepted.

6. The layout system for an integrated circuit according to claim 5, wherein: The global routing module includes a global routing unit and a detailed routing unit; The global routing unit is used to optimize the layout of the circuit module through the optimization layout unit, and then use the global routing algorithm based on MazeRouting to further divide the divided circuit module area into grids, apply breadth-first search on the grids to find the path from the output end of the circuit module to the input end of another circuit module, and mark the used grid units to avoid conflicts; The detailed routing unit is used to further optimize each routing path based on the global routing, and to quantify the quality of the routing by optimizing the objective function, including the routing length, delay and power consumption, and then to summarize and calculate the length of each path through the detailed routing algorithm to obtain the total routing length L; The total wiring length L is obtained by the following algorithm unit; Where M represents the number of routing paths, e represents the routing edge, and length(e i ) represents the length of the i-th wiring.

7. The layout system for an integrated circuit according to claim 1, wherein: The evaluation and optimization module includes a preliminary evaluation and optimization unit and a rule detection unit; The preliminary evaluation and optimization unit includes a comprehensive algorithm unit and an evaluation and optimization unit; The comprehensive algorithm unit is used to perform dimensionless processing on the total layout cost C and the total wiring length L optimized by the simulated annealing algorithm, and then perform correlation calculation to obtain a comprehensive layout quality coefficient Z; The comprehensive layout quality coefficient Z is obtained by the following algorithm formula: Z=(a1*C)+(a2*L)+A; In the formula, a1 and a2 represent the weight values ​​of the optimized layout total cost C and the total wiring length L, respectively, and a1+a2=1, the specific value of which is set by the user, and A represents the correction parameter.

8. The layout system for an integrated circuit according to claim 7, wherein: The evaluation and optimization unit is used to preset the layout quality threshold F1 according to the obtained comprehensive layout quality coefficient Z, perform preliminary comparative evaluation, and perform further optimization according to the evaluation result. The specific evaluation scheme is as follows; When the comprehensive layout quality coefficient Z ≥ the layout quality threshold F1, it means that the layout of the current integrated circuit is normal, and then further circuit rule checking is performed; When the comprehensive layout quality coefficient Z is less than the layout quality threshold F1, it indicates that the layout of the current integrated circuit is abnormal. At this time, the annealing algorithm and the detailed wiring algorithm are re-executed to iteratively optimize the layout quality.

9. The layout system for an integrated circuit according to claim 8, wherein: The rule detection unit is used to be triggered when the layout of the integrated circuit is normal, and further import the current layout total cost C and total wiring length L into the rule detection tool through the design rule detection tools Cadence, DRC, Synopsys and ICValidator. The tool automatically checks each physical object in the layout according to the rule library, and checks according to the rule set set by the user, and generates a rule check result R. If a place that does not meet the rules is detected, the tool will generate a conflict report to indicate the specific rule conflict and location; The rule checking result R is as follows: When the rule check result R=0, it means that the layout complies with all physical and electrical rules and enters the next stage of manufacturing preparation; When the rule check result R=1, it means that the layout quality of the current integrated circuit is normal, but there is a rule conflict in the layout, and the designer needs to further adjust the layout.

10. A layout method for an integrated circuit, comprising the layout system for an integrated circuit as claimed in any one of claims 1 to 9, characterized in that: The following steps are involved: S1. First, use EDIF and VerilogNetlist parsing tools to input the circuit netlist design tool, then extract the netlist information from the circuit description file and convert it into an internal data structure; S2, using heuristic methods and Kernighan-Lin algorithm, divide the circuit into initial regions, evaluate the boundary clarity and overlap of the modules, determine the module area through linear programming, and calculate the initial shape using CAD tools; S3. Use the heuristic algorithm to calculate the initial position of the module, obtain the total layout cost C, calculate the probability P(E) of accepting the new layout based on the cost difference △C and the current temperature T through the Boltzmann distribution in the annealing algorithm, and determine the acceptability of the new layout based on the layout threshold r; S4. Use the MazeRouting algorithm to divide the module area into grids, find paths and avoid conflicts, optimize each routing path, quantify the routing quality, and calculate the total routing length L; S5. Finally, calculate the comprehensive layout quality coefficient Z of the total layout cost C and the total wiring length L, evaluate whether it reaches the preset threshold F1, use the tool to check the layout, generate the rule check result R, and decide whether to make adjustments.

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