A semiconductor test structure and a semiconductor test method

Abstract

The present invention provides a semiconductor test structure and a semiconductor test method, wherein the semiconductor test structure comprises: a substrate, a well region and a plurality of shallow trench isolation regions are provided, the plurality of shallow trench isolation regions are located on the well region, and the bottom of the well region is continuous; a plurality of measurement structure groups, the measurement structure group comprises a gate to be tested and an active region, the gate to be tested is provided on the surface of the shallow trench isolation region, the active region is provided on the top of the well region and is located on one side of the shallow trench isolation region; and a test voltage terminal, the plurality of gates to be tested are electrically connected to the test voltage terminal, the current value is measured on the active region, and the leakage position of the gate to be tested is determined based on the measured current value. The present invention can determine the measurement structure group where leakage occurs and the measurement structure group where no leakage occurs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor testing structure and a semiconductor testing method. Background Art

[0002] In the semiconductor manufacturing process, shallow trench isolation (STI) is often used for process isolation, which will form a recessed area at the junction of the shallow trench isolation area and the active area. After the polysilicon thin film layer is formed, the polysilicon thin film layer at the recessed area is distorted. After the polysilicon thin film layer is etched to form the gate, polysilicon residues are likely to appear at the recessed area. When the distance between the gate and the active area is small, the polysilicon residue at the recessed area will cause a short circuit between the gate and the active area to cause leakage, resulting in circuit failure. However, in the prior art, it is impossible to determine the specific location of the gate leakage. Therefore, there is room for improvement. Summary of the invention

[0003] The present invention provides a semiconductor test structure and a semiconductor test method to solve the technical problem in the prior art that the specific position of gate leakage cannot be determined.

[0004] The present invention provides a semiconductor test structure, comprising:

[0005] A substrate is provided with a well region and a plurality of shallow trench isolation regions, wherein the plurality of shallow trench isolation regions are located on the well region, and the bottom of the well region is continuous;

[0006] A plurality of measurement structure groups, each of which includes a gate to be measured and an active region, wherein the gate to be measured is disposed on a surface of the shallow trench isolation region, and the active region is disposed on a top of the well region and is located on one side of the shallow trench isolation region; and

[0007] A test voltage terminal is provided, and a plurality of the gates to be tested are electrically connected to the test voltage terminal. A current value is measured on the active area, and a leakage position of the gates to be tested is determined based on the measured current value.

[0008] In one embodiment of the present invention, the gate to be tested includes a first gate and a second gate, a plurality of the first gates and / or a plurality of the second gates are electrically connected to the test voltage terminal, a current value is measured on the active area, and the leakage position of the first gate and / or the second gate is determined based on the measured current value.

[0009] In one embodiment of the present invention, in the measurement structure group, a path direction along the first gate, the active region, and the second gate is recorded as an alignment direction;

[0010] When multiple first gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, or when multiple second gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, it is determined that the first gate or the second gate is deviated in the alignment direction.

[0011] In one embodiment of the present invention, when multiple first gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, and when multiple second gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, it is determined that the measurement structure group has a deviation in the etching process.

[0012] In one embodiment of the present invention, in the measurement structure group, the active region is located between the first gate and the second gate.

[0013] In one embodiment of the present invention, in the measurement structure group, the distance between the active region and the first gate or the second gate is set to zero or 10 nm to 100 nm.

[0014] The present invention also provides a semiconductor testing method, comprising:

[0015] Providing a substrate, forming a well region on the surface of the substrate, forming a plurality of shallow trench isolation regions on the well region, and the bottom of the well region is continuous;

[0016] A gate to be tested is formed on the surface of the shallow trench isolation region, and an active region is formed on the surface of the well region, wherein the active region is arranged on the top of the well region and is located on one side of the shallow trench isolation region;

[0017] Grouping the plurality of gates to be measured and the plurality of active regions into a plurality of measurement structure groups, wherein the measurement structure groups include the gates to be measured and the active regions;

[0018] The plurality of gates to be tested are electrically connected to a test voltage terminal, a current value is measured on the active area, and a leakage position of the gate to be tested is determined based on the measured current value.

[0019] In one embodiment of the present invention, the step of grouping the plurality of gates to be measured and the plurality of active regions into a plurality of measurement structure groups, wherein the measurement structure groups include the gates to be measured and the active regions, comprises:

[0020] Located between two adjacent gates to be tested, an active region is formed on the surface of the well region, so that there are two gates to be tested between the two adjacent active regions;

[0021] The gate to be tested on one side of the active area is recorded as a first gate, and the gate to be tested on the other side of the active area is recorded as a second gate;

[0022] The first gate, the active region and the second gate are recorded as a measurement structure group, and a plurality of the first gates, a plurality of the active regions and a plurality of the second gates are grouped into a plurality of the measurement structure groups.

[0023] In one embodiment of the present invention, the step of electrically connecting the plurality of gates to be tested to a test voltage terminal, measuring a current value on the active area, and determining a leakage position of the gate to be tested based on the measured current value comprises:

[0024] In the measurement structure group, the path direction along the first gate, the active area, and the second gate is recorded as an alignment direction;

[0025] A plurality of the first gates are electrically connected to the test voltage terminal, and when the measured current value on the active area is greater than the normal current value, or a plurality of the second gates are electrically connected to the test voltage terminal, and when the measured current value on the active area is greater than the normal current value, it is determined that the first gate or the second gate is deviated in the alignment direction.

[0026] In one embodiment of the present invention, the step of electrically connecting the plurality of gates to be tested to a test voltage terminal, measuring a current value on the active area, and determining a leakage position of the gate to be tested based on the measured current value comprises:

[0027] When multiple first gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, and when multiple second gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, it is determined that the measurement structure group has a deviation in the etching process.

[0028] Beneficial effects of the present invention: A semiconductor test structure and a semiconductor test method proposed by the present invention have an unexpected technical effect of electrically connecting the gates to be tested in multiple measurement structure groups to the test voltage terminal and measuring the current value in the active area. If leakage occurs in the gate to be tested in the measurement structure group, the gate to be tested, the well area and the active area are conductive, and leakage current will be generated. If no leakage occurs in the gate to be tested in the measurement structure group, the gate to be tested, the well area and the active area are not conductive, and no leakage current will be generated. The present invention performs electrical tests on multiple measurement structure groups to determine the measurement structure group where leakage occurs and the measurement structure group where no leakage occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 An electron microscope schematic diagram of the gate and active area in a semiconductor structure provided by the prior art.

[0031] Figure 2 A schematic diagram of leakage current 50 between a gate and an active region in a semiconductor structure provided in the prior art.

[0032] Figure 3 A schematic diagram of the positions of a gate and an active region in a semiconductor structure provided by the prior art.

[0033] Figure 4 A schematic diagram of the positions of a gate and an active region in another semiconductor structure provided in the prior art.

[0034] Figure 5 A connection diagram of a semiconductor test structure provided by an embodiment of the present invention.

[0035] Figure 6 A connection diagram of another semiconductor test structure provided by an embodiment of the present invention.

[0036] Figure 7 An embodiment of the present invention provides Figure 5 Schematic diagram of the cross section of AA in .

[0037] Figure 8 A schematic structural diagram of a substrate provided in one embodiment of the present invention.

[0038] Fig. 9 A schematic structural diagram of etching a substrate to form a shallow trench isolation region provided in an embodiment of the present invention.

[0039] Fig.10 A schematic diagram of a structure for depositing a shallow trench isolation region provided in an embodiment of the present invention.

[0040] Fig.11 A schematic structural diagram of polishing a shallow trench isolation region provided by an embodiment of the present invention.

[0041] Fig.12 A schematic structural diagram of forming an active region by ion implantation into a well region according to an embodiment of the present invention.

[0042] Fig.13A schematic diagram of a structure for forming a polysilicon thin film layer on the surface of an active area and a shallow trench isolation area provided in one embodiment of the present invention.

[0043] Fig.14 A schematic diagram of a structure for forming a photoresist on a surface of a polysilicon thin film layer provided by an embodiment of the present invention.

[0044] Fig.15 A schematic diagram of a structure for etching a polysilicon thin film layer to form a gate provided by an embodiment of the present invention.

[0045] Fig.16 A schematic structural diagram of forming a dielectric layer on the surfaces of an active area, a shallow trench isolation area and a gate provided in an embodiment of the present invention.

[0046] Fig.17 A schematic structural diagram of dry etching a dielectric layer to form a sidewall provided in an embodiment of the present invention.

[0047] Fig.18 An embodiment of the present invention provides Fig.17 Schematic diagram of leakage current 50 between the gate and the active area.

[0048] Fig.19 A schematic diagram of the steps of a semiconductor testing method provided by an embodiment of the present invention.

[0049] Fig. 20 An embodiment of the present invention provides Fig.19 Schematic diagram of step S30 in FIG.

[0050] Fig.21 An embodiment of the present invention provides Fig.19 Schematic diagram of step S40 in FIG.

[0051] Description of Figure Numbers

[0052] 10. Substrate; 110. Well region; 120. Shallow trench isolation region; 20. Polysilicon thin film layer; 210. Recessed region; 220. Gate to be tested; 230. Dielectric layer; 240. Sidewall; 30. Active region; 310. Contact hole; 410. First test voltage; 420. Second test voltage; 50. Leakage current 50; 510. Gap; 60. Photoresist. DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0054] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0055] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0056] See also Figures 5 to 21 The present invention proposes a semiconductor test structure and a semiconductor test method, which can be applied to the field of semiconductor shallow trench isolation (STI) process. By measuring the current value between the gate 220 to be tested and the active area 30, the leakage position of the gate 220 to be tested can be determined. The present invention analyzes whether the polysilicon remaining at the position of the recessed area 210 between the gate 220 to be tested and the active area 30 will cause a short circuit between the gate 220 to be tested and the active area 30. The following is a detailed analysis through specific embodiments.

[0057] See also Figure 5 , Figure 6 and Figure 7 In one embodiment of the present invention, the present invention proposes a semiconductor test structure, which may include a substrate 10, a measurement structure group and a test voltage terminal. Among them, a well region 110 and a shallow trench isolation region 120 may be provided on the substrate 10, and the shallow trench isolation region 120 is located on the well region 110, and the bottom of the well region 110 is continuous. The measurement structure group may include a gate 220 to be tested and an active region 30, the gate 220 to be tested may be provided on the surface of the shallow trench isolation region 120, and the active region 30 may be provided on the top of the well region 110 and on one side of the shallow trench isolation region 120. The gate 220 to be tested is electrically connected to the test voltage terminal, and the current value is measured on the active region 30.

[0058] Specifically, Figure 7 As shown, the substrate 10 (Sub, substrate) is used as a reference surface and mechanical support, and a device structure such as a well region 110, a shallow trench isolation region 120, a gate to be tested 220 and an active region 30 can be formed on the surface of the substrate 10. In the field of complementary metal oxide semiconductors, when multiple N-type metal oxide semiconductors and P-type metal oxide semiconductors need to be made on a substrate 10 at the same time, a local substrate is made for one type of transistor, which is called a well region 110. In this embodiment, the well region 110 is formed on the substrate 10, and the bottom of the well region 110 is made continuous.

[0059] Specifically, Figure 7 As shown, the shallow trench isolation region (STI, shallow trench isolation) 120 is used for processes below 0.25um, and a groove can be formed by depositing, patterning, and etching silicon using a silicon nitride mask, and then filling the groove with deposited oxide to isolate the deposited oxide from the silicon. In this embodiment, the shallow trench isolation region 120 can be used to prevent the gate 220 to be tested on the top thereof from generating leakage current.

[0060] See also Figure 5 and Figure 6 In one embodiment of the present invention, the number of measurement structure groups may be multiple, and multiple measurement structure groups may be electrically tested to determine the measurement structure group with leakage and the measurement structure group without leakage. The gates 220 to be tested in the multiple measurement structure groups are electrically connected to the test voltage terminal, and the current value is measured on the active area (AA, Active Area) 30. For example, all or part of the gates 220 to be tested in the multiple measurement structure groups are electrically connected to the test voltage terminal, and the test voltage terminal is used to provide voltage to the gates 220 to be tested, and the current value is measured on the active area 30.

[0061] Of course, there may be more than two test voltage terminals, for example, the test voltage terminals include a first test voltage 410 and a second test voltage 420. Some of the gates 220 to be tested in the multiple measurement structure groups are electrically connected to the first test voltage 410, and other gates 220 to be tested in the multiple measurement structure groups are electrically connected to the second test voltage 420, and the measurement current values ​​corresponding to the first test voltage 410 and the second test voltage 420 can be obtained on the active area 30, respectively.

[0062] Among them, since the bottom of the well region 110 is continuous, the test voltage terminal is used to provide a voltage to the gate 220 to be tested. If the gate 220 to be tested, the well region 110 and the active region 30 are conductive, the gate 220 to be tested in the measurement structure group will have leakage and generate a leakage current 50. The test voltage terminal is used to provide a voltage to the gate 220 to be tested. If the gate 220 to be tested, the well region 110 and the active region 30 are not conductive, the gate 220 to be tested in the measurement structure group will not have leakage and will not generate a leakage current 50.

[0063] Specifically, Figure 5 and Figure 7 As shown, the dimension of the gate 220 to be tested along the direction of the source and drain (not shown in the figure) is called the length (L) of the gate 220 to be tested, and the dimension of the gate 220 to be tested perpendicular to the source and drain is called the width (W) of the gate 220 to be tested. The gates 220 to be tested in multiple measurement structure groups are electrically connected to the test voltage terminal, and the current value is measured on the active area 30. If the measured current value on the active area 30 in some measurement structure groups is greater than the normal current value, while the measured current value on the active area 30 in other measurement structure groups is equal to the normal current value, it means that only the measurement structure groups corresponding to the measured current value greater than the normal current value have leakage, and it can be determined that the gates 220 to be tested in these measurement structure groups have alignment deviations in their length direction.

[0064] Specifically, the gate electrodes 220 to be tested in the plurality of measurement structure groups are electrically connected to the test voltage terminal, and the current value is measured on the active area 30. If the measured current values ​​on the active area 30 in all the measurement structure groups are greater than the normal current value, it means that all the measurement structure groups have leakage, and it can be determined that all the measurement structure groups have deviations in the etching process.

[0065] In one embodiment of the present invention, the number of the gates 220 to be tested and the active areas 30 in the measurement structure group is not limited. For example, in one measurement structure group, the number of the gates 220 to be tested is one, and the number of the active areas 30 is one. When the electrical properties of the gates 220 to be tested in multiple measurement structure groups are tested, one gate 220 to be tested corresponds to one active area 30.

[0066] For example, Figure 7As shown, in one measurement structure group, the number of the gates 220 to be tested is two, and the number of the active area 30 is one. The active area 30 may be located between the two gates 220 to be tested, and the gate 220 to be tested on one side of the active area 30 is recorded as the first gate, and the gate 220 to be tested on the other side of the active area 30 is recorded as the second gate. When the gates 220 to be tested in multiple measurement structure groups are electrically tested, multiple first gates or multiple second gates are electrically connected to the test voltage terminal, and the current value is measured on the active area 30 to improve the test efficiency of the gates 220 to be tested. In other embodiments, the number of gates 220 to be tested and the active area 30 in one measurement structure group may be adjusted accordingly as appropriate.

[0067] See also Figure 5 , Figure 6 and Figure 7 As shown, in one embodiment of the present invention, in the measurement structure group, the path direction along the first gate, the active area 30, and the second gate is recorded as the alignment direction. A plurality of gates 220 to be tested are electrically connected to the test voltage terminal. For example, a first test voltage 410 can be set on a plurality of first gates, and a second test voltage 420 can be set on a plurality of second gates. When the first test voltage 410 is set on a plurality of first gates, the measured current value on the active area 30 is greater than the normal current value, and when the second test voltage 420 is set on a plurality of second gates, the measured current value on the active area 30 is equal to the normal current value, it indicates that the first gate has deviated in the alignment direction. The first gate, the well area 110, and the active area 30 are conductive, generating a leakage current 50.

[0068] Alternatively, when a second test voltage 420 is set on multiple second gates, and the measured current value on the active area 30 is greater than the normal current value, and a first test voltage 410 is set on multiple first gates, and the measured current value on the active area 30 is equal to the normal current value, it indicates that the second gates are deviated in the alignment direction. The second gates, the well area 110, and the active area 30 are conductive, generating a leakage current 50.

[0069] See also Figure 5 , Figure 6 and Figure 7 As shown, in one embodiment of the present invention, a first test voltage 410 is set on a plurality of first gates, and the measured current value on the active area 30 is greater than the normal current value, and a second test voltage 420 is set on a plurality of second gates, and the measured current value on the active area 30 is greater than the normal current value, indicating that the measurement structure group has a deviation in the etching process. The first gate, the well area 110, and the active area 30 are conductive, and the second gate, the well area 110, and the active area 30 are conductive, thereby generating a leakage current 50.

[0070] See also Figure 5 , Figure 6 and Figure 7 As shown, in one embodiment of the present invention, in the measurement structure group, the distance between the active area 30 and the gate 220 to be measured is set to zero or 10nm~100nm, the bottom of the well area 110 is continuous, and adjacent active areas 30 are connected through the well area 110 at the bottom, and adjacent active areas 30 are separated by shallow trench isolation areas 120 in the horizontal direction.

[0071] See also Figures 8 to 18 , is the semiconductor test structure proposed by the present invention, and its specific preparation process can be shown as follows.

[0072] See also Figure 8 In one embodiment of the present invention, in the field of complementary metal oxide semiconductors, when multiple N-type metal oxide semiconductors and P-type metal oxide semiconductors need to be made on a substrate 10 at the same time, a local substrate is made for one type of transistor, which is called a well region 110. In this embodiment, the substrate 10 (Sub, substrate) serves as a reference surface and mechanical support, and the well region 110 can be formed on the surface of the substrate 10, and the bottom of the well region 110 is made continuous. A photoresist (PR, Photo Resist) 60 can be formed on the surface of the well region 110, and the photoresist 60 can remove the exposed part of the surface of the well region 110 during the etching process.

[0073] See also Fig. 9 In one embodiment of the present invention, the well region 110 and the photoresist 60 are subjected to photolithography and etching processes to form a shallow trench isolation region (STI, shallow trench isolation) 120 on the well region 110. The number of the shallow trench isolation region 120 can be multiple.

[0074] See also Fig.10 In one embodiment of the present invention, the shallow trench isolation region 120 may be filled with deposited oxide to isolate the deposited oxide from silicon. That is, by providing the shallow trench isolation region 120 on the well region 110, the gate 220 to be tested at the top of the shallow trench isolation region 120 may be prevented from generating leakage current during the subsequent manufacturing process. After the shallow trench isolation region 120 is filled with deposited oxide, the photoresist 60 may be removed.

[0075] See also Fig.11 In one embodiment of the present invention, after removing the photoresist 60 , the well region 110 and the shallow trench isolation region 120 may be subjected to a chemical mechanical polishing (CMP) process to planarize the surfaces of the well region 110 and the shallow trench isolation region 120 .

[0076] See also Fig.12 In one embodiment of the present invention, an active area (AA) 30 can be formed on the surface of the well region 110 by ion implantation (IMP). Structures such as the source, drain and gate of the field effect transistor can be formed on the active area 30, and two adjacent active areas 30 are isolated by a shallow trench isolation region 120.

[0077] See also Fig.13 In one embodiment of the present invention, a polysilicon thin film layer 20 is formed on the surface of the well region 110, the shallow trench isolation region 120, and the active region 30. Fig.14 As shown, a photoresist 60 may be formed on the surface of the polysilicon thin film layer 20, the photoresist 60 may be located above the shallow trench isolation region 120, and the width of the photoresist 60 is smaller than the width of the shallow trench isolation region 120. The photoresist 60 may allow the exposed portion of the surface of the polysilicon thin film layer 20 to be removed during the etching process.

[0078] See also Fig.15 In one embodiment of the present invention, the polysilicon film layer 20 and the photoresist 60 are subjected to photolithography and etching processes so that a gate 220 to be tested is formed on the top of the shallow trench isolation region 120, and the width of the gate 220 to be tested is smaller than the width of the shallow trench isolation region 120.

[0079] See also Fig.16 In one embodiment of the present invention, the photoresist 60 is removed, and a dielectric layer 230 is formed on the surfaces of the active region 30, the well region 110, and the gate 220 to be tested. Fig.17 As shown, by utilizing the anisotropic characteristics of dry etching, the dielectric layer 230 is dry-etched to form a spacer 240 at the step position between the gate 220 to be tested and the well region 110. The spacer 240 protects the sidewall of the gate 220 to be tested, and can be used to prevent the surface of the gate 220 to be tested from being damaged, thereby extending the service life of the gate 220 to be tested.

[0080] See also Fig.18 A contact hole 310 is opened on the active area 30 and the gate 220 to be tested, and a metal wire is connected in the contact hole 310. The active area 30 and the gate 220 to be tested can be electrically tested through the metal wire, and the leakage position of the gate 220 to be tested can be determined based on the measured current value.

[0081] See also Figure 5 , Figure 7 and Fig.18In one embodiment of the present invention, if the gate 220 to be tested does not deviate in the length (L) direction, or the gate 220 to be tested does not deviate in the etching process, that is, the gate 220 to be tested is formed in a normal process, then when a plurality of gates 220 to be tested are electrically connected to a test voltage terminal, the measured current value on the active area 30 is equal to the normal current value. When the gate 220 to be tested deviates in the length (L) direction, or when the gate 220 to be tested deviates in the etching process, that is, the gate 220 to be tested is formed in a process with deviation, such as Figure 3 and Figure 4 As shown, the gap 510 between the gate 220 to be tested and the active area 30 is too small, resulting in conduction between the gate 220 to be tested and the active area 30. When a plurality of gates 220 to be tested are electrically connected to a test voltage terminal, such as Figure 2 As shown, a leakage current 50 is formed between the gate 220 to be tested, the recessed area 210 and the active area 30 . The recessed area 210 is located between the gate 220 to be tested and the active area 30 . The measured current value on the active area 30 is greater than the normal current value.

[0082] Specifically, when the gate 220 to be tested deviates in the length (L) direction, even if the etching process of the gate 220 to be tested is changed, a short circuit between the gate 220 to be tested and the active area 30 will still occur. Therefore, the position and alignment accuracy of the gate 220 to be tested can be changed in the semiconductor process, so that the gap 510 between the gate 220 to be tested and the active area 30 can be normal, so that the gate 220 to be tested and the active area 30 are separated.

[0083] Specifically, when the gate 220 to be tested deviates in the etching process, the conduction between the gate 220 to be tested and the active area 30 is not caused by the deviation of the gate 220 to be tested in the length (L) direction. Therefore, by changing the position and alignment accuracy of the gate 220 to be tested, a short circuit between the gate 220 to be tested and the active area 30 will still occur. Therefore, by changing the etching process of the gate 220 to be tested in the semiconductor process, the gap 510 between the gate 220 to be tested and the active area 30 can be normal, so that the gate 220 to be tested and the active area 30 are separated.

[0084] Since the gate 220 to be tested has a deviation in its length (L) direction, and the gate 220 to be tested has a deviation in the etching process, these are two completely different technical problems, and their solutions are also completely different. Therefore, in the case of a short circuit between the gate 220 to be tested and the active area 30, it is necessary to determine the specific cause of the conduction between the gate 220 to be tested and the active area 30, and to take different improvement measures.

[0085] See also Figures 7 to 19In one embodiment of the present invention, the present invention may provide a semiconductor testing method, which may include the following specific steps.

[0086] Step S10, providing a substrate, forming a well region on the surface of the substrate, forming a plurality of shallow trench isolation regions on the well region, and the bottom of the well region is continuous.

[0087] Step S20, forming a gate to be tested on the surface of the shallow trench isolation region, and forming an active region on the surface of the well region, wherein the active region is arranged on the top of the well region and is located on one side of the shallow trench isolation region.

[0088] Step S30: Grouping the plurality of gates to be tested and the plurality of active regions into a plurality of measurement structure groups, wherein the measurement structure groups include the gates to be tested and the active regions.

[0089] Step S40 , electrically connecting a plurality of gates to be tested to a test voltage terminal, measuring current values ​​on the active region, and determining leakage positions of the gates to be tested based on the measured current values.

[0090] The following describes and analyzes the specific embodiments.

[0091] Step S10, providing a substrate, forming a well region on the surface of the substrate, forming a plurality of shallow trench isolation regions on the well region, and the bottom of the well region is continuous.

[0092] In one embodiment of the present invention, Figure 8 As shown, a well region 110 may be formed on the surface of the substrate 10, and the bottom of the well region 110 may be continuous. Fig. 9 As shown, the well region 110 is subjected to photolithography and etching processes so as to form a shallow trench isolation region 120 on the well region 110 . The number of the shallow trench isolation region 120 may be multiple.

[0093] Step S20, forming a gate to be tested on the surface of the shallow trench isolation region, and forming an active region on the surface of the well region, wherein the active region is arranged on the top of the well region and is located on one side of the shallow trench isolation region.

[0094] In one embodiment of the present invention, Fig.12 As shown, an active region 30 can be formed on the surface of the well region 110 by ion implantation. The active region 30 is disposed on the top of the well region 110 and is located on one side of the shallow trench isolation region 120. Two adjacent active regions 30 are isolated by the shallow trench isolation region 120. Fig.13 As shown in FIG. 1 , a polysilicon thin film layer 20 is formed on the surface of the well region 110, the shallow trench isolation region 120, and the active region 30. Fig.14 and Fig.15As shown, the polysilicon film layer 20 is subjected to photolithography and etching processes so that a gate to be tested 220 is formed on the top of the shallow trench isolation region 120 , and the width of the gate to be tested 220 is smaller than the width of the shallow trench isolation region 120 .

[0095] Step S30: Grouping the plurality of gates to be tested and the plurality of active regions into a plurality of measurement structure groups, wherein the measurement structure groups include the gates to be tested and the active regions.

[0096] In one embodiment of the present invention, the number of measurement structure groups can be multiple, and multiple measurement structure groups can be electrically tested to determine the measurement structure group that has leakage and the measurement structure group that has no leakage. The gates 220 to be tested in the multiple measurement structure groups are electrically connected to the test voltage terminal, and the current value is measured on the active area 30. Since the bottom of the well area 110 is connected, if the gate 220 to be tested in the measurement structure group has leakage, the gate 220 to be tested, the well area 110 and the active area 30 are conductive, and leakage current 50 will be generated. If the gate 220 to be tested in the measurement structure group does not have leakage, the gate 220 to be tested, the well area 110 and the active area 30 are not conductive, and leakage current 50 will not be generated.

[0097] Step S40 , electrically connecting a plurality of gates to be tested to a test voltage terminal, measuring current values ​​on the active region, and determining leakage positions of the gates to be tested based on the measured current values.

[0098] In one embodiment of the present invention, the gates 220 to be tested in the plurality of measurement structure groups are electrically connected to a test voltage terminal, and the current value is measured on the active region 30 .

[0099] Specifically, if the measured current value on the active area 30 in some measurement structure groups is greater than the normal current value, while the measured current value on the active area 30 in other measurement structure groups is equal to the normal current value, it means that only the measurement structure groups corresponding to the measured current values ​​greater than the normal current value have leakage phenomena, and it can be determined that the gates 220 to be measured in these measurement structure groups have misalignment in their length direction.

[0100] Specifically, if the measured current values ​​on the active regions 30 in all the measurement structure groups are greater than the normal current values, it means that all the measurement structure groups have leakage phenomena, and it can be determined that all the measurement structure groups have deviations in the etching process.

[0101] See also Fig. 20In one embodiment of the present invention, step S30 may include step S310, step S320 and step S330. Among them, step S310 can be represented as being located between two adjacent gates 220 to be measured, and an active area 30 is formed on the surface of the well area 110, so that there are two gates 220 to be measured between the two adjacent active areas 30. Step S320 can be represented as recording the gate 220 to be measured on one side of the active area 30 as the first gate, and recording the gate 220 to be measured on the other side of the active area 30 as the second gate. Step S330 can be represented as recording the first gate, the active area 30, and the second gate as a measurement structure group, and grouping multiple first gates, multiple active areas 30, and multiple second gates into multiple measurement structure groups.

[0102] Specifically, in one measurement structure group, the number of the gates 220 to be tested is two, and the number of the active area 30 is one. The active area 30 may be located between the two gates 220 to be tested, and the gate 220 to be tested on one side of the active area 30 is recorded as the first gate, and the gate 220 to be tested on the other side of the active area 30 is recorded as the second gate. When the gates 220 to be tested in the multiple measurement structure groups are electrically tested, the multiple first gates or the multiple second gates are electrically connected to the test voltage terminal, and the current value is measured on the active area 30 to improve the test efficiency of the gates 220 to be tested.

[0103] See also Fig.21 In one embodiment of the present invention, step S40 may include step S410, step S420 and step S430. Among them, step S410 can be represented as in the measurement structure group, the path direction along the first gate, the active area 30, and the second gate is recorded as the alignment direction. Step S420 can be represented as electrically connecting multiple first gates to the test voltage terminal, and when the measured current value on the active area 30 is greater than the normal current, or electrically connecting multiple second gates to the test voltage terminal, when the measured current value on the active area 30 is greater than the normal current, it is determined that the measurement structure group has a deviation in the alignment direction. Step S430 can be represented as electrically connecting multiple first gates to the test voltage terminal, when the measured current value on the active area 30 is greater than the normal current, and electrically connecting multiple second gates to the test voltage terminal, when the measured current value on the active area 30 is greater than the normal current, it is determined that the measurement structure group has a deviation in the etching process.

[0104] In summary, the present invention proposes a semiconductor test structure and a semiconductor test method, and the unexpected technical effect is that the gates to be tested in multiple measurement structure groups are electrically connected to the test voltage terminal, and the current value is measured on the active area. If the gate to be tested in the measurement structure group has leakage, the gate to be tested, the well area and the active area are conductive, and leakage current will be generated. If the gate to be tested in the measurement structure group does not have leakage, the gate to be tested, the well area and the active area are not conductive, and leakage current will not be generated. The present invention performs electrical tests on multiple measurement structure groups to determine the measurement structure group where leakage occurs and the measurement structure group where no leakage occurs.

[0105] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the art without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention. As used in the description herein and in the following entire claims, unless otherwise specified, "one", and "the" include plural references. Similarly, as used in the description herein and in the following entire claims, unless otherwise specified, the meaning of "in..." includes "in..." and "on...".

Claims

1. A semiconductor test structure, characterized in that: include: A substrate is provided with a well region and a plurality of shallow trench isolation regions, wherein the plurality of shallow trench isolation regions are located on the well region, and the bottom of the well region is continuous; A plurality of measurement structure groups, each of which includes a gate to be measured and an active area, wherein the gate to be measured is arranged on the surface of the shallow trench isolation area, and the active area is arranged on the top of the well area and located on one side of the shallow trench isolation area; as well as A test voltage terminal, to which the plurality of gates to be tested are electrically connected, a current value is measured on the active area, and a leakage position of the gate to be tested is determined based on the measured current value; The gate to be tested includes a first gate and a second gate, multiple first gates and / or multiple second gates are electrically connected to the test voltage terminal, a current value is measured on the active area, and the leakage position of the first gate and / or the second gate is determined based on the measured current value.

2. The semiconductor test structure according to claim 1, characterized in that: In the measurement structure group, the path direction along the first gate, the active area, and the second gate is recorded as an alignment direction; When multiple first gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, or when multiple second gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, it is determined that the first gate or the second gate is deviated in the alignment direction.

3. The semiconductor test structure according to claim 1, characterized in that: When multiple first gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, and when multiple second gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, it is determined that the measurement structure group has a deviation in the etching process.

4. The semiconductor test structure according to claim 1, characterized in that: In the measurement structure group, the active region is located between the first gate and the second gate.

5. The semiconductor test structure according to claim 4, characterized in that: In the measurement structure group, the distance between the active region and the first gate or the second gate is set to zero or 10 nm to 100 nm.

6. A semiconductor testing method, characterized in that: include: Providing a substrate, forming a well region on the surface of the substrate, forming a plurality of shallow trench isolation regions on the well region, and the bottom of the well region is continuous; A gate to be tested is formed on the surface of the shallow trench isolation region, and an active region is formed on the surface of the well region, wherein the active region is arranged on the top of the well region and is located on one side of the shallow trench isolation region; Grouping the plurality of gates to be measured and the plurality of active regions into a plurality of measurement structure groups, wherein the measurement structure groups include the gates to be measured and the active regions; Electrically connecting the plurality of gates to be tested to a test voltage terminal, measuring a current value on the active area, and determining a leakage position of the gate to be tested based on the measured current value; The step of grouping the plurality of gates to be measured and the plurality of active regions into a plurality of measurement structure groups, wherein the measurement structure groups include the gates to be measured and the active regions, comprises: Located between two adjacent gates to be tested, an active region is formed on the surface of the well region, so that there are two gates to be tested between the two adjacent active regions; The gate to be tested on one side of the active area is recorded as a first gate, and the gate to be tested on the other side of the active area is recorded as a second gate; Recording the first gate, the active region and the second gate as a measurement structure group, and grouping a plurality of the first gates, a plurality of the active regions and a plurality of the second gates into a plurality of the measurement structure groups; A plurality of the first gates and / or a plurality of the second gates are electrically connected to the test voltage terminal, a current value is measured on the active area, and a leakage position of the first gate and / or the second gate is determined based on the measured current value.

7. The semiconductor testing method according to claim 6, characterized in that: The step of electrically connecting the plurality of gates to be tested to a test voltage terminal, measuring a current value on the active area, and determining a leakage position of the gate to be tested based on the measured current value comprises: In the measurement structure group, the path direction along the first gate, the active area, and the second gate is recorded as an alignment direction; A plurality of the first gates are electrically connected to the test voltage terminal, and when the measured current value on the active area is greater than the normal current value, or a plurality of the second gates are electrically connected to the test voltage terminal, and when the measured current value on the active area is greater than the normal current value, it is determined that the first gate or the second gate is deviated in the alignment direction.

8. The semiconductor testing method according to claim 6, characterized in that: The step of electrically connecting the plurality of gates to be tested to a test voltage terminal, measuring a current value on the active area, and determining a leakage position of the gate to be tested based on the measured current value comprises: When multiple first gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, and when multiple second gates are electrically connected to the test voltage terminal and the measured current value on the active area is greater than the normal current value, it is determined that the measurement structure group has a deviation in the etching process.

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