A semiconductor capacitor and its array

Abstract

The present application provides a semiconductor capacitor and its array, wherein the semiconductor capacitor includes a substrate; a barrier layer, the barrier layer is directly arranged on the substrate; a first metal layer, a second metal layer, and a first insulating layer sandwiched between the first metal layer and the second metal layer; a second insulating layer, the second insulating layer is filled between the barrier layer and the first metal layer; a first through hole in contact with the first metal layer; a second through hole in contact with the second metal layer; wherein the barrier layer at least completely covers the first metal layer in the projection along the thickness direction of the substrate, and the thickness of the second insulating layer is more than one order of magnitude greater than the first insulating layer. The semiconductor capacitor and its array provided by the present application can further reduce the equivalent series resistance of the capacitor when the product is miniaturized and has a high capacitance.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and relates to semiconductor capacitors and arrays thereof, and in particular to semiconductor capacitors and arrays thereof with miniaturization and large capacitance. Background Art

[0002] Capacitors are commonly used passive components in integrated circuits. In RF applications, capacitors are often integrated with inductors and / or resistors to achieve filtering and tuning. Equivalent series resistance (ESR) is a key parameter of capacitors, which directly affects the quality factor (Q) of capacitors. The smaller the equivalent series resistance, the higher the quality factor of the capacitor and the lower the overall heating of the capacitor.

[0003] Currently, in order to optimize the ESR of high-Q series semiconductor capacitors, it is usually achieved by selecting low-loss dielectric layers and using low-resistance metal materials. However, when traditional semiconductor materials with better processing costs and precision, such as silicon, are selected as substrates, since traditional semiconductor substrate materials such as silicon have a strong absorption effect on radio frequency electric fields, it will directly lead to a significant increase in the equivalent series resistance (ESR) of the capacitor, affecting the capacitor performance. Summary of the invention

[0004] In order to solve the technical problem in the prior art that it is difficult to further reduce the capacitor equivalent series resistance when the product is miniaturized and has a high capacitance, the present invention provides the following technical solutions:

[0005] A first aspect of the present application provides a semiconductor capacitor, characterized in that the semiconductor capacitor comprises:

[0006] substrate;

[0007] a barrier layer, the barrier layer being directly disposed on the substrate;

[0008] A first metal layer, a second metal layer, and a first insulating layer interposed between the first metal layer and the second metal layer;

[0009] A second insulating layer, the second insulating layer is filled between the barrier layer and the first metal layer;

[0010] a first through hole in contact with the first metal layer; a second through hole in contact with the second metal layer;

[0011] Wherein, the barrier layer at least completely covers the first metal layer in the projection along the thickness direction of the substrate;

[0012] The thickness of the second insulating layer is greater than that of the first insulating layer by more than one order of magnitude.

[0013] Optionally, the barrier layer is a conductive material.

[0014] Optionally, the barrier layer has a stacked structure of conductive material-dielectric material-conductive material.

[0015] Optionally, the semiconductor capacitor further has a third insulating layer, which is directly stacked on the second insulating layer and covers the entire first metal layer, the first insulating layer and the second metal layer.

[0016] Optionally, the semiconductor capacitor further comprises a metal wiring layer disposed on the third insulating layer, and the first through hole and the second through hole respectively pass through the third insulating layer and are connected to the metal wiring layer.

[0017] Optionally, the dielectric constant of the third insulating layer is less than 3.9.

[0018] Optionally, the third insulating layer has a different material than the second insulating layer.

[0019] Optionally, the substrate is silicon or silicon carbide.

[0020] Optionally, the barrier layer completely covers the substrate surface.

[0021] A second aspect of the present application provides a semiconductor capacitor array, which includes a plurality of semiconductor capacitors as described in the first aspect; external terminals connected to the semiconductor capacitor array; and connecting components for connecting the semiconductor capacitors; wherein the plurality of semiconductor capacitors are arranged vertically and / or horizontally.

[0022] In a third aspect, the present application provides an integrated passive component, the passive component comprising one or more semiconductor capacitors, one or more semiconductor inductors, and / or one or more semiconductor resistors; a substrate carrying the passive component; a package body, the package body completely encapsulating the semiconductor capacitor, the semiconductor inductor, and / or the semiconductor resistor;

[0023] The semiconductor capacitor has an intermediate insulating layer between two electrode plates;

[0024] The invention is characterized in that a barrier layer is directly arranged on the substrate, and the barrier layer at least completely covers the semiconductor capacitor in the projection along the thickness direction of the substrate;

[0025] An interlayer insulating layer is provided between the semiconductor capacitor and the barrier layer, and the thickness of the interlayer insulating layer is greater than that of the intermediate insulating layer by more than one order of magnitude.

[0026] Optionally, the blocking layer also extends to under other passive components other than the semiconductor capacitor.

[0027] A fourth aspect of the present application is an integrated circuit structure, comprising one or more semiconductor capacitors and one or more active devices; a substrate carrying the integrated circuit structure; and a package body, wherein the package body completely encapsulates the semiconductor capacitor and the active device;

[0028] The semiconductor capacitor has an intermediate insulating layer between two electrode plates;

[0029] The invention is characterized in that a barrier layer is directly arranged on the substrate, and the barrier layer at least completely covers the semiconductor capacitor in the projection along the thickness direction of the substrate;

[0030] An interlayer insulating layer is provided between the semiconductor capacitor and the barrier layer, and the thickness of the interlayer insulating layer is greater than that of the intermediate insulating layer by more than one order of magnitude.

[0031] Optionally, the integrated circuit structure further includes one or more semiconductor inductors and / or one or more semiconductor resistors.

[0032] Optionally, the barrier layer also extends to underneath other integrated circuit structures other than active devices.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. The capacitors for which protection is sought in the present invention are based on semiconductor materials, rather than traditional capacitors based on ceramic materials, such as MLCC or SLC. A barrier layer is directly provided on a semiconductor material substrate, and the barrier layer at least completely covers the first metal layer in the projection along the thickness direction of the substrate. The above arrangement limits the radio frequency electric field to above the substrate, prevents electromagnetic waves from propagating to the substrate, greatly reduces the substrate's absorption of radio frequency signals, and thereby effectively reduces the equivalent series resistance of the capacitor. That is, the present invention reduces the equivalent series resistance to 1 / 50 of that of a traditional semiconductor capacitor by providing a barrier layer on the surface of the substrate, so that the capacitor can obtain a larger quality factor and improve the overall performance of the semiconductor capacitor.

[0035] 2. The capacitor for which protection is sought in the present invention is prepared by semiconductor processing technology. In particular, in the MIM structure formed by the first metal layer-first insulating layer-second metal layer, the growth thickness and uniformity of the first insulating layer can be precisely controlled by deposition, sputtering, etc. The thickness of the first insulating layer can be as low as 5nm, which can greatly improve the capacitance value of the semiconductor capacitor compared to the traditional process. In addition, the control accuracy of the semiconductor process is much higher than that of the ceramic sintering process. The semiconductor capacitor preparation process provided by the present invention is controlled within 1% in accuracy, which is more than 10 times higher than the sintering process.

[0036] 3. The capacitor for which protection is sought in the present invention also has the characteristic of flexible adjustment of capacitance. The semiconductor capacitor in the present invention includes a MIM capacitor, namely, a first metal layer, a first insulating layer, a second metal layer, and a parasitic capacitor in the structure, and the parasitic capacitor includes a parasitic capacitor formed by a metal wiring layer and a second metal layer, and a first metal layer and a barrier layer. In actual use, the capacitance of the overall semiconductor capacitor can be flexibly adjusted as a whole by selecting the second and third insulating layers with suitable dielectric constants and their thicknesses, the overlapping morphology of the metal wiring layer and the second metal layer, and the dielectric constant and thickness of the first insulating layer in the MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A structural diagram of a semiconductor capacitor provided for this application;

[0038] Figure 2 This is a comparative diagram of equivalent series resistance under two structures with a barrier layer and without a barrier layer, shown in an exemplary embodiment of the present application;

[0039] Figure 3 A structural diagram of another semiconductor capacitor provided in this application;

[0040] Figure 4 A graph comparing the quality factors of a semiconductor inductor with and without a barrier layer in the present invention;

[0041] Figure 5 A structural diagram of an integrated passive component provided for this application;

[0042] Figure 6 A structural deformation of an integrated passive component provided by the present application;

[0043] Figure 7 A structural diagram of an integrated circuit provided for this application;

[0044] Figure 8 A structural deformation diagram of an integrated circuit provided in this application.

[0045] Among them, 1 – substrate;

[0046] 2-blocking layer; 21-first blocking sublayer; 22-first insulating sublayer; 23-second blocking sublayer;

[0047] 3-Second insulating layer;

[0048] 4-MIM capacitor structure; 41-first metal layer; 42-first insulating layer; 43-second metal layer;

[0049] 5 - third insulating layer;

[0050] 6-first through hole; 7-second through hole;

[0051] 8-metal wiring layer; 9-passivation layer;

[0052] 10-semiconductor capacitor; 111-passive component 1; 112-passive component 2; ... 11n-passive component n;

[0053] 13 - Package; 14 - Interlayer insulation layer; 15 - Active components. DETAILED DESCRIPTION

[0054] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0055] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "the" and "the" used in this application are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0056] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0057] Specific embodiments are given below to introduce the technical solution of the present application in detail.

[0058] Figure 1 The structure diagram of the semiconductor capacitor provided for this application. Please refer to Figure 1 , the semiconductor capacitor provided in this embodiment may include:

[0059] Substrate 1;

[0060] A barrier layer 2, wherein the barrier layer 2 is directly disposed on the substrate 1;

[0061] A first metal layer 41, a second metal layer 43, and a first insulating layer 42 sandwiched between the first metal layer 41 and the second metal layer 43;

[0062] A second insulating layer 3, wherein the second insulating layer 3 is filled between the barrier layer 2 and the first metal layer 41;

[0063] A first through hole 6 in contact with the first metal layer 41; a second through hole 7 in contact with the second metal layer 43;

[0064] Wherein, the barrier layer 2 at least completely covers the first metal layer 41 in projection along the thickness direction of the substrate 1;

[0065] Furthermore, the thickness of the second insulating layer 3 is greater than that of the first insulating layer 42 by more than one order of magnitude.

[0066] It should be noted that in the semiconductor capacitor structure provided by the present invention, the core MIM capacitor structure 4 is composed of a first metal layer 41, a first insulating layer 42 and a second metal layer 43. The materials of the first metal layer 41 and the second metal layer 43 can be Cu, Al, Ti, TiN, etc. or a multilayer film composed thereof, and the first insulating layer 42 uses a dielectric material such as silicon nitride, silicon oxide, magnesium oxide, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, etc. or a multilayer film structure composed thereof. In particular, the materials of the first metal layer 41 and the second metal layer 43 can be selected from different materials.

[0067] The thickness and dielectric constant of the first insulating layer 42 are important parameters of the overall MIM capacitor. Through semiconductor material growth methods such as deposition and sputtering, in particular, high-precision growth processes such as atomic layer deposition can be selected to accurately control the growth thickness and uniformity of the first insulating layer 42. The thickness of the first insulating layer 42 can be as low as 5nm, which can greatly improve the capacitance value of the semiconductor capacitor compared to traditional capacitor preparation processes.

[0068] A barrier layer 2 is provided on the substrate 1, wherein the function of the barrier layer 2 is to block or reduce the diffusion of RF energy to the substrate 1, thereby reducing the absorption of the substrate 1. Therefore, in order to ensure the blocking effect, the barrier layer 2 should at least completely cover the first metal layer 41 in the projection along the thickness direction of the substrate 1. That is, the pattern of the barrier layer 2 projected onto the substrate 1 needs to at least cover the larger metal layer in the core MIM capacitor in terms of morphology to ensure that the RF electric field generated by the MIM capacitor is shielded by the barrier layer 2 and does not overflow to the substrate 1. It should be noted that the barrier layer 2 can be provided in the form of completely covering the substrate 1 to avoid electric field leakage caused by the area where the barrier layer 2 is not formed. At the same time, the step of patterning the barrier layer 2 is omitted, which can further simplify the process.

[0069] It should also be noted that the second insulating layer 3 is filled between the barrier layer 2 and the first metal layer 41, and its thickness is greater than the first insulating layer 42 by more than one order of magnitude. Specifically, a dielectric layer with a smaller dielectric constant is selected as the material of the second insulating layer 3. In particular, the dielectric constant of the second insulating layer 3 is an oxide dielectric layer with a dielectric constant less than 3.9, such as silicon oxide. In order to provide a stronger insulation effect and reduce the effect of parasitic capacitance, the thickness of the second insulating layer 3 is generally greater than that of the first insulating layer 42, to the order of microns. The typical thickness of the second insulating layer 3 is 1-25um. The thickness difference between the first insulating layer 42 and the second insulating layer 3 can provide different degrees of insulation and isolation effects at different locations to meet specific electrical performance requirements.

[0070] Specifically, the material of the barrier layer 2 may be a conductive material. For example, in one embodiment, the material of the barrier layer 2 is Cu, Al, Ti, TiN, or a multilayer film composed thereof. Specifically, the material of the barrier layer 2 is a conductive material that can effectively shield radio frequency energy. In addition, the multilayer film composed of these materials can combine the advantages of different materials to provide a better blocking effect.

[0071] At the same time, in order to better enhance the blocking effect, the thickness of the blocking layer 2 is generally greater than 20nm. A thicker blocking layer 2 can more effectively block the diffusion of RF energy to the substrate 1, reduce the absorption of RF energy by the substrate 1, and thus improve the performance and stability of the semiconductor capacitor.

[0072] Optionally, when the barrier layer 2 and the substrate 1 have poor adhesion and the barrier layer material diffuses significantly to the substrate, if aluminum is selected as the barrier layer 2 and the substrate 1 is a Si material, the aluminum grows directly on silicon and has a small adhesion force, which increases the possibility of barrier layer peeling, poor uniformity and other problems. In addition, aluminum grows directly on silicon and is easy to diffuse and form spikes, which in turn affects the reliability of the capacitor. In order to avoid the above-mentioned problems of poor adhesion and diffusion to the substrate, a silicon dioxide layer can be grown on the substrate surface by a thermal oxidation process as an intermediate layer to improve the reliability of the entire capacitor. It should be noted that when the barrier layer material and the silicon substrate diffuse insignificantly and have good adhesion, it is not necessary to set the intermediate layer.

[0073] It should be noted that the substrate 1 is a semiconductor substrate material such as silicon, silicon germanium, gallium nitride, silicon carbide, zinc oxide, diamond, etc., which provides basic support for the entire semiconductor capacitor. Silicon, as a semiconductor material, has good mechanical support performance, and has very mature processing technology and industrial chain. The cost of using silicon as a substrate is relatively low. In addition, the electrical properties can be accurately adjusted by means such as doping. In specific implementation, the material of the substrate 1 can be intrinsic silicon (high-resistance silicon), or it can be doped silicon, or it can be a third-generation semiconductor material (SiC, etc.) or an insulating substrate (such as magnesium oxide, aluminum oxide, glass substrate, etc.). By selecting different materials as substrates, different needs can be met. For example, using intrinsic silicon as a substrate, because intrinsic silicon has a high resistivity, it can reduce undesirable phenomena such as leakage; for another example, using doped silicon as a substrate, due to the doping of different impurities, the electrical properties of silicon can be accurately adjusted to meet the needs of different circuit designs. In addition, SiC can be used as a substrate if it is necessary to work at higher temperatures, frequencies and powers.

[0074] It should be noted that the semiconductor capacitor also has a third insulating layer 5, which is directly stacked on the second insulating layer 3 and covers the entire first metal layer 41, the first insulating layer 42 and the second metal layer 43, so as to provide comprehensive insulation and isolation protection for the MIM capacitor structure 4. Specifically, this comprehensive coverage can effectively prevent leakage and short circuits between different metal layers and between the metal layer and the external environment, thereby improving the electrical performance and stability of the semiconductor capacitor. In specific applications, the third insulating layer 5 only needs to cover the first metal layer 41-first insulating layer 42-second metal layer 43 to form the MIM capacitor structure 4, and the typical thickness of the third insulating layer 5 is 0.6-5um.

[0075] It should also be noted that the third insulating layer 5 has a different material from the second insulating layer 3, and the dielectric constants of the second and third insulating layers are less than 3.9. Since the third insulating layer 5 and the second insulating layer 3 are made of different materials, they will be different in physical and chemical properties, which may include thermal stability, mechanical strength, adhesion to adjacent layers, etc., and will also have different dielectric constants. Specifically, the selection of different materials can be determined according to specific performance requirements and the compatibility of the manufacturing process to achieve a more optimized overall structure. Among them, the dielectric constants of the second and third insulating layers are less than 3.9, which helps to reduce the capacitance effect, so that in high-frequency applications, the signal transmission speed is faster and the loss is smaller, thereby improving the performance of the circuit, and the smaller dielectric constant can also reduce the storage energy of the electric field in the insulating layer, reducing energy loss and heat generation. By combining different materials with low dielectric constants, the frequency response characteristics of semiconductor capacitors can be improved, so that they can maintain stable performance in a wider frequency range. In addition, it also helps to improve the insulation performance of capacitors, enhance the isolation effect of electrical signals, and reduce mutual interference.

[0076] It should also be noted that the second and third insulating layers may be configured to have the same material.

[0077] It should also be noted that the semiconductor capacitor also has a metal wiring layer 8 disposed on the third insulating layer 5, and the first through hole 6 and the second through hole 7 respectively pass through the third insulating layer 5 and are connected to the metal wiring layer 8. Specifically, the first through hole 6 is in contact with the first metal layer 41, and the second through hole 7 is in contact with the second metal layer 43, which are used to achieve connection with an external circuit so that the capacitor can be used in the circuit.

[0078] Among them, the metal wiring layer 8 is mainly used to realize the wiring and connection of the circuit, and effectively electrically connect different semiconductor capacitor elements or external circuits. The first through hole 6 and the second through hole 7 are respectively connected to the metal wiring layer 8 through the third insulating layer 5. This connection method ensures that the first metal layer 41 and the second metal layer 43 can be connected to the metal wiring layer 8 through the through hole, so that the current and signal can be smoothly transmitted in the entire circuit. In this way, the flexibility and integration of the circuit layout are improved, and a complex circuit structure can be more conveniently constructed through the metal wiring layer 8, and the third insulating layer 5 provides good insulation protection for this connection, preventing short circuit and signal interference.

[0079] It should be noted that a passivation layer 9 is also provided on the metal wiring layer 8, and holes are opened on the metal wiring layer 8 and the passivation layer 9 to protect the interior of the semiconductor capacitor from pollution such as water vapor.

[0080] Figure 2 This is a diagram showing the change of equivalent series resistance in two structures with and without a barrier layer, as shown in an exemplary embodiment of the present application. Figure 2 For example, at 2pF, the equivalent series resistance of the capacitor without a barrier layer is 1000ohm, while the equivalent series resistance of the capacitor with a barrier layer drops to less than 10ohm. It can be seen that at a frequency of 900Mhz, especially at small capacitance values ​​(<10pF), the equivalent series resistance of the capacitor structure with a barrier layer is greatly reduced, bringing outstanding technical effects and greatly improving the performance of the capacitor.

[0081] The semiconductor capacitor provided by the present application, by adding a barrier layer and selecting the material of the barrier layer as a conductive material, can, on the one hand, significantly reduce the penetration and diffusion of radio frequency energy into the substrate, reduce the absorption of radio frequency energy by the substrate, thereby improving the performance and stability of the capacitor in a radio frequency environment. In addition, it also helps to isolate the first metal layer from the substrate, reduce unnecessary charge exchange and interference between them, and optimize the electrical properties of the capacitor. On the other hand, by setting a barrier layer to block the diffusion of radio frequency energy, the heating of the substrate caused by energy absorption can be reduced, thereby optimizing the thermal distribution of the semiconductor capacitor and improving its reliability and service life in a high temperature environment.

[0082] The capacitor for which protection is sought in the present invention is prepared by semiconductor processing technology. In particular, in the MIM structure formed by the first metal layer-first insulating layer-second metal layer, the growth thickness and uniformity of the first insulating layer can be accurately controlled by deposition, sputtering, etc. The thickness of the first insulating layer can be as low as nanometers, which can greatly improve the capacitance value of the semiconductor capacitor compared to the traditional process. In addition, the control accuracy of the semiconductor process is much higher than that of the ceramic sintering process. The semiconductor capacitor preparation process provided by the present invention is controlled within 1% in accuracy, which is more than 10 times higher than the sintering process.

[0083] The semiconductor capacitor in the present invention includes a MIM capacitor, that is, a first metal layer, a first insulating layer, a second metal layer, and a parasitic capacitor in the structure, and the parasitic capacitor includes a parasitic capacitor formed by a metal wiring layer and a second metal layer, and a first metal layer and a barrier layer, respectively. In actual use, the capacitance of the overall semiconductor capacitor can be flexibly adjusted by selecting the second and third insulating layers with suitable dielectric constants and their thicknesses, the overlapping morphology of the metal wiring layer and the second metal layer, and the dielectric constant and thickness of the first insulating layer in the MIM capacitor.

[0084] In addition, the barrier layer is set as a laminated structure of conductive material-dielectric material-conductive material, which can more effectively block radio frequency energy. Compared with a barrier layer of a single conductive material, it has a better shielding effect, can more comprehensively block radio frequency energy of different frequencies and intensities, and can also enhance insulation performance and reduce the risk of leakage and short circuit. Ultimately, it plays a role in effectively reducing the equivalent series resistance of semiconductor capacitors.

[0085] In specific applications, the barrier layer 2 can be configured to be a stack of barrier layer-insulating layer-barrier layer according to actual needs, and a multi-layer structure can be repeatedly stacked. Specifically, the conductive material of the outer layer can continue to play the role of shielding RF energy and prevent RF energy from diffusing to the substrate, while the dielectric material in the middle can play the role of isolation and enhancing insulation performance, further preventing the conduction and coupling of RF energy.

[0086] like Figure 3A simple variant embodiment is shown, in which the single structure barrier layer in the first embodiment of the present invention is improved, specifically by setting a first barrier sublayer 21-first insulating sublayer 22-second barrier sublayer 23 to form a composite structure. Through the stacked multiple barrier sublayers, the radio frequency electric field can be absorbed multiple times, and then the equivalent series resistance of the capacitor can be further reduced after multiple absorptions. Through this stacked structure, radio frequency energy can be blocked more effectively. Compared with a barrier layer of a single conductive material, it has a better shielding effect, can more comprehensively block radio frequency energy of different frequencies and intensities, and can also enhance insulation performance and reduce the risk of leakage and short circuit. In addition, the combination of different materials can improve the mechanical strength and stability of the barrier layer, making it more adaptable to various working environments.

[0087] Corresponding to the aforementioned semiconductor capacitor embodiments, the present application also provides a semiconductor capacitor array, which includes any of the aforementioned semiconductor capacitors; external terminals connected to the semiconductor capacitor array; and connecting components that connect the semiconductor capacitors; wherein multiple semiconductor capacitors are arranged vertically and / or horizontally.

[0088] It should be noted that the vertical arrangement can increase the number of capacitors within a limited space and improve the integration; the horizontal arrangement facilitates the parallel connection of circuits and improves the current carrying capacity and signal transmission efficiency; the combined vertical and horizontal arrangement can be optimized according to the specific circuit design and space limitations to achieve the best performance and layout effect.

[0089] Specifically, this array structure can provide a larger capacitance value to meet the demand for large-capacity capacitors, and due to the combination of multiple capacitors, the overall reliability and stability can be improved, reducing the impact of a single capacitor failure on the entire system.

[0090] Based on the concept provided by the semiconductor capacitor with a barrier layer disclosed in the present invention, the semiconductor capacitor can also be applied to an integrated passive device IPD structure prepared by integrating multiple passive components, or an integrated circuit structure integrated with active devices.

[0091] In the integration of multiple passive components, it is particularly necessary to consider the impact of the conversion structure between capacitors and inductors. In order to explore the impact of adding a barrier layer on semiconductor inductors, the present invention also focuses on the comparative study of whether or not a barrier layer is provided on the key parameter of the inductor, the quality factor. Please refer to Figure 4It can be seen that when the frequency is below 7GHz, the quality factor of the case without a barrier layer is slightly higher than that with a barrier layer, and in the range above 7GHz, the quality factor with a barrier layer will be significantly better than that without a barrier layer. Through the discussion of the quality factor of semiconductor inductors, it can be seen that setting an additional barrier layer under the semiconductor inductor will not bring adverse effects, especially when the operating frequency reaches above 7GHz, the barrier layer below it will further improve the performance of the inductor.

[0092] Based on this, the present invention provides an integrated passive component, please refer to Figure 5 The passive components include one or more semiconductor capacitors 10, one or more passive components 111, and / or one or more passive components 112; a substrate 1 carrying the passive components; a package 13, the package completely encapsulates the semiconductor capacitor, the passive component 111, and / or the passive component 112; the semiconductor capacitor 10 has an intermediate insulating layer between two electrode plates; a blocking layer 2 is directly arranged on the substrate 1, and the blocking layer 2 at least completely covers the semiconductor capacitor 10 in the projection along the thickness direction of the substrate 1; an interlayer insulating layer 14, the interlayer insulating layer 14 is arranged between the semiconductor capacitor 10 and the blocking layer 2, and the thickness of the interlayer insulating layer is more than one order of magnitude greater than the intermediate insulating layer.

[0093] In practical applications, the passive components 111 and 112 may be semiconductor inductors and / or semiconductor resistors. In addition, n passive components 111 . . . 11n may be provided, and may further include other semiconductor capacitors.

[0094] The description of the substrate 1 and the barrier layer 2 in this embodiment can refer to the description of the same structure mentioned above, and will not be repeated here.

[0095] Specifically, the integrated passive component also has an interlayer insulating layer, which is at least arranged between the semiconductor capacitor 10 and the substrate 1. In the specific preparation process, the interlayer insulating layer can be arranged to be completely laid on the barrier layer and the substrate surface, and then a flattening process is performed to obtain a plane to facilitate the subsequent preparation of the passive component. The interlayer insulating layer usually selects a dielectric layer with a dielectric constant less than 3.9, which helps to reduce the capacitance effect. In this way, in high-frequency applications, the signal transmission speed is faster and the loss is smaller, thereby improving the performance of the circuit, and the smaller dielectric constant can also reduce the storage energy of the electric field in the insulating layer, reducing energy loss and heat.

[0096] Please refer to the following Figure 6 , showing a deformation structure of the integrated passive component provided by the present invention, which is Figure 5 The difference is that the barrier layer not only covers the bottom of the semiconductor capacitor, but also extends to the bottom of other passive components. Figure 4From the analysis, it can be seen that introducing an additional barrier layer on the substrate surface of a semiconductor inductor or semiconductor resistor will not deteriorate its individual performance. Therefore, the area of ​​the barrier layer can be further expanded until it covers the entire substrate surface.

[0097] In addition, please refer to Figure 7 The present application also provides an integrated circuit structure, including one or more semiconductor capacitors 10, and one or more active devices 15; a substrate 1 carrying the integrated circuit structure; a package 13, the package 13 completely encapsulates the semiconductor capacitor 10 and the active device 15; the semiconductor capacitor 10 has an intermediate insulating layer between two electrode plates; it is characterized in that a barrier layer 2 is directly arranged on the substrate 1, and the barrier layer 2 at least completely covers the semiconductor capacitor 10 in the projection along the thickness direction of the substrate 1; an interlayer insulating layer 14, the interlayer insulating layer 14 is arranged between the semiconductor capacitor 10 and the barrier layer 2, and the thickness of the interlayer insulating layer 14 is more than one order of magnitude greater than the intermediate insulating layer.

[0098] There are many types of active devices in an integrated circuit, and the present invention does not specifically limit the types of active devices. In practical applications, the active device is directly arranged in contact with the substrate, and a barrier layer and an interlayer insulating layer are avoided thereunder.

[0099] In practical applications, the passive component 111 may be a semiconductor inductor or a semiconductor resistor. In addition, there may be n passive components 111 . . . 11n, which may further include another semiconductor capacitor.

[0100] Please refer to the following Figure 8 , showing a modified structure of the integrated circuit provided by the present invention, which is Figure 7 The difference is that the barrier layer not only covers the bottom of the semiconductor capacitor, but also extends to the bottom of other passive device structures besides the active device. Figure 4 It can be seen from the analysis that introducing an additional barrier layer on the substrate surface of a semiconductor inductor or semiconductor resistor does not deteriorate its individual performance, so the area of ​​the barrier layer can be further expanded.

[0101] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A semiconductor capacitor, characterized in that: The semiconductor capacitor comprises: substrate; a barrier layer, the barrier layer being directly disposed on the substrate, wherein the barrier layer is a conductive material; A first metal layer, a second metal layer, and a first insulating layer interposed between the first metal layer and the second metal layer; a second insulating layer, the second insulating layer being filled between the barrier layer and the first metal layer, wherein the second insulating layer directly covers the entire surface of the barrier layer; a first through hole in contact with the first metal layer; a second through hole in contact with the second metal layer; Wherein, the barrier layer at least completely covers the first metal layer in the projection along the thickness direction of the substrate; The thickness of the second insulating layer is greater than that of the first insulating layer by more than one order of magnitude.

2. The semiconductor capacitor according to claim 1, wherein: The barrier layer has a stacked structure of conductive material-dielectric material-conductive material.

3. The semiconductor capacitor according to claim 1, wherein: The semiconductor capacitor also has a third insulating layer, which is directly stacked on the second insulating layer and covers the entire first metal layer, the first insulating layer and the second metal layer.

4. The semiconductor capacitor according to claim 3, characterized in that: The semiconductor capacitor further has a metal wiring layer disposed on the third insulating layer, and the first through hole and the second through hole respectively pass through the third insulating layer and are connected to the metal wiring layer.

5. The semiconductor capacitor according to claim 3, characterized in that: The dielectric constant of the third insulating layer is less than 3.

9.

6. The semiconductor capacitor according to claim 3, characterized in that: The third insulating layer has a different material from that of the second insulating layer.

7. The semiconductor capacitor according to claim 1, wherein: The substrate is silicon or silicon carbide.

8. The semiconductor capacitor according to claim 1, wherein: The barrier layer completely covers the surface of the substrate.

9. A semiconductor capacitor array, characterized in that: It comprises a plurality of semiconductor capacitors as described in any one of claims 1 to 8; external terminals connected to the semiconductor capacitor array; and connecting components for connecting the semiconductor capacitors; wherein the plurality of semiconductor capacitors are arranged vertically and / or horizontally.

10. An integrated passive component, the passive component comprising one or more semiconductor capacitors, one or more semiconductor inductors, and / or one or more semiconductor resistors; a substrate carrying the passive element; a package body, wherein the package body completely encapsulates the semiconductor capacitor, the semiconductor inductor, and / or the semiconductor resistor; The semiconductor capacitor has an intermediate insulating layer between two electrode plates; Characterized in that a barrier layer is directly disposed on the substrate, and the barrier layer at least completely covers the semiconductor capacitor in a projection along the thickness direction of the substrate, wherein the barrier layer is a conductive material; An interlayer insulating layer is disposed between the semiconductor capacitor and the barrier layer, wherein the interlayer insulating layer directly covers the entire surface of the barrier layer, and the thickness of the interlayer insulating layer is greater than that of the intermediate insulating layer by more than one order of magnitude.

11. The integrated passive component according to claim 10, characterized in that: The blocking layer also extends to below other passive components except the semiconductor capacitor.

12. An integrated circuit structure, comprising one or more semiconductor capacitors and one or more active devices; a substrate carrying the integrated circuit structure; and a package, wherein the package completely encapsulates the semiconductor capacitor and the active device; The semiconductor capacitor has an intermediate insulating layer between two electrode plates; It is characterized in that A barrier layer is directly disposed on the substrate, wherein the barrier layer at least completely covers the semiconductor capacitor in a projection along the thickness direction of the substrate, wherein the barrier layer is a conductive material; An interlayer insulating layer is disposed between the semiconductor capacitor and the barrier layer, wherein the interlayer insulating layer directly covers the entire surface of the barrier layer, and the thickness of the interlayer insulating layer is greater than that of the intermediate insulating layer by more than one order of magnitude.

13. The integrated circuit structure according to claim 12, wherein: The integrated circuit structure further includes one or more semiconductor inductors and / or one or more semiconductor resistors.

14. The integrated circuit structure according to claim 12, wherein: The barrier layer also extends to below other integrated circuit structures other than the active devices.

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