A multi-serial port communication method and system based on FPGA

Abstract

The invention discloses a multi-serial port communication method and system based on FPGA, and relates to the technical field of serial port communication. The method comprises: obtaining the current serial port communication data of the FPGA module, and then determining the available baud rate of the serial port device to be accessed; determining the minimum baud rate according to the device identification of the serial port device to be accessed, and pre-processing the bit error rate to obtain the target bit error rate difference, and then determining the position coordinates and interference direction of the virtual interference source, correcting the minimum baud rate, and obtaining the target minimum baud rate; finally, determining the target baud rate according to the difference between the available baud rate and the target minimum baud rate. The invention fits the external interference source into a virtual interference source by considering factors such as the bit error rate and the device position, and dynamically adjusts the baud rate according to the virtual interference source, thereby achieving the goal of meeting the communication needs of more devices under limited communication resources, improving the communication efficiency and quality, and enhancing the stability and reliability of communication.

Description

Technical Field

[0001] The present invention relates to the technical field of serial port communication, and in particular to a multi-serial port communication method and system based on FPGA. Background Art

[0002] Multi-serial communication refers to a technology in which multiple serial communication interfaces (such as UART, USART, etc.) are used in a system to exchange data with different external devices at the same time. This communication method is widely used in industrial automation, data acquisition, remote control and other fields because it allows the system to interact with multiple devices at the same time, improving the flexibility and efficiency of the system.

[0003] However, in a multi-serial communication environment, the management of communication baud rate and the control of communication bit error rate are important challenges. Baud rate, as a unit to measure the data transmission rate, directly affects the efficiency and real-time performance of data transmission. In a multi-serial system, different devices may support different baud rate ranges, and the actual available baud rate may be limited due to factors such as transmission distance and line quality. When dealing with baud rate adjustment, existing multi-serial communication methods often only focus on the capabilities of the device itself and the resource allocation within the system, while ignoring the impact of external interference sources on communication quality. These external interference sources may include electromagnetic interference, signal attenuation, line noise, etc., which will reduce signal quality and increase bit error rate, thereby affecting the stability and reliability of communication. Summary of the invention

[0004] In view of the defects in the prior art, the present invention provides a multi-serial port communication method and system based on FPGA.

[0005] On the one hand, the present invention provides a multi-serial port communication method based on FPGA, the method comprising:

[0006] When receiving a serial port communication request sent by a serial port device to be connected, obtaining the current serial port communication data of the FPGA module, wherein the serial port communication data includes the device identification and device location of the serial port device to be connected and the device identification and device location of the connected serial port device, the serial port baud rate and bit error rate of the corresponding serial port; calculating the serial port baud rate sum according to the serial port baud rate, and determining the available baud rate of the serial port device to be connected according to the difference between the serial port baud rate sum and the preset serial port baud rate sum;

[0007] Determine the minimum baud rate according to the device identification of the serial port device to be connected; pre-process the bit error rate to obtain a target bit error rate difference, and determine the position coordinates and interference direction of the virtual interference source according to the device position and the target bit error rate difference; correct the minimum baud rate according to the position coordinates and interference direction to obtain the target minimum baud rate;

[0008] The target baud rate is determined according to the difference between the available baud rate and the target minimum baud rate; and the communication between the serial port device to be connected and the FPGA module is established according to the target baud rate.

[0009] Preferably, obtaining the device identification of the serial port device to be connected to determine the minimum baud rate includes:

[0010] The baud rate of the serial port device to be connected is determined from a baud rate table according to the device identification of the serial port device to be connected, wherein the baud rate table is used to map the relationship between the device identification of the serial port device and the minimum baud rate.

[0011] Preferably, preprocessing the bit error rate includes:

[0012] Calculating a bit error rate difference between the bit error rate and a bit error rate threshold, wherein the bit error rate threshold is determined according to a bit error rate threshold table, and the bit error rate threshold table is used to map the relationship between the serial port device identifier and the bit error rate threshold;

[0013] The bit error rate difference is normalized to obtain a target bit error rate difference.

[0014] Preferably, the formula for determining the position coordinates of the virtual interference source according to the device position and the target bit error rate difference is:

[0015]

[0016] In the formula, represents the location coordinates of the virtual interference source, Indicates the number of connected serial port devices. Indicates The location coordinates of the connected serial port devices, For the The target bit error rate difference of the connected serial port devices.

[0017] Preferably, determining the interference direction of the virtual interference source according to the device position and the target bit error rate difference includes:

[0018] Determine the connected serial port device with the largest target bit error rate as the reference point;

[0019] The direction vector from the virtual interference source to the reference point is calculated according to the position coordinates of the reference point and the position coordinates of the virtual interference source, and the direction vector is normalized to obtain the unit direction vector of the virtual interference source, and the formula is:

[0020]

[0021] In the formula, Represents the position coordinates of the reference point, Represents the direction vector from the interference source to the reference point, Represents the unit direction vector of the virtual interference source.

[0022] Preferably, the minimum baud rate is corrected according to the position coordinates and the interference direction, and the target minimum baud rate formula is obtained as follows:

[0023]

[0024] In the formula, Indicates the location coordinates of the serial port device to be connected. Indicates the Euclidean distance from the virtual interference source to the serial port device to be connected. Represents the unit vector between the serial port device to be connected and the virtual interference source position, represents the interference directional product, Indicates the minimum baud rate, Indicates the target minimum baud rate, is a constant.

[0025] Preferably, determining the target baud rate according to the difference between the available baud rate and the target minimum baud rate comprises:

[0026] When the target minimum baud rate is less than the available baud rate, selecting the smallest available baud rate among the available baud rates as the target baud rate;

[0027] When the target minimum baud rate belongs to the available baud rate, determining the target minimum baud rate to be a target baud rate;

[0028] When the target minimum baud rate is greater than the available baud rate, baud rate scheduling is performed according to the difference between the target minimum baud rate and the available baud rate.

[0029] On the other hand, the present invention provides a multi-serial port communication system based on FPGA, the system includes an FPGA module, the FPGA module includes a CPU unit and an FPGA unit connected by a bus, and the FPGA unit includes:

[0030] A first determination unit is used to obtain the current serial port communication data of the FPGA module when receiving a serial port communication request sent by the serial port device to be connected, wherein the serial port communication data includes a device identification and a device location of the serial port device to be connected and a device identification and a device location of the connected serial port device, a serial port baud rate and a bit error rate of the corresponding serial port; calculate a serial port baud rate sum according to the serial port baud rate, and determine an available baud rate of the serial port device to be connected according to a difference between the serial port baud rate sum and a preset serial port baud rate sum;

[0031] The second determination unit is used to determine the minimum baud rate according to the device identification of the serial port device to be connected; pre-process the bit error rate to obtain a target bit error rate difference, and determine the position coordinates and interference direction of the virtual interference source according to the device position and the target bit error rate difference; correct the minimum baud rate according to the position coordinates and the interference direction to obtain the target minimum baud rate;

[0032] The serial port communication unit is used to determine the target baud rate according to the difference between the available baud rate and the target minimum baud rate; and establish communication between the serial port device to be connected and the FPGA module according to the target baud rate.

[0033] The beneficial effects of the present invention are embodied in: a multi-serial port communication method and system based on FPGA, the method comprising: when receiving a serial port communication request sent by a serial port device to be accessed, obtaining the current serial port communication data of the FPGA module, and calculating the serial port baud rate and the serial port baud rate according to the serial port baud rate, thereby determining the available baud rate of the serial port device to be accessed; determining the minimum baud rate according to the device identification of the serial port device to be accessed, and preprocessing the bit error rate to obtain the target bit error rate difference, thereby determining the position coordinates and interference direction of the virtual interference source, correcting the minimum baud rate, and obtaining the target minimum baud rate; finally, determining the target baud rate according to the difference between the available baud rate and the target minimum baud rate. The present invention fits the external interference source into a virtual interference source by considering factors such as the bit error rate and the device position, and dynamically adjusts the baud rate according to the virtual interference source, thereby achieving the goal of meeting the communication needs of more devices under limited communication resources, improving communication efficiency and quality, and enhancing the stability and reliability of communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0035] Figure 1 A schematic diagram of a multi-serial port communication method based on FPGA provided by the present invention;

[0036] Figure 2 A schematic diagram of the structure of a multi-serial port communication system based on FPGA provided by the present invention. DETAILED DESCRIPTION

[0037] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0038] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0039] Example 1

[0040] like Figure 1 As shown, the present invention provides a multi-serial port communication method based on FPGA, the method comprising:

[0041] Step 1, when receiving a serial port communication request sent by a serial port device to be accessed, obtain the current serial port communication data of the FPGA module, wherein the serial port communication data includes the device identification and device location of the serial port device to be accessed and the device identification and device location of the connected serial port device, the serial port baud rate and bit error rate of the corresponding serial port; calculate the serial port baud rate sum according to the serial port baud rate, and determine the available baud rate of the serial port device to be accessed according to the difference between the serial port baud rate sum and the preset serial port baud rate sum.

[0042] The FPGA module includes the FPGA unit, which plays a core role in serial communication and is responsible for receiving, processing and forwarding data. It is necessary to obtain the current serial communication data of the FPGA module in order to understand the current status of the serial communication, including the identification, location, baud rate and bit error rate of the connected device.

[0043] The serial port baud rate indicates the rate of data transmission and is an important indicator for measuring the performance of serial port communication. By calculating the sum of the baud rates of all currently connected serial port devices, the current total communication load of the system can be obtained. By comparing the difference between the current sum of the serial port baud rates and the preset sum of the serial port baud rates, it can be evaluated whether there is additional communication capacity to accommodate new serial port devices. If the difference is large, it means that there is enough capacity and a higher baud rate can be allocated to the device to be connected; otherwise, a lower baud rate needs to be allocated to ensure the stability and efficiency of the overall communication.

[0044] This embodiment can dynamically adjust and optimize the allocation of serial port communication resources to ensure that the communication requirements of more devices are met as much as possible under limited communication resources.

[0045] Step 2, determine the minimum baud rate according to the device identification of the serial port device to be connected; pre-process the bit error rate to obtain the target bit error rate difference, and determine the position coordinates and interference direction of the virtual interference source according to the device position and the target bit error rate difference; correct the minimum baud rate according to the position coordinates and interference direction to obtain the target minimum baud rate.

[0046] The bit error rate is an indicator that measures the accuracy of data transmission within a specified time, and is usually used to evaluate the performance of serial communication. The calculation of the bit error rate is mainly based on the ratio of the number of erroneous code elements to the total number of transmitted code elements during the transmission process.

[0047] When the baud rate is high, the data transmission speed is faster, but this also means that the frequency of signal changes increases. High-frequency signals are more susceptible to factors such as noise and interference during transmission, resulting in an increase in the bit error rate. Data transmission systems at high baud rates require more powerful error correction capabilities to ensure accurate data transmission. When the baud rate is high, the data transmission speed is faster, but this also means that the frequency of signal changes increases. High-frequency signals are more susceptible to factors such as noise and interference during transmission, resulting in an increase in the bit error rate. Data transmission at high baud rates requires more powerful error correction capabilities to ensure accurate data transmission.

[0048] In an embodiment of the present invention, obtaining the device identification of the serial port device to be accessed to determine the minimum baud rate includes: determining the baud rate of the serial port device to be accessed from a baud rate table according to the device identification of the serial port device to be accessed, wherein the baud rate table is used to map the relationship between the device identification of the serial port device and the minimum baud rate.

[0049] In an embodiment of the present invention, preprocessing the bit error rate includes: calculating the bit error rate difference between the bit error rate and a bit error rate threshold, wherein the bit error rate threshold is determined according to a bit error rate threshold table, and the bit error rate threshold table is used to map the relationship between the serial port device identifier and the bit error rate threshold; normalizing the bit error rate difference to obtain a target bit error rate difference.

[0050] Specifically, for each serial port device, the difference between its bit error rate and the bit error rate threshold at the corresponding baud rate is calculated, the maximum and minimum bit error rate differences of all serial port devices are found, and then the target bit error rate difference is calculated using the normalization formula, and the target bit error rate difference is standardized to improve the efficiency of subsequent processing.

[0051] It should be noted that serial port communication interference includes interference that only affects the serial port device itself and interference that affects multiple serial port communications of the serial port device. The interference that affects itself is easy to measure. In a specific embodiment, the bit error rate difference can be corrected according to the calculated interference amount that affects itself.

[0052] Specifically, the connection status of the serial port is detected by the connection port pressure sensor, the cable status is detected by the ultrasonic sensor, and the power status of the serial port device is detected by the current sensor or voltage sensor. The time when the abnormality is detected is matched with the time when the bit error occurs, and the corresponding bit errors are eliminated. The bit error rate is calculated based on the eliminated bit errors. At the same time, it is also necessary to calculate the ratio of the bit error rate corresponding to the eliminated part to the bit error rate corresponding to the non-eliminated part, and the bit error rate threshold is corrected according to the ratio.

[0053] In the embodiment of the present invention, the formula for determining the position coordinates of the virtual interference source according to the device position and the target bit error rate difference is:

[0054]

[0055] In the formula, represents the location coordinates of the virtual interference source, Indicates the number of connected serial port devices. Indicates The location coordinates of the connected serial port devices, For the The target bit error rate difference of the connected serial port devices.

[0056] In an embodiment of the present invention, determining the interference direction of the virtual interference source according to the device position and the target bit error rate difference includes: determining the connected serial port device with the largest target bit error rate as a reference point; calculating the direction vector from the virtual interference source to the reference point according to the position coordinates of the reference point and the position coordinates of the virtual interference source, normalizing the direction vector, and obtaining the unit direction vector of the virtual interference source, the formula is:

[0057]

[0058] In the formula, Represents the position coordinates of the reference point, Represents the direction vector from the interference source to the reference point, Represents the unit direction vector of the virtual interference source.

[0059] Of course, in other embodiments, the connected serial port devices can be clustered according to the data type transmitted by the connected serial port devices, the location betweenness (average distance from other connected devices), the baud rate, etc., and the connected serial port devices can be divided into multiple categories, and the cluster center of each category is determined as a reference point, and the unit direction vector corresponding to each reference point is calculated according to the method of the above embodiment. Then, when calculating the distance between the serial port device to be connected and each cluster center, the weight of each unit direction vector is determined according to the distance, and the final unit direction vector is obtained according to the weight and the unit direction vector.

[0060] The external interference is fitted into a virtual interference source through the above method, and the position and interference direction of the virtual interference source are determined.

[0061] In the embodiment of the present invention, the minimum baud rate is corrected according to the position coordinates and the interference direction, and the target minimum baud rate formula is obtained as follows:

[0062]

[0063] In the formula, Indicates the location coordinates of the serial port device to be connected. Indicates the Euclidean distance from the virtual interference source to the serial port device to be connected. Represents the unit vector between the serial port device to be connected and the virtual interference source position, represents the interference directional product, Indicates the minimum baud rate, Indicates the target minimum baud rate, is a constant.

[0064] The closer the result of the interference direction product is to 1, the closer the serial port device to be connected is in the interference direction of the virtual interference source; the closer the result is to -1, the closer the serial port device to be connected is in the opposite direction of the virtual interference source; the closer the result is to 0, the direction of the serial port device to be connected is perpendicular to the virtual interference source.

[0065] Step 3: determine a target baud rate according to the difference between the available baud rate and the target minimum baud rate, and establish communication between the serial port device to be connected and the FPGA module according to the target baud rate.

[0066] In an embodiment of the present invention, determining a target baud rate according to a difference between the available baud rate and the target minimum baud rate includes: when the target minimum baud rate is less than or equal to the available baud rate, selecting the smallest available baud rate among the available baud rates as the target baud rate; when the target minimum baud rate belongs to the available baud rate, determining the target minimum baud rate as the target baud rate; when the target minimum baud rate is greater than the available baud rate, performing baud rate scheduling according to the difference between the target minimum baud rate and the available baud rate.

[0067] In one embodiment, the available baud rate is a range interval. In mode 1, if the minimum baud rate is less than this range interval, it indicates that the current available baud rate margin is large, and the minimum available baud rate among the available baud rates can be selected as the target baud rate, which is not only conducive to improving communication efficiency and communication quality, but also avoids occupying a large amount of available baud rate resources. In mode 2, if it is within this range interval, the target minimum baud rate is directly determined as the target baud rate. In mode 3, if it is greater than this range interval, it indicates that the current available baud rate is not enough to achieve reliable and stable serial port communication. At this time, a part of the baud rate corresponding to the serial port device that has been connected in accordance with mode 1 is dispatched to the serial port corresponding to the serial port device to be connected.

[0068] In one embodiment, the available baud rates are some of the conventional baud rates.

[0069] In summary, the present invention provides a multi-serial port communication method based on FPGA, the method comprising: when receiving a serial port communication request sent by a serial port device to be accessed, obtaining the current serial port communication data of the FPGA module, and calculating the serial port baud rate and the serial port baud rate according to the serial port baud rate, thereby determining the available baud rate of the serial port device to be accessed; determining the minimum baud rate according to the device identification of the serial port device to be accessed, and preprocessing the bit error rate to obtain the target bit error rate difference, thereby determining the position coordinates and interference direction of the virtual interference source, correcting the minimum baud rate, and obtaining the target minimum baud rate; finally, determining the target baud rate according to the difference between the available baud rate and the target minimum baud rate. The present invention fits all interference sources into a virtual interference source by considering factors such as the bit error rate and the device position, and dynamically adjusts the baud rate according to the virtual interference source, thereby achieving the goal of meeting the communication needs of more devices under limited communication resources, improving communication efficiency and quality, and enhancing the stability and reliability of communication.

[0070] Example 2

[0071] like Figure 2 As shown, the present invention provides a multi-serial port communication system based on FPGA, the system includes an FPGA module, the FPGA module includes a CPU unit and an FPGA unit connected by a bus, and the FPGA unit includes:

[0072] A first determination unit is used to obtain the current serial port communication data of the FPGA module when receiving a serial port communication request sent by the serial port device to be connected, wherein the serial port communication data includes a device identification and a device location of the serial port device to be connected and a device identification and a device location of the connected serial port device, a serial port baud rate and a bit error rate of the corresponding serial port; calculate a serial port baud rate sum according to the serial port baud rate, and determine an available baud rate of the serial port device to be connected according to a difference between the serial port baud rate sum and a preset serial port baud rate sum;

[0073] The second determination unit is used to determine the minimum baud rate according to the device identification of the serial port device to be connected; pre-process the bit error rate to obtain a target bit error rate difference, and determine the position coordinates and interference direction of the virtual interference source according to the device position and the target bit error rate difference; correct the minimum baud rate according to the position coordinates and the interference direction to obtain the target minimum baud rate;

[0074] The serial port communication unit is used to establish communication between the serial port device to be connected and the FPGA module according to the target baud rate.

[0075] The FPGA-based multi-serial port communication system provided in the embodiment of the present invention and the FPGA-based multi-serial port communication method provided in the above embodiment are based on the same inventive concept. Therefore, the more detailed working process of each unit in the embodiment of the present invention refers to the above embodiment and will not be repeated here.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention.

Claims

1. A multi-serial port communication method based on FPGA, characterized in that: include: When receiving a serial port communication request sent by a serial port device to be connected, obtaining the current serial port communication data of the FPGA module, wherein the serial port communication data includes the device identification and device location of the serial port device to be connected and the device identification and device location of the connected serial port device, the serial port baud rate and bit error rate of the corresponding serial port; calculating the serial port baud rate sum according to the serial port baud rate, and determining the available baud rate of the serial port device to be connected according to the difference between the serial port baud rate sum and the preset serial port baud rate sum; Determine the minimum baud rate according to the device identification of the serial port device to be connected; pre-process the bit error rate to obtain a target bit error rate difference, and determine the position coordinates and interference direction of the virtual interference source according to the device position and the target bit error rate difference; correct the minimum baud rate according to the position coordinates and interference direction to obtain the target minimum baud rate; The target baud rate is determined according to the difference between the available baud rate and the target minimum baud rate; and the communication between the serial port device to be connected and the FPGA module is established according to the target baud rate.

2. The FPGA-based multi-serial port communication method according to claim 1, characterized in that: Obtaining the device identification of the serial port device to be connected and determining the minimum baud rate includes: determining the baud rate of the serial port device to be connected from a baud rate table according to the device identification of the serial port device to be connected, wherein the baud rate table is used to map the relationship between the serial port device identification and the minimum baud rate.

3. The FPGA-based multi-serial port communication method according to claim 1, characterized in that: Preprocessing the bit error rate includes: Calculating a bit error rate difference between the bit error rate and a bit error rate threshold, wherein the bit error rate threshold is determined according to a bit error rate threshold table, and the bit error rate threshold table is used to map the relationship between the serial port device identifier and the bit error rate threshold; The bit error rate difference is normalized to obtain a target bit error rate difference.

4. The FPGA-based multi-serial port communication method according to claim 1, characterized in that: The formula for determining the position coordinates of the virtual interference source according to the device position and the target bit error rate difference is: In the formula, represents the location coordinates of the virtual interference source, Indicates the number of connected serial port devices. Indicates The location coordinates of the connected serial port devices, For the The target bit error rate difference of the connected serial port devices.

5. The FPGA-based multi-serial port communication method according to claim 4, characterized in that: Determining the interference direction of the virtual interference source according to the device position and the target bit error rate difference includes: Determine the connected serial port device with the largest target bit error rate as the reference point; The direction vector from the virtual interference source to the reference point is calculated according to the position coordinates of the reference point and the position coordinates of the virtual interference source, and the direction vector is normalized to obtain the unit direction vector of the virtual interference source, that is, the interference direction, and the formula is: In the formula, Represents the position coordinates of the reference point, Represents the direction vector from the interference source to the reference point, Represents the unit direction vector of the virtual interference source.

6. The FPGA-based multi-serial port communication method according to claim 5, characterized in that: The minimum baud rate is corrected according to the position coordinates and interference direction, and the target minimum baud rate formula is obtained as follows: In the formula, Indicates the location coordinates of the serial port device to be connected. Indicates the Euclidean distance from the virtual interference source to the serial port device to be connected. Represents the unit vector between the serial port device to be connected and the virtual interference source position, represents the interference directional product, Indicates the minimum baud rate, Indicates the target minimum baud rate, is a constant.

7. The FPGA-based multi-serial port communication method according to claim 1, characterized in that: Determining the target baud rate by the difference between the available baud rate and the target minimum baud rate comprises: When the target minimum baud rate is less than the available baud rate, selecting the smallest available baud rate among the available baud rates as the target baud rate; When the target minimum baud rate belongs to the available baud rate, determining the target minimum baud rate to be a target baud rate; When the target minimum baud rate is greater than the available baud rate, baud rate scheduling is performed according to the difference between the target minimum baud rate and the available baud rate.

8. A multi-serial port communication system based on FPGA, characterized in that: The device comprises an FPGA module, wherein the FPGA module comprises a CPU unit and an FPGA unit connected via a bus, wherein the FPGA unit comprises: A first determination unit is used to obtain the current serial port communication data of the FPGA module when receiving a serial port communication request sent by the serial port device to be connected, wherein the serial port communication data includes a device identification and a device location of the serial port device to be connected and a device identification and a device location of the connected serial port device, a serial port baud rate and a bit error rate of the corresponding serial port; calculate a serial port baud rate sum according to the serial port baud rate, and determine an available baud rate of the serial port device to be connected according to a difference between the serial port baud rate sum and a preset serial port baud rate sum; The second determination unit is used to determine the minimum baud rate according to the device identification of the serial port device to be connected; pre-process the bit error rate to obtain a target bit error rate difference, and determine the position coordinates and interference direction of the virtual interference source according to the device position and the target bit error rate difference; correct the minimum baud rate according to the position coordinates and the interference direction to obtain the target minimum baud rate; The serial port communication unit is used to determine the target baud rate according to the difference between the available baud rate and the target minimum baud rate; and establish communication between the serial port device to be connected and the FPGA module according to the target baud rate.

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