Circuit topology associated data construction method, integrated circuit design method and system

Abstract

The present invention provides a circuit topology association data construction method, an integrated circuit design method and system, the circuit topology association data construction method includes the steps of analyzing the integrated circuit and extracting the circuit unit and its attribute information, analyzing the topological similarity between the extracted circuit units, dividing the multiple circuit units into topological set groups according to the topological similarity, and generating topological association information for each topological set group and associating it with a specific implementation technology, so that the constructed circuit topology association data can be used by EDA tools to realize specific circuit implementation based on a specific topological type. In the integrated circuit design method, the EDA tool can use the circuit topology association data to reorganize the circuit logic structure based on a specific topological type before performing logic optimization, so as to realize a more optimized integrated circuit design, which is conducive to solving problems such as timing, congestion and metal resource challenges in high-performance CPU and GPU design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a circuit topology association data construction method, an integrated circuit design method and a system. Background Art

[0002] In the prior art, electronic design automation (EDA) tools are usually used to design integrated circuits, including generating logic netlists and physical layout wiring diagrams of circuits. Existing EDA tools use universal solutions for all circuits. In the design, common problems include timing and congestion problems. For example, in the design of high-performance CPUs and high-performance GPUs, the above problems exist and are difficult to be well solved. Existing CPU and GPU designs usually use a fault power-dominated design method, which cannot provide a solution to this problem.

[0003] Specifically, Figure 6 A common integrated circuit design method in the prior art is shown, and the method comprises the following steps:

[0004] Step 1, generate the logic structure of the circuit based on the design described in a high-level language or HDL;

[0005] Step 2: Logic Optimization of the logic structure of the circuit;

[0006] Step 3: Perform initial physical layout and routing based on the optimized logic structure.

[0007] Step 4: Perform clock tree synthesis on the initial physical layout and routing.

[0008] Step 5: Perform timing and placement optimization on the initial physical layout and routing after clock tree synthesis.

[0009] That is to say, the existing integrated circuit design methods do not allow the reorganization of the circuit design before the logic optimization, and the initial physical layout and routing are performed before the clock tree synthesis and the timing and layout and routing optimization. Therefore, the existing methods have great limitations and it is difficult to solve the problems of timing, congestion and limited metal resources in the design of high-performance CPUs and GPUs. Summary of the invention

[0010] The present invention is made to solve the above-mentioned problem, and aims to provide a data construction method capable of constructing information data of association relationships between circuit topological structures, so that tools or processes can use the data to automatically / semi-automatically realize more optimized integrated circuit design with a specific topological structure. The present invention adopts the following technical solutions:

[0011] The present invention provides a method for constructing circuit topology association data, which is used to construct circuit topology association data, and the data is used for electronic design automation tools to realize circuit implementation based on topology type. The method has the following technical characteristics. The method comprises the following steps: Step S1-1, analyzing the integrated circuit to extract multiple circuit units and their attribute information, wherein the attribute information includes the topology type defined by the circuit transfer function; Step S1-2, for each of the extracted topology types, analyzing the topological similarity between the multiple circuit units under the topology type; Step S1-3, dividing the multiple circuit units under the topology type into one or more topology set groups based on the topological similarity; Step S1-4, generating topology association information for each of the topology set groups based on the attribute information and the topological similarity, and associating the topology association information with the corresponding implementation technology of the circuit unit, thereby obtaining the circuit topology association data.

[0012] The circuit topology association data construction method provided by the present invention may also have such technical features, wherein the implementation technology includes the area division method, the replication method of components or assemblies in each area, the interconnection method of the components or assemblies, and the resource sharing method, and the topology association information includes the group number of each topology set group, the corresponding topology type and the corresponding attribute information.

[0013] The circuit topology associated data construction method provided by the present invention may also have such a technical feature, wherein the attribute information includes the unit name of the circuit unit, circuit function, layout information, and logical connection relationship with other circuit units.

[0014] The circuit topology association data construction method provided by the present invention may also have such a technical feature, wherein, in step S1-3, when one topology type corresponds to multiple topology set groups, the topological similarity between the circuit units of the multiple topology set groups is also calculated, and based on the topological similarity, the multiple topology set groups of the same topology type are divided into one or more similarity groups, and the association information also includes the group number of the similarity group to which each topology set group belongs, and the topological similarity strength between the circuit units in different topology set groups in the similarity group.

[0015] The circuit topology association data construction method provided by the present invention may also have such a technical feature, wherein, in step S1-3, when a similarity group contains multiple topology set groups, the topological similarity between the circuit units of the multiple topology set groups is also calculated as the topological similarity strength, and the topological association information also includes the corresponding topological similarity strength.

[0016] The circuit topology association data construction method provided by the present invention may also have such a technical feature, wherein the topology association information also includes dimension information of the circuit units in the topology set group.

[0017] The circuit topology association data construction method provided by the present invention may also have such a technical feature, wherein, in step S1-1, a search algorithm or a machine learning method is used to identify the circuit unit from the integrated circuit.

[0018] The present invention provides an integrated circuit design method, which has the following technical features. The method includes the following steps: step S2-1, an electronic design automation tool obtains a topological type and a topological dimension of a circuit based on a circuit design, and applies a corresponding implementation technology to the circuit design based on the topological type and the topological dimension and the circuit topology associated data, thereby generating a logical structure of the circuit; step S2-2, performing logic optimization on the logical structure; step S2-3, performing physical layout and routing based on the logical structure after logic optimization, wherein the circuit topology associated data is obtained by the above-mentioned circuit topology associated data construction method.

[0019] The integrated circuit design method provided by the present invention may also have such a technical feature, that the method is used to design circuits in high-performance CPUs, circuits in high-performance GPUs, circuits in high-performance DDRs, multiplier circuits with large input spaces, floating-point multiplier circuits, or XOR tree circuits with large input spaces.

[0020] The present invention provides an integrated circuit design system having the following technical features: the system comprises: a database comprising circuit topology related data; and one or more electronic design automation tools, at least for generating the logical structure of the circuit based on the circuit design and the circuit topology related data, wherein the circuit topology related data is obtained by the above-mentioned circuit topology related data construction method.

[0021] Function and Effect of the Invention

[0022] According to the circuit topology association data construction method, integrated circuit design method and system of the present invention, the circuit topology association data construction method includes the steps of analyzing the integrated circuit and extracting circuit units and attribute information, analyzing the topological similarity between the extracted circuit units, dividing the circuit units into topological set groups according to similarity, and generating topological association information for each topological set group, so that the constructed circuit topology association data can be used by EDA tools to realize specific circuit implementation based on a specific topological type. In the integrated circuit design method, the EDA tool can use the circuit topology association data to reconstruct the circuit logic structure based on a specific topological type before performing logic optimization, thereby realizing a more optimized integrated circuit design, which is conducive to solving problems such as timing, congestion and metal resource challenges in high-performance CPU and GPU design. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flow chart of a method for constructing circuit topology associated data in an embodiment of the present invention.

[0024] Figure 2 It is a logic block diagram of an integrated circuit design system in an embodiment of the present invention.

[0025] Figure 3 It is a flow chart of the integrated circuit design method in an embodiment of the present invention.

[0026] Figure 4 It is a schematic diagram of the logical structure of the cross topology structure in an embodiment of the present invention.

[0027] Figure 5 yes Figure 4 Schematic diagram of the ideal physical layout of the logical structure.

[0028] Figure 6 The invention is a flow chart of an integrated circuit design method in the prior art.

[0029] Reference numerals:

[0030] Integrated circuit design system 100 ; database 110 ; topology association information library 111 ; component definition library 112 ; timing library 113 ; netlist library 114 ; electronic design automation (EDA) tool 120 . DETAILED DESCRIPTION

[0031] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the circuit topology association data construction method, integrated circuit design method and system of the present invention are specifically described below in combination with embodiments and drawings.

[0032] This embodiment provides a circuit topology association data construction method for constructing topology association information related to a circuit topology structure, so that an EDA tool can use the topology association information to better implement the circuit of an integrated circuit.

[0033] Figure 1 4 is a flow chart of the circuit topology association data construction method in this embodiment.

[0034] like Figure 1 As shown, the circuit topology association data construction method of this embodiment specifically includes the following steps:

[0035] Step S1-1, analyzing multiple integrated circuits to extract multiple circuit units and their attribute information.

[0036] Each circuit unit includes multiple components and their connection relationships, and the attribute information of the circuit unit may include, for example, the topological type and topological dimension of the circuit unit. The topological type may be defined by the transfer function of the circuit unit, and the topological dimension includes the input and output dimensions of the circuit unit.

[0037] Specifically, in step S1 - 1 , the circuit structure of the integrated circuit is designed under analysis, and all required information is extracted using the state element naming rules and expressions, ICG (Integrated Clock Gating) enabling mode, and data relationships in the prior art.

[0038] For example, attribute information can be obtained through EDA tools. Usually, each component has its own attribute information, which may include the name of the component, logical connection relationship, component type, etc. Therefore, EDA tools can determine the attribute information of each circuit unit through circuit analysis or manually defined circuit unit size. Taking storage units as an example, storage units usually have regular naming expressions. Based on the naming, a circuit unit can be determined to be a storage unit, and then its attribute information can be extracted.

[0039] For example, the attribute information defines the unit name, function, layout information, logical relationship, etc. of the circuit unit. The unit name may include a storage unit, a computing unit, a communication bus, etc. The function indicates the purpose of the circuit topology unit, such as multiplication calculation, multiplication and accumulation calculation, storage, etc. The layout information includes the layout position of the components included in the circuit unit. For example, the layout position can be determined manually based on experience, or the layout position can also be obtained by extracting the layout information of the layout by the EDA tool. The logical relationship includes the logical connection relationship of the circuit unit, such as the input register and output register corresponding to the unit, and may also include other units that share resources with the circuit unit. The logical relationship can be obtained by the EDA tool through the front-end netlist.

[0040] Of course, the attribute information may also include more content, and the specific form of the unit name, function, layout information and logical relationship may be specifically set according to the actual needs of the circuit.

[0041] Furthermore, based on the components of the circuit unit and their connection relationships, the transfer function corresponding to each circuit unit can be obtained by analyzing the circuit type, applying relevant theorem formulas, and performing Laplace transform to define the topological type of the circuit unit.

[0042] In an alternative solution, a search algorithm or machine learning method in the prior art may be used to automatically identify circuit units with a specific structure from an integrated circuit, and further combined with the above-mentioned technology to extract the required information.

[0043] Step S1 - 2 : for each extracted topology type, analyzing the topology similarity between multiple circuit units under the topology type.

[0044] Specifically, in step S1-2, the topological similarity between two circuit units is analyzed based on the functions of the circuit units, the types and parameters of each component, the input and output dimensions, various attribute information, etc., to obtain a similarity value. Specifically, a method in the prior art can be used.

[0045] Step S1-3: dividing the multiple circuit units under the topology type into one or more topology set groups based on topology similarity.

[0046] Specifically, in step S1-3, a plurality of circuit units whose topological similarities are higher than a predetermined similarity threshold are divided into a topological set group. In this embodiment, the similarity threshold is 90%.

[0047] Furthermore, when a topology type corresponds to multiple topology cluster groups, the topological similarity between these multiple topology cluster groups is calculated, that is, the topological similarity between the circuit units of different topology cluster groups of the same topology type is calculated, and based on the topological similarity, the multiple topology cluster groups of the same topology type are further divided into one or more similar groups.

[0048] Specifically, the topological similarity between multiple circuit units in different topology collection groups under the same topology type can also be calculated based on the function, component type, attribute information, etc. of the circuit unit to obtain a similarity value, and multiple topology collection groups with similarity values ​​higher than a predetermined similarity threshold can be divided into a similarity group.

[0049] Furthermore, when a similarity group includes multiple topology set groups, the topology similarities between circuit units in different topology set groups in the same similarity group are further calculated to obtain a similarity strength percentage.

[0050] Step S1-4, based on the above attribute information, topology similarity and similarity group division information, topology association information is generated for each topology set group, that is, topology association information is generated for each specific circuit unit, and the topology association information is associated with the corresponding implementation technology.

[0051] The circuit topology association data includes specific logical structure information of multiple circuit units, corresponding implementation technologies and corresponding topology association information.

[0052] The topology association information is shown in Table 1 below:

[0053] The group number of the topology collection group Topology Type The group number of the similarity group to which the topology set belongs Topological similarity strength Dimensions 1 cross group A 90% M:N 2 Multiplier group C 100% M:N:O 3 cross group A 90% M:N 4 N:1 Selector group D 0% N:1 5 cross group B 0% M:N 6 Multiplier group C 100% M:N:O 7 XOR Tree group E 0% M:1

[0054] Table 1 is the association information table of the topology collection group.

[0055] As shown in Table 1, the topology association information includes the collection group ID of each topology collection group, the corresponding topology type, the collection group ID of the similarity group to which the topology collection group belongs, the topology similarity strength between the circuit topologies in multiple different topology collection groups in the similarity group, and the dimension information. Each piece of information is associated with a known implementation technology of a specific circuit unit, so that the automation tool can automatically apply the corresponding implementation technology based on the topology structure. The implementation technology includes the area division method, the replication method of components or assemblies in each slice area, the interconnection method of components or assemblies, and the resource sharing method.

[0056] Exemplarily, the extracted topology types include Cross Bar, Multiplier, N:1 Selection, and XOR Tree. Among them, the circuit topology with the topology type of Cross Bar is divided into three topology set groups 1, 3, and 5 according to their topological similarities, and these topology set groups are further divided into two similarity groups group A and group B according to their topological similarities. Similarity group group A contains multiple topology set groups of the same topology type, and the similarity strength between these topology set groups is 90%. Similarity group group B contains one topology set group, so its corresponding similarity strength is 0%. The same is true for other topology types, which will not be explained one by one.

[0057] Through the above steps, a database or data set containing a variety of known specific circuit units and their topological association information can be obtained. The tool used for integrated circuit design can use the database or data set to perform automatic / semi-automatic design.

[0058] This embodiment also provides an integrated circuit design system and method based on the above circuit topology association information.

[0059] Figure 2 It is a logic block diagram of the integrated circuit design system in this embodiment.

[0060] like Figure 2 As shown, the integrated circuit design system 100 includes a database 110 and one or more electronic design automation (EDA) tools 120 .

[0061] The database 110 includes a topology association information library 111 , a component definition library 112 , a timing library 113 , and a netlist library 114 .

[0062] The topology association information library 111 includes the circuit topology association data. The component definition library 112, the timing library 113 and the netlist library 114 can adopt the corresponding databases in the prior art.

[0063] The EDA tool 120 generates a logic structure (logic netlist) of a circuit based on a circuit design described in a high-level language or a hardware description language (HDL) and the circuit topology-related data.

[0064] Specifically, first, the EDA tool 120 derives the topological type and input-output dimensions of the circuit based on the behavior and logical functions of the circuit described by the high-level language or HDL, and then uses the above circuit topology association data to apply the corresponding implementation technology to the circuit, automatically performing area division, replication of components or assemblies in each slice area, and interconnection of components or assemblies and resource sharing design, thereby obtaining the logical structure of the circuit (logic netlist).

[0065] For example, in GPU design, the EDA tool 120 can use the corresponding circuit topology association data to know that there are multiple copies of the "simd" area, how to replicate the multiply-accumulate (MAC) unit in each "simd" area, and how to interconnect the MAC unit with other circuit units.

[0066] Figure 3 is a flow chart of the integrated circuit design method in this embodiment.

[0067] like Figure 3 As shown, based on the above-mentioned integrated circuit design system 100, the integrated circuit design method of this embodiment includes the following steps:

[0068] Step S2-1, the EDA tool generates a logic structure of the circuit based on the circuit design described in a high-level language or HDL and the circuit topology associated data, wherein the EDA tool applies a corresponding implementation technology to the circuit design based on the topology type of the circuit design.

[0069] Step S2-2, performing logic optimization on the logic structure of the circuit.

[0070] Step S2-3, performing initial physical layout and routing based on the logical structure after logic optimization.

[0071] Step S2-4, performing clock tree synthesis on the initial physical layout and routing.

[0072] Step S2-5, performing timing and layout optimization on the initial physical layout after clock tree synthesis to obtain an optimized physical layout.

[0073] Among them, step S2-2 to step S2-5 are integrated circuit design methods in the prior art, and thus will not be described in detail.

[0074] The following will illustrate the functions of the method and system of this embodiment with reference to specific examples.

[0075] Figure 4 It is a schematic diagram of the logical structure of the cross topology structure in this embodiment.

[0076] like Figure 4 As shown in Figure 1, an example is the circuit design of a high-performance CPU or GPU. The dynamic capability of a high-performance CPU is determined by the floating-point multipliers in its design, while the dynamic capability of a high-performance GPU is determined by the double-precision multipliers in its design. In addition, the dynamic capability of the scheduler in the CPU also requires special attention. However, high-performance CPUs and GPUs share common challenges in terms of interconnection.

[0077] Specifically, taking the circuit design of a high-performance GPU as an example, it is necessary to perform layout and routing on M source data storage (Source Data Storage) units and N multiplication-accumulation (MAC) units.

[0078] like Figure 4 As shown, in the logical structure, M source data storage units 201, 202, ..., 20m are located in one side area, N MAC units 501, 502, ..., 504 are located in the other side area, and N full cross bar interconnection units 401, 402, ..., 404 that interconnect the M source data storage units with the N MAC units are located in the center area between the two. There are a lot of wiring between the N full cross bar interconnection units and the M source data storage units.

[0079] In the case of M >> N, for example, in the case of M = 64, N = 4, the bus width of the full cross interconnect structure is 64 bits, and the full cross interconnect unit can be regarded as a 64-to-1 multiplexer (MUX), and 301~304 are the control terminals of the four MUXs. For the direction from the M source data storage units to the N MAC units, there will be 64×64×4 = 32K interconnect wirings and four sets of decoding logic to support four sets of 64-to-1 MUXs. For such layout and wiring design, the challenge is very obvious. Using the common integrated circuit design method in the prior art, logic optimization is performed first and then physical layout and wiring are performed. The M source data storage units are located on the same side, which will occupy a large amount of metal resources. The full cross interconnect structure is concentrated in the central area, which is prone to congestion problems. Therefore, for such circuit design, the existing method is prone to challenges of limited metal resources and congestion problems in decoding shared logic.

[0080] Figure 5 yes Figure 4 Schematic diagram of the ideal physical layout of the logical structure.

[0081] like Figure 5 As shown, the most ideal physical layout and wiring of the above logic structure can be obtained through the integrated circuit design method of this embodiment. The topological structure of the circuit design is a fully cross-interconnected structure of four MAC units and sixty-four source data storage units. The circuit design is symmetrical, the four MAC units are the same, and the logical connection structure of each MAC unit is also the same. Therefore, through the method of this embodiment, the EDA tool can use the above circuit topology association information to apply the corresponding implementation technology, such as a slicing implementation technology commonly used in memory design in the prior art, so as to automatically divide four slicing areas arranged in a field shape, and place the four MAC units 501~504 in the slicing areas 601~604 respectively, and make the four MAC units 501~504 close to each other, and distribute multiple source data storage units 201~20m (only eight of them are shown in the figure) in the four slicing areas 601~604 and make the source data storage units relatively located in the outer part of the entire area. In this way, multiple source data storage units are distributed in the four slicing areas instead of being concentrated on one side, and the four MUXs originally located in the central area can be distributed to the four slicing areas 601~604, so that the metal resources used can be greatly reduced, and the released metal resources can be used to set other circuit units, etc.

[0082] The conventional integrated circuit design method in the prior art is used. Figure 4 The logical layout structure shown, the placement of multiple source data storage units and multiple MAC units will obviously be difficult to access Figure 5 Placement location shown in .

[0083] Similar to the above example, the method of this embodiment can also be used for the circuit design of high-performance CPU and high-performance DDR.

[0084] In addition, the method of this embodiment can also be used for circuit design of a multiplier with a very large input space, a floating-point multiplier, and an exclusive-OR (XOR) tree with a very large input space.

[0085] Functions and Effects of the Embodiments

[0086] According to the circuit topology association data construction method, integrated circuit design method and system provided in this embodiment, the circuit topology association data construction method includes the steps of analyzing the integrated circuit and extracting the circuit unit and its attribute information, analyzing the topological similarity of the extracted circuit unit, dividing the circuit unit into topological set groups according to the similarity, and generating topological association information for each topological set group and associating it with a specific implementation technology, so that the constructed circuit topology association data can be used by EDA tools to realize specific circuit implementation based on a specific topological type. In the integrated circuit design method, the EDA tool can use the circuit topology association data to reorganize the circuit logic structure based on a specific topological type before performing logic optimization, so as to achieve a more optimized integrated circuit design, which is conducive to solving problems such as timing, congestion and metal resource challenges in high-performance CPU and GPU design.

[0087] In an embodiment, the extracted circuit units are divided into multiple topology set groups according to topology similarity analysis, and the topology set groups are further divided into multiple similarity groups. The topology association information includes the topology type, the similarity strength of the circuit topologies of different topology set groups in the similarity group, and the topology dimension. Therefore, the EDA tool uses this information to know where the circuit units similar to a certain circuit unit are, and where the interconnections between these circuit units and with other circuit units are, so that the corresponding implementation technology can be applied based on the topology type, including area division method and resource sharing method, so as to improve the performance and power of the circuit, and improve the utilization rate of known circuit units in circuit design, thereby improving the design efficiency.

[0088] Furthermore, the embodiments use a search algorithm or a machine learning method to identify circuit topology from an integrated circuit, which can efficiently and accurately identify a large number of known circuit topologies, thereby efficiently constructing circuit topology association data.

[0089] Furthermore, in the embodiment, integrated circuit design is performed under analysis, and state element naming rules and expressions, ICG and data relationships are used to extract required information, which can efficiently extract all required information, thereby efficiently constructing circuit topology related data.

[0090] The above embodiments are only used to illustrate the specific implementation of the present invention, and the present invention is not limited to the description scope of the above embodiments. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only to illustrate the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for constructing circuit topology associated data, for constructing circuit topology associated data, the data being used for use by electronic design automation tools to apply circuit implementation technology based on topology types, characterized in that: The following steps are involved: Step S1-1, analyzing the integrated circuit to extract a plurality of circuit units and their attribute information, wherein the attribute information includes a topology type defined by a circuit transfer function; Step S1-2, for each of the extracted topology types, analyzing the topology similarity between the multiple circuit units under the topology type; Step S1-3, dividing the plurality of circuit units under the topology type into one or more topology set groups based on the topology similarity; Step S1-4: generating topology association information for each topology set based on the attribute information and the topology similarity, and associating the topology association information with the corresponding implementation technology of the circuit unit, thereby obtaining the circuit topology association data.

2. The circuit topology association data construction method according to claim 1, characterized in that: in, The implementation technology includes a method of dividing regions, a method of replicating components or assemblies in each region, a method of interconnecting the components or assemblies, and a method of sharing resources. The topology association information includes the group number of each topology set group, the corresponding topology type, and the corresponding attribute information.

3. The circuit topology association data construction method according to claim 2, characterized in that: in, The attribute information includes the unit name, circuit function, layout information, and logical connection relationship with other circuit units of the circuit unit.

4. The circuit topology association data construction method according to claim 3, characterized in that: in, In step S1-3, when one topology type corresponds to multiple topology set groups, the topology similarity between the circuit units of the multiple topology set groups is also calculated, and the multiple topology set groups of the same topology type are divided into one or more similar groups according to the topology similarity. The association information further includes the group number of the similarity group to which each of the topology set groups belongs, and the topology similarity strength between the circuit units in different topology set groups in the similarity group.

5. The circuit topology association data construction method according to claim 4, characterized in that: in, In step S1-3, when a similar group includes multiple topology sets, the topology similarities between the circuit units of the multiple topology sets are calculated as the topology similarity strength. The topological association information also includes the corresponding topological similarity strength.

6. The circuit topology association data construction method according to claim 2, characterized in that: in, The topology association information also includes topology dimension information of the circuit units in the topology set.

7. The circuit topology association data construction method according to any one of claims 1 to 6, characterized in that: in, In step S1 - 1 , a search algorithm or a machine learning method is used to identify the circuit unit from the integrated circuit.

8. An integrated circuit design method, characterized in that: The following steps are involved: Step S2-1, the electronic design automation tool obtains the topology type and topology dimension of the circuit based on the circuit design, and applies the corresponding implementation technology to the circuit design based on the topology type and topology dimension and circuit topology associated data, thereby generating a logical structure of the circuit; Step S2-2, performing logic optimization on the logic structure; Step S2-3, performing physical layout and routing based on the logical structure after logical optimization, The circuit topology association data is obtained by the circuit topology association data construction method according to any one of claims 1 to 7.

9. The integrated circuit design method according to claim 8, characterized in that: The method is used to design a circuit in a high-performance CPU, a circuit in a high-performance GPU, a circuit in a high-performance DDR, a multiplier circuit with a large input space, a floating-point multiplier circuit, or an XOR tree circuit with a large input space.

10. An integrated circuit design system, characterized in that: include: A database, including circuit topology related data; as well as One or more electronic design automation tools, at least for generating a logical structure of the circuit based on the circuit design and the circuit topology associated data, The circuit topology association data is obtained by the circuit topology association data construction method according to any one of claims 1 to 7.

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