Turbo code cascade encoder and decoding method, device and storage medium in deep space communication

Abstract

The present invention provides a Turbo code cascade encoder and decoding method, device, and storage medium for deep space communication. The Turbo code cascade encoder includes an interleaver and two component encoders; the input end of the interleaver is connected to the input end of one component encoder, and the output end is connected to the input end of another component encoder; the component encoder is formed by cascading a Turbo code encoder and a short code encoder; the Turbo code encoder includes a first adder, a second adder, and a register module; the output end of the first adder is connected to the input end of the short code encoder and the register module; the output end of the register module is connected to the input end of the short code encoder and the second adder; the output end of the second adder is connected to the input end of the first adder. The present invention uses a method of cascading Turbo codes and short codes to design a Turbo code cascade encoder, which has a simple structure and is easy to implement in hardware, and can reduce the code rate to ensure communication performance.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a Turbo code cascade encoder and decoding method, device, and storage medium in deep space communication. Background Art

[0002] In the field of deep space communication, especially in harsh environments with extremely low signal-to-noise ratios, achieving reliable data transmission is a technical challenge. Although traditional spread spectrum technology can reduce the signal-to-noise ratio during communication by increasing the power of the transmitted signal, it does not improve the gain of channel coding. Therefore, providing a low-rate channel error correction code with high coding gain has become one of the key technologies to ensure communication reliability under low signal-to-noise ratio conditions.

[0003] At present, cascade codes are usually used for channel coding in extremely low signal-to-noise ratio environments. Although cascade codes can ensure the reliability of communication under low signal-to-noise ratio conditions, the current cascade coding structure either has a complex implementation process or a high decoding complexity. In addition, for the design of Turbo codes in extremely low signal-to-noise ratio environments, in order to reduce the bit rate of Turbo codes, one method is to increase the number of registers. Although this method can reduce the bit rate, it also increases the decoding complexity, which in turn leads to an increase in the decoding delay. In addition, another method is to increase the number of encoders and interleavers. This method can also reduce the bit rate, but it places higher requirements on system resources and processing power, which may affect the real-time performance and efficiency of the system.

[0004] Therefore, how to design a cascade coding structure for Turbo codes that can ensure communication reliability in extremely low signal-to-noise ratio environments, optimize the decoding process, and ensure the parallelism and throughput of hardware implementation is a technical problem that needs to be solved. Summary of the invention

[0005] In view of this, one of the purposes of the present invention is to provide a Turbo code cascade encoder and decoding method, device, and storage medium for deep space communication, which can ensure communication reliability in an extremely low signal-to-noise ratio environment, optimize the Turbo code decoding process, and have simple hardware implementation. In order to achieve the above purpose, the technical solution adopted in the embodiment of the present invention is as follows:

[0006] In the first aspect, the present invention provides a Turbo code cascade encoder for deep space communication, comprising: an interleaver and two component encoders; the input end of the interleaver is connected to the input end of one component encoder, and the output end of the interleaver is connected to the input end of another component encoder; the component encoder is formed by cascading a Turbo code encoder and a short code encoder; the Turbo code encoder comprises a first adder, a second adder and a register module; the output end of the first adder is connected to the short code encoder and the input end of the register module; the output end of the register module is connected to the short code encoder and the input end of the second adder; the output end of the second adder is connected to the input end of the first adder.

[0007] In a second aspect, the present invention provides a decoding method for a Turbo code cascade encoder in deep space communication, the method comprising: modulating the check information and system information output by the encoder, and adding noise to the modulated check information and system information through a Gaussian white noise channel; wherein the encoder is a Turbo code cascade encoder in deep space communication as described in any one of the aforementioned implementations; determining the target system information and target check information input into a SISO decoder based on the modulated check information and system information and the check information and system information to which noise has been added; inputting preset prior information, the target system information and the target check information into the SISO decoder for iterative decoding until the current number of iterations reaches a preset total number and stops, and obtaining the target decoding information after decision processing on the output information.

[0008] In a third aspect, the present invention provides a Turbo code cascade encoder decoding device for deep space communication, comprising a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the Turbo code cascade encoder decoding method for deep space communication described in the second aspect.

[0009] In a fourth aspect, the present invention provides a storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the decoding method of the Turbo code cascade encoder in deep space communication as described in the second aspect above is implemented.

[0010] The present invention provides a Turbo code cascade encoder and decoding method, device, and storage medium for deep space communication. The Turbo code cascade encoder includes an interleaver and two component encoders; the input end of the interleaver is connected to the input end of one component encoder, and the output end of the interleaver is connected to the input end of another component encoder; the component encoder is formed by cascading a Turbo code encoder and a short code encoder; the Turbo code encoder includes a first adder, a second adder, and a register module; the output end of the first adder is connected to the input end of the short code encoder and the register module; the output end of the register module is connected to the short code encoder and the input end of the second adder; the output end of the second adder is connected to the input end of the first adder. The present invention adopts a method of cascading Turbo codes and short codes to design a Turbo code cascade encoder, which has a simple structure and is easy to implement in hardware, and the encoding process and decoding process are also simple, which can reduce the code rate and ensure communication performance.

[0011] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of the structure of the first existing Turbo code encoder is shown;

[0014] Figure 2 A schematic diagram of the structure of the second existing Turbo code encoder is shown;

[0015] Figure 3 A schematic diagram of the structure of a Turbo code cascade encoder for deep space communication provided by an embodiment of the present invention is shown;

[0016] Figure 4 A partial structural schematic diagram of a Turbo code cascade encoder provided by an embodiment of the present invention is shown;

[0017] Figure 5 A schematic diagram of the structure of a Turbo code-RM code cascade encoder according to an embodiment of the present invention is shown;

[0018] Figure 6 A schematic flow chart of a Turbo code cascade encoder decoding method provided by an embodiment of the present invention is shown;

[0019] Figure 7 A schematic structural diagram of a SISO decoder provided by an embodiment of the present invention is shown;

[0020] Figure 8 A structural block diagram of a Turbo code cascade encoder-decoder device for deep space communication provided by an embodiment of the present invention is shown.

[0021] Description of the drawings: Turbo code cascade encoder-30; interleaver-301; component encoder-302; Turbo code encoder-3021; ​​short code encoder-3022; first adder-3021-1; second adder-3021-2; register module-3021-3; Turbo code cascade encoder decoding device-80; memory-801; processor-802; communication interface-803. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0024] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0025] At present, channel coding in extremely low signal-to-noise ratio environments can usually use concatenated codes. Among them, LDPC code-Hadamard code concatenated code, Turbo code-Hadamard code concatenated code, Turbo code-BCH code concatenated code and LDPC code-BCH code are all research hotspots. However, these concatenated codes all have some defects: LDPC code-Hadamard code concatenated code and Turbo code-Hadamard code concatenated code are favored due to their excellent performance stability, but this cascade structure also brings a significant increase in decoding complexity. Turbo code-BCH code concatenated code can be used under extremely low signal-to-noise ratio conditions, but the implementation process is relatively complicated and the distance between codewords cannot be guaranteed. As for LDPC code-BCH code concatenated code, BCH code mainly plays a role in improving the bit error rate, but the performance depends on the characteristics of LDPC code. Although these concatenated code schemes can improve the performance of the communication system, they are relatively complex and put forward higher requirements for the optimization of the decoding algorithm.

[0026] In addition, Turbo code design is also a research focus in extremely low signal-to-noise ratio environments. In order to reduce the bit rate of Turbo codes, there are the following methods:

[0027] See also Figure 1 , Figure 1 FIG. 1 shows a schematic diagram of the structure of the first existing Turbo code encoder. Where D represents a register, is the input bit; , , , , …, is the output of the Turbo code encoder; n is the number of registers. The core of this structural design method is to increase the number of registers. However, the more registers there are, the higher the decoding complexity and the greater the decoding delay.

[0028] See also Figure 2 , Figure 2 The structure diagram of the second existing Turbo code encoder is shown. The Turbo code encoder includes three component encoders, wherein: is the input bit of the mth component encoder, m=1, 2, 3; It is the system information output by the Turbo code encoder; , , is the bit output of the first component encoder; , , is the bit output of the second component encoder; , , is the bit output of the third component encoder. The core of this structural design is to increase the number of encoders and interleavers. This method can also reduce the bit rate, but it places higher requirements on system resources and processing power, which may affect the real-time performance and efficiency of the system.

[0029] In view of this, an embodiment of the present invention provides a Turbo code cascade encoder for use in deep space communications. Figure 3 , Figure 3 FIG. 1 shows a schematic diagram of the structure of a Turbo code cascade encoder in deep space communication provided by an embodiment of the present invention. Figure 3 The end pointed by the arrow is the input end, and the other end is the output end.

[0030] like Figure 3 As shown, the Turbo code cascade encoder 30 includes: an interleaver 301 and two component encoders 302; the input end of the interleaver 301 is connected to the input end of one component encoder 302, and the output end of the interleaver 301 is connected to the input end of the other component encoder 302;

[0031] The component encoder 302 is formed by cascading a Turbo code encoder 3021 and a short code encoder 3022; the Turbo code encoder 3021 includes a first adder 3021-1, a second adder 3021-2 and a register module 3021-3; the output end of the first adder 3021-1 is connected to the short code encoder 3022 and the input end of the register module 3021-3; the output end of the register module 3021-3 is connected to the short code encoder 3022 and the input end of the second adder 3021-2; the output end of the second adder 3021-2 is connected to the input end of the first adder 3021-1.

[0032] from Figure 3 As can be seen from the structure shown, the structure of the Turbo code cascade encoder 30 provided in the embodiment of the present invention is simple and easy to implement in hardware. At the same time, in terms of cascade code design, the embodiment of the present invention adopts cascading Turbo code and short code, so that the encoding and decoding process is also simple and can ensure communication performance.

[0033] See also Figure 4 , Figure 4The schematic diagram of a part of the structure of the Turbo code cascade encoder provided by the embodiment of the present invention is shown. The register module 3021-3 includes a plurality of registers connected in sequence; the output end of each register is connected to the input end of the short code encoder 3022; the output end of the first adder 3021-1 is connected to the input end of a register; the output ends of the last two registers in the direction away from the first adder 3021-1 are connected to the input end of the second adder 3021-2.

[0034] It should be understood that Figure 4 Only four registers are shown, but this should not be understood as a limitation on the number of registers. Users can flexibly set the number of registers according to actual needs, and the embodiment of the present invention does not limit this.

[0035] For the convenience of distinction, the embodiments of the present invention will Figure 3 The component encoder 302 in the embodiment is divided into a first component encoder and a second component encoder. Figure 3 In the embodiment, the first component encoder is connected to the input end of the interleaver 301, and the second component encoder is connected to the output end of the interleaver 301. The difference between the first component encoder and the second component encoder is that:

[0036] The first component encoder is used to encode the original bits to be encoded, output the encoded system information, and output the check information through the first short code encoder.

[0037] The second component encoder is used to encode the bits to be encoded and output the check information through the second short code encoder; wherein the bits to be encoded corresponding to the second component encoder are obtained by interleaving the original bits to be encoded by the interleaver.

[0038] Therefore, in the embodiment of the present invention, the input of the first component encoder is the original bits to be encoded, and the input of the second component encoder is the bits to be encoded after the original bits to be encoded have been interleaved.

[0039] Similarly, to distinguish Figure 3 In the two short code encoders 3022, the embodiment of the present invention describes the short code encoder cascaded with the first component encoder as the first short code encoder, and describes the short code encoder cascaded with the second component encoder as the second short code encoder.

[0040] It can be understood that in the embodiment of the present invention, the original bits to be encoded are input into the first component encoder for encoding, and the encoded system information and the check information obtained by the first short code encoder are output. The bits to be encoded are input into the second component encoder for encoding, and the second short code encoder outputs the check information. After these check information and system information are modulated and noise is added through a Gaussian white noise channel, the system information and check information received by the receiving end can be obtained, which provides an input basis for the decoder to perform decoding.

[0041] In an optional implementation, the short code encoder 3022 in the embodiment of the present invention may be, but is not limited to, a RM (Reed-Muller) code. Since the RM code can make the Euclidean distance between each codeword in the codeword set relatively large, thereby ensuring a large minimum distance between codewords, by cascading the Turbo code and the short code, both the error correction capability can be guaranteed and the encoded data can have a large minimum code distance, thereby achieving the purpose of reducing the code rate.

[0042] In an optional implementation, the RM code is designed based on the minimum code rate. In one implementation, the code length of the RM code encoder satisfies the relationship: ; Where L is the code length and Q is a positive integer. For example, L can be 2, 4, 8, 16, 32, etc., which can achieve a very low code rate.

[0043] For ease of understanding, Figure 3 and Figure 4 Based on Figure 5 , Figure 5 A schematic diagram of the structure of a Turbo code-RM code cascade encoder provided by an embodiment of the present invention is shown. In order to simplify the structure, Figure 5 In the figure, the register is replaced by D, and the first adder 3021-1 and the second adder 3021-2 are both represented by adder symbols.

[0044] exist Figure 5 middle, is the original bits to be encoded input to the first component encoder; is the bit to be encoded input to the second component encoder; is the system information output by the first component encoder; is the check information output by the RM code encoder in the first component encoder; is the check information output by the RM code encoder in the second component encoder; , , , , It is the intermediate state of the bit to be encoded and is also the input of the RM code encoder.

[0045] In the embodiment of the present invention, , as well as After modulation, we can get , as well as ,right , as well as By adding noise to the Gaussian white noise channel, the system information received by the receiver can be obtained. , Verification Information as well as .

[0046] In one embodiment of the present invention, the decoder corresponding to the Turbo code cascade encoder in the above implementation may be a SISO (Soft-InSoft-Out) decoder. For each input bit, the SISO decoder evaluates the probability of it being 0 or 1, and infers the correct value of the bit based on these probabilities, thereby retaining the real information to the maximum extent and improving the accuracy of decoding.

[0047] The following provides a decoding method based on a SISO decoder for the Turbo code cascade encoder provided in an embodiment of the present invention. Figure 6 , Figure 6 A schematic flow chart of a Turbo code cascade encoder decoding method provided by an embodiment of the present invention is shown, which may include the following steps:

[0048] S601. Modulate the check information and system information output by the encoder, and add noise to the modulated check information and system information through a Gaussian white noise channel; wherein the encoder is a Turbo code cascade encoder provided in an embodiment of the present invention.

[0049] In the embodiment of the present invention, for the convenience of description, a Turbo code-RM code cascade encoder is taken as an example, and the modulated system information is recorded as ; The modulated check information consists of two parts, respectively recorded as and ; After adding noise, the system information and check information received by the receiver are recorded as , as well as .

[0050] S602, determining target system information and target check information input to a SISO decoder according to the check information and system information after modulation and the check information and system information after adding noise;

[0051] In the embodiment of the present invention, the target system information of the SISO decoder is obtained by multiplying the modulated system information, the system information after adding noise, and the preset channel reliability. Similarly, the target check information is obtained by multiplying the modulated check information, the check information after adding noise, and the channel reliability.

[0052] In order to facilitate the description of the subsequent embodiments, taking the Turbo code-RM code cascade encoder as an example, the embodiment of the present invention here represents the original bits input to the encoder at the kth time as ,So The system information at the kth moment output after the Turbo code-RM code cascade encoder can be expressed as , written simply as , Similarly, the check information at the kth moment output by the short code encoder 3022 is expressed as , written simply as , then the target check information of the SISO decoder can finally be expressed as .

[0053] S603, input the preset prior information, target system information and target verification information into the SISO decoder for iterative decoding, and stop when the number of iterations reaches the preset total number of times, and obtain the target decoding information after decision processing on the output information.

[0054] To understand the above decoding process, please refer to Figure 7 , Figure 7 FIG. 1 is a schematic diagram showing the structure of a SISO decoder in an embodiment of the present invention. The SISO decoder mainly includes a first SISO decoder and a second component decoder, a first interleaver and a second interleaver, a deinterleaver and a decision device, and the connection relationship between them is as follows: Figure 7 As shown, no further description is given here.

[0055] also, Figure 7 The minus sign drawn near the adder in indicates that the subtraction process is completed by the adder. Figure 7 Still taking the Turbo code-RM code cascade encoder as an example, the various input information of the SISO decoder is drawn. Figure 7 The parameters involved are explained as follows:

[0056] and : is the check information input to the first SISO decoder, is the check information input to the second SISO decoder; wherein, is the channel reliability, , is the noise variance of the Gaussian white noise channel.

[0057] and is the system information input to the first SISO decoder, Yes The system information is input into the second SISO decoder after being interleaved by the second interleaver.

[0058] and : is the prior information input to the first SISO decoder, is the prior information input to the second SISO decoder. It is the original bit input into the Turbo code-RM code cascade encoder at the kth time.

[0059] and : is the posterior probability of the first SISO decoder output, is the posterior probability of the second SISO decoder output;

[0060] and : is the first external information output by the first SISO decoder, is the second external information output by the second SISO decoder; wherein, , as well as Satisfies the relationship: ; , as well as Satisfies the relationship: .

[0061] based on Figure 7 The decoding architecture shown in FIG. 1 is used to describe step S603 in detail in the embodiment of the present invention. Step S603 may include the following steps:

[0062] Step a1: Determine the target inputs corresponding to the first SISO decoder and the second SISO decoder respectively from the target system information and the target verification information, and use the prior information as the initial prior probability value of the first SISO decoder.

[0063] from Figure 7 It can be seen that the target input corresponding to the first SISO decoder and the second SISO decoder respectively includes three parts: input system information, input verification information and prior information.

[0064] For the first SISO decoder, the embodiment of the present invention converts the modulated system information corresponding to the first component encoder into , System information after adding noise and channel reliability The product of As input system information, the modulated calibration information , Verification information after adding noise and channel reliability The product of As input verification information. At the same time, the prior information is the initial prior probability value, that is, zero.

[0065] For the second SISO decoder, the embodiment of the present invention converts the input system information of the first component encoder into After the second interleaver performs interleaving, the As input system information, the modulated calibration information , Verification information after adding noise Channel reliability The product of As the input check information of the second SISO decoder.

[0066] That is, for the Turbo code-RM code cascade encoder and SISO decoder, the first component encoder corresponds to the first SISO decoder, and the second component encoder corresponds to the second SISO decoder, so that the input of each component decoder can be quickly determined.

[0067] In the embodiment of the present invention, the initial prior probability value of the first SISO decoder is 0. In the subsequent iterative decoding process, the prior probability value of the first SISO decoder is obtained by deinterleaving the second external information output by the second SISO decoder; the prior probability value of the second SISO decoder is obtained by interleaving the first external information output by the first SISO decoder.

[0068] Step a2: input the target input and the prior probability value corresponding to the first SISO decoder into the first SISO decoder for decoding, and output the first external information.

[0069] See also Figure 7 ,Will , and After inputting the first SISO decoder, the output is the posterior probability , the recursive formula of the posterior probability will be introduced in the subsequent content. Then through the formula The first external information corresponding to the first SISO decoder can be calculated

[0070] Step a3: Input the first extrinsic information into the first interleaver to obtain the prior probability value of the second SISO decoder, and input the target input and the prior probability value corresponding to the second SISO decoder into the second SISO decoder for decoding, and output the second extrinsic information.

[0071] Continue to see Figure 7 , the first external information After being input into the first interleaver for processing, the prior probability value of the second SISO decoder is obtained , then , and After inputting the second SISO decoder, the output is the posterior probability , and then by the formula The second external information of the second SISO decoder can be calculated .

[0072] It should be noted that for the first external information in step a2 and the second external information in step a3 After being calculated by the above two formulas respectively, they can also be normalized using a preset normalization parameter alp. Alp can be flexibly set, such as 0.7 or 0.75, which is not limited in the embodiment of the present invention.

[0073] Step a4: inputting the second external information into the deinterleaver to obtain a priori probability value of the first SISO decoder;

[0074] Return to step a2 and stop until the current number of iterations reaches the preset total number, and then execute step a5: the output of the second SISO decoder is processed by the decision device to obtain target decoding information.

[0075] By performing iterative decoding in the above manner, the first SISO decoder and the second SISO decoder complete one decoding each, which is considered one iteration. If the current number of iterations reaches the preset total number, the iterative decoding can be stopped, and the posterior probability of the output of the second SISO decoder can be obtained at this time. , and the decision is made by the decision device, the decision formula is:

[0076]

[0077] The judgment formula means: If , then it means The decoding result is 1, otherwise The decoding result is 0.

[0078] The following describes the recursive process of the posterior probability in the embodiment of the present invention. For the convenience of description, the embodiment of the present invention converts the posterior probability output by the first SISO decoder into and the posterior probability output by the second SISO decoder Unified abbreviation , the calculation formula is as follows:

[0079]

[0080] The meaning of each parameter in the formula is as follows:

[0081] and : is the current state of the register record, It is the state before the current state.

[0082] : is a certain decoding moment.

[0083] and : Represents the state at the kth moment The forward recursive probability of The state at the kth moment is The backward recursive probability of .

[0084] and : The state at time k-1 is The forward recursive probability of The state at time k+1 is The backward recursive probability of ; where, and Satisfies the following formula:

[0085]

[0086]

[0087] in, Indicates that at the kth moment, from the state Go to Status The transition probability of , =1,2; represents the kth original bit to be encoded input into the Turbo code-RM code cascade encoder When , the RM code encoder outputs the verification information.

[0088] and : represents the kth moment From the state Go to Status The transition probability, represents the kth moment From the state Go to Status The transition probability.

[0089] and : Indicates that when the Turbo code-RM code cascade encoder input When it is 0, the state Go to Status Take the maximum value among all the probabilities of Indicates that when the Turbo code-RM code cascade encoder input When it is 1, the state Go to Status Take the maximum value among all the probabilities.

[0090] In summary, the Turbo code cascade encoder provided by the embodiment of the present invention can ensure stable decoding performance under extremely low signal-to-noise ratio conditions, while also ensuring decoding parallelism and throughput. Reduce decoding delay.

[0091] The embodiment of the present invention also provides a Turbo code cascade encoder decoding device 80 (hereinafter referred to as electronic device), which is applied in deep space communication. Figure 8 , Figure 8 The structural block diagram of the Turbo code cascade encoder-decoder device in deep space communication provided by an embodiment of the present invention is shown, including: a memory 801, a processor 802 and a communication interface 803. The memory 801, the processor 802 and the communication interface 803 are directly or indirectly electrically connected to each other to realize data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines.

[0092] Optionally, the bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0093] In the embodiment of the present invention, the processor 802 may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiment of the present invention. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present invention may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor. The software module may be located in the memory 801, and the processor 802 reads the program instructions in the memory 801 and completes the steps of the above method in combination with its hardware.

[0094] In the embodiment of the present invention, the memory 801 may be a non-volatile memory, such as a hard disk (HDD) or a solid-state drive (SSD), etc., or a volatile memory (Volatile Memory), such as RAM. The memory may also be any other medium that can be used to carry or store the desired program executable code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in the embodiment of the present invention may also be a circuit or any other device that can realize a storage function, for storing instructions and / or data.

[0095] The memory 801 can be used to store software programs and modules, such as the instructions / modules of the Turbo code cascade encoder or SISO decoder provided in the embodiment of the present invention, which can be stored in the memory 801 or in the operating system (OS) of the solidified electronic device in the form of software or firmware. The processor 802 executes the software programs and modules stored in the memory 801 to perform various functional applications and data processing. The communication interface 803 can be used to communicate signaling or data with other node devices.

[0096] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0097] Understandably, Figure 8 The structure shown is for illustration only. The electronic device may also include Figure 8 More or fewer components as shown, or with Figure 8 Different configurations shown. Figure 8 The components shown may be implemented in hardware, software or a combination thereof.

[0098] The electronic device may also include a network device and / or a user device. The network device includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud consisting of a large number of hosts or network servers based on cloud computing.

[0099] Based on the above embodiments, the present application further provides a storage medium, in which a computer program is stored. When the computer program is executed by a computer, the computer executes the Turbo code cascade encoder decoding method provided in the above embodiments.

[0100] Based on the above embodiments, an embodiment of the present invention further provides a computer program. When the computer program is run on a computer, the computer executes the Turbo code cascade encoder decoding method provided in the above embodiments.

[0101] Based on the above embodiments, an embodiment of the present invention further provides a chip, which is used to read a computer program stored in a memory and to execute the Turbo code cascade encoder decoding method provided in the above embodiments.

[0102] An embodiment of the present invention further provides a computer program product, comprising instructions, which, when executed on a computer, enables the computer to execute the Turbo code cascade encoder decoding method provided in the above embodiment.

[0103] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by instructions. These instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0104] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0105] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0106] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A Turbo code cascade encoder for deep space communication, characterized in that: include: an interleaver and two component encoders; The input end of the interleaver is connected to the input end of one component encoder, and the output end of the interleaver is connected to the input end of another component encoder; The component encoder is formed by cascading a Turbo code encoder and a short code encoder; the Turbo code encoder includes a first adder, a second adder and a register module; the output end of the first adder is connected to the short code encoder and the input end of the register module; the output end of the register module is connected to the short code encoder and the input end of the second adder; the output end of the second adder is connected to the input end of the first adder; The short code encoder is an RM code encoder; The code length of the RM code encoder satisfies the relationship: ; Wherein, L is the code length and Q is a positive integer.

2. The Turbo code cascade encoder for deep space communication according to claim 1, characterized in that: The register module includes a plurality of registers connected in sequence; the output end of each register is connected to the input end of the short code encoder; the output end of the first adder is connected to the input end of a register; and the output ends of the last two registers in the direction away from the first adder are connected to the input end of the second adder.

3. The Turbo code cascade encoder for deep space communication according to claim 1, characterized in that: The two component encoders are a first component encoder and a second component encoder; the short code encoder includes a first short code encoder and a second short code encoder; The first component encoder is used to encode the original bits to be encoded, output the encoded system information, and output the check information through the first short code encoder; The interleaver is used to perform interleaving processing on the original bits to be encoded to obtain bits to be encoded of the second component encoder; The second component encoder is used to encode the bits to be encoded and output check information through the second short code encoder.

4. The Turbo code cascade encoder for deep space communication according to claim 1, characterized in that: The decoder corresponding to the Turbo code cascade encoder is the SISO decoder.

5. A method for decoding Turbo code cascade encoders in deep space communication, characterized in that: The method comprises: Modulating the check information and system information output by the encoder, and adding noise to the modulated check information and system information through a Gaussian white noise channel; wherein the encoder is a Turbo code cascade encoder for deep space communication as claimed in any one of claims 1 to 4; Determine the target system information and target check information input to the SISO decoder according to the check information and system information after the modulation and the check information and system information after adding noise; Inputting the preset prior information, the target system information and the target verification information into the SISO decoder for iterative decoding until the current number of iterations reaches the preset total number of iterations, and then performing decision processing on the output information to obtain the target decoding information; The SISO decoder comprises a first SISO decoder and a second SISO decoder, a first interleaver, a deinterleaver and a decision device; Inputting the preset prior information, the target system information and the target verification information into the SISO decoder for iterative decoding until the current number of iterations reaches the preset total number of iterations and then stopping, and performing decision processing on the output information to obtain target decoding information, including: Determine the target inputs corresponding to the first SISO decoder and the second SISO decoder respectively from the target system information and the target verification information, and use the prior information as an initial prior probability value of the first SISO decoder; Inputting the target input and the prior probability value corresponding to the first SISO decoder into the first SISO decoder for decoding, and outputting first external information; Input the first extrinsic information into the first interleaver for processing to obtain a priori probability value of the second SISO decoder, and input the target input and the priori probability value corresponding to the second SISO decoder into the second SISO decoder for decoding, and output second extrinsic information; Inputting the second external information into the deinterleaver for processing to obtain a priori probability value of the first SISO decoder; Return to the step of inputting the target input corresponding to the first SISO decoder and the prior probability value into the first SISO decoder for decoding, and outputting the first external information, until the current number of iterations reaches the preset total number of iterations; The output of the second SISO decoder is processed by the decision device to obtain the target decoding information.

6. A Turbo code cascade encoder decoding device for deep space communication, characterized in that: It includes a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor can execute the machine executable instructions to implement the Turbo code cascade encoder decoding method in deep space communication as described in claim 5.

7. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the decoding method of Turbo code cascade encoder in deep space communication as claimed in claim 5 is implemented.

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