A multi-stability circuit based on fractional-order discrete memristors of different orders

Abstract

The invention discloses a multi-stability circuit based on fractional-order discrete memristors of different orders, comprising: a first fractional-order discrete memristor circuit, a second fractional-order discrete memristor circuit, a third fractional-order discrete memristor circuit and a fractional-order Logistic mapping circuit. The order selection range of the fractional-order discrete memristors of different orders of the invention is 0-1, and the introduction of different orders makes the fractional-order discrete memristor circuit have more flexible and rich dynamic characteristics and memory performance, which can better adapt to the needs of different systems, and the multi-stability circuit based on fractional-order discrete memristors of different orders has complex and rich chaotic characteristics such as initial value regulation, symmetric attractor, amplitude bidirectional regulation and offset enhancement.

Description

Technical Field

[0001] The invention belongs to the technical field of chaotic circuits, and in particular relates to a multi-stability circuit based on fractional-order discrete memristors of different orders. Background Art

[0002] The emergence of nano-memristors is expected to realize non-volatile random access memory, which can store and process information well. In subsequent research, memristors have been widely used in many fields such as nonlinear circuits, neural networks, and secure communications due to their small size, low energy consumption, high integration, and non-volatility.

[0003] For a long time, the research on memristors has been conducted in the continuous domain, and the discrete domain has not been discussed until recent years. Traditional continuous memristors can usually work at continuous time and level, but their application in digital circuits is limited because digital circuits usually process discrete signals and states, while discrete memristors are easier to integrate into digital circuits because their resistance values ​​can only take a finite number of discrete values, and are applied in discrete domain systems. The Chinese invention patent with publication number CN114822641A discloses a discrete memristor analog circuit and its design method, which uses an analog circuit to realize a discrete memristor constructed by combining a differential operator, solving the problem of limited accuracy of the existing discrete memristor equivalent circuit. The Chinese invention patent with publication number CN117933323A discloses a mapping method based on dual discrete memristors, using two periodic discrete memristors to construct two new dual memristor hyperchaotic mapping models, and proposes a simple method for obtaining hyperchaotic and extremely multi-stability discrete mapping based on memristors. However, the discrete memristors of the above inventions are all integer-order. Currently, the research on fractional-order discrete memristors is far from enough, especially the inability to improve the complex multi-stability of fractional-order discrete memristor circuits of different orders. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a multi-stability circuit based on fractional-order discrete memristors of different orders.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] A multi-stability circuit based on fractional-order discrete memristors of different orders, comprising: a first fractional-order discrete memristor circuit, a second fractional-order discrete memristor circuit, a third fractional-order discrete memristor circuit and a fractional-order Logistic mapping circuit; the order of the first fractional-order discrete memristor circuit is , the order of the second fractional-order discrete memristor circuit is , the order of the third fractional-order discrete memristor circuit is ; The first fractional-order discrete memristor circuit is used to generate chaotic sequences , the second fractional-order discrete memristor circuit is used to generate chaotic sequences , the third fractional-order discrete memristor circuit is used to generate chaotic sequences , fractional-order logistic mapping circuit is used to generate chaotic sequence ;in,

[0007] The expressions of the first fractional-order discrete memristor circuit, the second fractional-order discrete memristor circuit, and the third fractional-order discrete memristor circuit are:

[0008]

[0009]

[0010]

[0011] in, , represents the memristor output voltage, represents the memristor input current, represents the amount of charge, represents the memristor value, represents the parameters of the memristor model, represents the value of the DC power supply V1 in the first fractional-order discrete memristor circuit, represents the value of the DC power supply V2 in the first fractional-order discrete memristor circuit, is the coefficient of historical data, represents the Grunwald-Letnikov type fractional-order difference definition, represents the order of fractional differences of different selected values, Indicates the current iteration number, Indicates the memory length;

[0012] The circuit expression of fractional-order logistic mapping is:

[0013]

[0014] in, ; is the system parameter;

[0015] The multi-stability circuit expressions of fractional-order discrete memristors of different orders are:

[0016]

[0017] in, , , ,L=3, ; and are the three fractional-order discrete memristors with different values ​​between 0 and 1, represents the value of the DC power supply VA1 in the first fractional-order difference operator circuit, represents the value of the DC power supply VB1 in the second fractional-order differential operator circuit, represents the value of the DC power supply VC1 in the third fractional-order difference operator circuit; and is the coupling parameter of the memristor coupled chaotic mapping, the value of the DC power supply V4 in the first fractional-order discrete memristor circuit, and the parameter Indicates the value of the DC power supply V6 in the second fractional-order discrete memristor circuit, using the parameter Indicates the value of the DC power supply V8 in the third fractional-order discrete memristor circuit, using the parameter express; is the system parameter, represents the value of the DC power supply V10 in the fractional-order logistic mapping circuit, Represents the values ​​of DC power supplies VA6, VB6, and VC6 in the first fractional-order discrete memristor circuit, the second fractional-order discrete memristor circuit, and the third fractional-order discrete memristor circuit.

[0018] Preferably, the first fractional-order discrete memristor circuit comprises a first multiplier M1, an input end of the first multiplier M1 is connected to an output end of a second sample-and-hold SAMP2 of the first fractional-order differential operator circuit, and an output end of the first multiplier M1 is connected to an input end of a second multiplier M2;

[0019] The negative electrode of the DC power supply V1 is grounded, and the positive electrode of the DC power supply V1 is connected to the non-inverting input terminal of the first voltage follower U1; the inverting input terminal of the first voltage follower U1 is connected to the output terminal of the first voltage follower U1, and the output terminal of the first voltage follower U1 is connected to the input terminal of the second multiplier M2;

[0020] The input end of the second multiplier M2 is connected to the output end of the first multiplier M1 and the output end of the first voltage follower U1 respectively, and the output end of the second multiplier M2 is connected to the inverting input end of the first inverting adder U3 via the first resistor R1; the non-inverting input end of the first inverting adder U3 is grounded;

[0021] The negative electrode of the DC power supply V2 is grounded, and the positive electrode of the DC power supply V2 is connected to the non-inverting input terminal of the second voltage follower U2; the inverting input terminal of the second voltage follower U2 is connected to the output terminal of the second voltage follower U2, and the output terminal of the second voltage follower U2 is connected to the input terminal of the third multiplier M3;

[0022] The input end of the third multiplier M3 is respectively connected to the output end of the second sample holder of the first fractional-order differential operator circuit and the output end of the second voltage follower U2, and the output end of the third multiplier M3 is connected to the inverting input end of the first inverting adder U3 via the second resistor R2;

[0023] The negative electrode of the DC power supply V3 is grounded, and the positive electrode of the DC power supply V3 is connected to the inverting input terminal of the first inverting adder U3 via the third resistor R3;

[0024] Two ends of the fourth resistor R4 are respectively connected to the inverting input end and the output end of the first inverting adder U3; the output end of the first inverting adder U3 is connected to the inverting input end of the first inverter U4 via the fifth resistor R5;

[0025] The non-inverting input terminal of the first inverter U4 is grounded, a sixth resistor R6 is connected between the inverting input terminal and the output terminal of the first inverter U4, and the output terminal of the first inverter U4 is connected to the input terminal of the fourth multiplier M4;

[0026] The negative electrode of the DC power supply V4 is grounded, and the positive electrode of the DC power supply V4 is connected to the non-inverting input terminal of the third voltage follower U5; the inverting input terminal of the third voltage follower U5 is connected to the output terminal of the third voltage follower U5, and the output terminal of the third voltage follower U5 is connected to the input terminal of the fourth multiplier M4;

[0027] The input end of the fourth multiplier M4 is connected to the output end of the first inverter U4 and the output end of the third voltage follower U5 respectively, and the output end of the first inverter U4 serves as the output end of the first fractional-order discrete memristor circuit to output a memristor signal .

[0028] Preferably, the second fractional-order discrete memristor circuit includes a fifth multiplier M5, an input end of the fifth multiplier M5 is connected to the output end of the eighth sample holder SAMP8 of the second fractional-order differential operator circuit, an output end of the fifth multiplier M5 is connected to the inverting input end of the second inverting adder U6 via a seventh resistor R7, and a non-inverting input end of the second inverting adder U6 is grounded;

[0029] The negative electrode of the DC power supply V5 is grounded, the positive electrode of the DC power supply V5 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the inverting input end of the second inverting adder U6;

[0030] Two ends of the ninth resistor R9 are respectively connected to the inverting input end and the output end of the second inverting adder U6; the output end of the second inverting adder U6 is connected to the inverting input end of the second inverter U7 via the tenth resistor R10;

[0031] The non-inverting input terminal of the second inverter U7 is grounded, an eleventh resistor R11 is connected between the inverting input terminal and the output terminal of the second inverter U7, and the output terminal of the second inverter U7 is connected to the input terminal of the sixth multiplier M6;

[0032] The negative electrode of the DC power supply V6 is grounded, and the positive electrode of the DC power supply V6 is connected to the non-inverting input terminal of the fourth voltage follower U8; the inverting input terminal of the fourth voltage follower U8 is connected to the output terminal of the fourth voltage follower U8, and the output terminal of the fourth voltage follower U8 is connected to the input terminal of the sixth multiplier M6;

[0033] The input end of the sixth multiplier M6 is connected to the output end of the second inverter U7 and the output end of the fourth voltage follower U8 respectively, and the output end of the second inverter U7 serves as the output end of the second fractional-order discrete memristor circuit to output a memristor signal .

[0034] Preferably, the third fractional-order discrete memristor circuit includes a seventh multiplier M7, an input end of the seventh multiplier M7 is connected to the output end of the fourteenth sample holder SAMP14 of the third fractional-order differential operator circuit, the output end of the seventh multiplier M7 is connected to the inverting input end of the third inverting adder U9 via the twelfth resistor R12, and the non-inverting input end of the third inverting adder U9 is grounded;

[0035] The negative electrode of the DC power supply V7 is grounded, the positive electrode of the DC power supply V7 is connected to one end of the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is connected to the inverting input end of the third inverting adder U9;

[0036] Two ends of the fourteenth resistor R14 are respectively connected to the inverting input terminal and the output terminal of the third inverting adder U9; the output terminal of the third inverting adder U9 is connected to the inverting input terminal of the third inverter U10 via the fifteenth resistor R15;

[0037] The non-inverting input terminal of the third inverter U10 is grounded, a sixteenth resistor R16 is connected between the inverting input terminal and the output terminal of the third inverter U10, and the output terminal of the third inverter U10 is connected to the input terminal of the eighth multiplier M8;

[0038] The negative electrode of the DC power supply V8 is grounded, and the positive electrode of the DC power supply V8 is connected to the non-inverting input terminal of the fifth voltage follower U11; the inverting input terminal of the fifth voltage follower U11 is connected to the output terminal of the fifth voltage follower U11, and the output terminal of the fifth voltage follower U11 is connected to the input terminal of the eighth multiplier M8;

[0039] The input end of the eighth multiplier M8 is connected to the output end of the third inverter U10 and the output end of the fifth voltage follower U11 respectively, and the output end of the third inverter U10 serves as the output end of the third fractional-order discrete memristor circuit to output a memristor signal .

[0040] Preferably, the fractional-order Logistic mapping circuit includes a ninth multiplier M9, an input end of the ninth multiplier M9 is connected to the output end of the eighth multiplier M8 of the third fractional-order discrete memristor circuit and the output end of the twentieth sample holder SAMP20, and the output end of the ninth multiplier M9 is connected to the inverting input end of the fourth inverting adder U14 via the twentieth resistor R20; the non-inverting input end of the fourth inverting adder U14 is grounded;

[0041] The input end of the tenth multiplier M10 is respectively connected to the output end of the fourth multiplier M4 of the first fractional-order discrete memristor circuit and the output end of the twentieth sample holder SAMP20, and the output end of the tenth multiplier M10 is connected to the input end of the eleventh multiplier M11; the output end of the eleventh multiplier M11 is connected to the inverting input end of the fourth inverting adder U14 via the twenty-first resistor R21;

[0042] The positive electrode of the DC power supply V9 ​​is grounded, and the negative electrode of the DC power supply V9 ​​is connected to the inverting input terminal of the fifth inverting adder U12 via the eighteenth resistor R18; the non-inverting input terminal of the fifth inverting adder U12 is grounded;

[0043] One end of the seventeenth resistor R17 is connected to the output end of the twentieth sample holder SAMP20, and the other end of the seventeenth resistor R17 is connected to the inverting input end of the fifth inverting adder U12; two ends of the nineteenth resistor R19 are respectively connected to the inverting input end and the output end of the fifth inverting adder U12;

[0044] The input end of the twelfth multiplier M12 is respectively connected to the output end of the fifth inverting adder U12 and the output end of the twentieth sample holder SAMP20, and the output end of the twelfth multiplier M12 is connected to the input end of the thirteenth multiplier M13;

[0045] The negative electrode of the DC power supply V10 is grounded, and the positive electrode of the DC power supply V10 is connected to the non-inverting input terminal of the sixth voltage follower U13; the inverting input terminal of the sixth voltage follower U13 is connected to the output terminal of the sixth voltage follower U13, and the output terminal of the sixth voltage follower U13 is connected to the input terminal of the thirteenth multiplier M13;

[0046] The input end of the thirteenth multiplier M13 is connected to the output end of the twelfth multiplier M12 and the output end of the sixth voltage follower U13 respectively, and the output end of the thirteenth multiplier M13 is connected to the inverting input end of the fourth inverting adder U14 via the twenty-second resistor R22;

[0047] The negative electrode of the DC power source V11 is grounded, and the positive electrode of the DC power source V11 is connected to the inverting input terminal of the fourth inverting adder U14 via the twenty-third resistor R23;

[0048] Two ends of the twenty-fourth resistor R24 ​​are respectively connected to the inverting input terminal and the output terminal of the fourth inverting adder U14; the output terminal of the fourth inverting adder U14 is connected to the inverting input terminal of the fourth inverter U15 via the twenty-fifth resistor R25;

[0049] The non-inverting input terminal of the fourth inverter U15 is grounded, a twenty-sixth resistor R26 is connected between the inverting input terminal and the output terminal of the fourth inverter U15, and the output terminal of the fourth inverter U15 is connected to the input terminal of the nineteenth sample holder;

[0050] The input end of the nineteenth sample holder SAMP19 is connected to the output end of the fourth inverter U15, and the output end of the nineteenth sample holder SAMP19 is connected to the input end of the twentieth sample holder SAMP20; the control end of the nineteenth sample holder SAMP19 and the control end of the twentieth sample holder SAMP20 are respectively connected to the input end and the output end of the NOT gate A3, and the output end of the twentieth sample holder SAMP20 serves as the output end of the fractional-order Logistic mapping circuit to output a chaotic signal .

[0051] Preferably, the first fractional-order differential operator circuit includes a pulse signal V01, and the pulse signal V01 and a NAND gate A1, sample holders SAMP1, SAMP2, SAMP3, SAMP4, SAMP5, and SAMP6 constitute a sample-hold circuit to achieve output of iterative charges;

[0052] The inverting adder UA7, the DC power supplies VA1, VA2, VA3, VA4, VA5, VA6, the voltage followers UA1, UA4, UA5, UA6, the resistors RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, RA11, the inverting adders UA2, UA3 form an inverting adding circuit to realize the iterative accumulation process of the charge;

[0053] Inverter UA8 and resistors RA12 and RA13 form an inverting circuit for restoring the iterated value to a positive value;

[0054] The value of the DC power supply VA1 is used to realize the first fractional-order discrete memristor circuit order The output end of the sample-and-hold circuit SAMP2 is used as the output end of the first fractional-order differential operator circuit to output the first fractional-order discrete memristor internal charge .

[0055] Preferably, the second fractional-order differential operator circuit includes a pulse signal V02, and the pulse signal V02 and a NAND gate A2, sample holders SAMP7, SAMP8, SAMP9, SAMP10, SAMP11, and SAMP12 form a sample-hold circuit to achieve output of iterative charges;

[0056] The inverting adder UB7, the DC power supplies VB1, VB2, VB3, VB4, VB5, VB6, the voltage followers UB1, UB4, UB5, UB6, the resistors RB1, RB2, RB3, RB4, RB5, RB6, RB7, RB8, RB9, RB10, RB11, the inverting adders UB2 and UB3 form an inverting adding circuit to realize the iterative accumulation process of the charge;

[0057] Inverter UB8 and resistors RB12 and RB13 form an inverting circuit for restoring the iterated value to a positive value;

[0058] The value of the DC power supply VB1 is used to realize the second fractional-order discrete memristor circuit order The output end of the sample-and-hold circuit SAMP8 is used as the output end of the second fractional-order differential operator circuit to output the internal charge of the second fractional-order discrete memristor. .

[0059] Preferably, the third fractional-order differential operator circuit includes a pulse signal V03, and the pulse signal V03 and a NAND gate A3, sample holders SAMP13, SAMP14, SAMP15, SAMP16, SAMP17, and SAMP18 constitute a sample-and-hold circuit to achieve output of iterative charges;

[0060] The inverting adder UC7, the DC power supplies VC1, VC2, VC3, VC4, VC5, VC6, the voltage followers UC1, UC4, UC5, UC6, the resistors RC1, RC2, RC3, RC4, RC5, RC6, RC7, RC8, RC9, RC10, RC11, the inverting adders UC2, UC3 form an inverting adding circuit to realize the iterative accumulation process of the charge;

[0061] Inverter UC8 and resistors RC12 and RC13 form an inverting circuit for restoring the iterated value to a positive value;

[0062] The value of the DC power supply VC1 is used to realize the third fractional-order discrete memristor circuit order The output end of the sample-and-hold circuit SAMP14 is used as the output end of the third fractional-order differential operator circuit to output the internal charge of the third fractional-order discrete memristor. .

[0063] The present invention combines fractional-order discrete memristors of different orders, that is, The first fractional-order discrete memristor circuit of The second fractional-order discrete memristor circuit of The third fractional-order discrete memristor circuit is combined with the fractional-order Logistic mapping circuit to construct a fractional-order discrete memristor coupled Logistic mapping circuit of different orders. Based on the advantages of fractional-order global memory characteristics, the fractional-order discrete memristor circuit adopts the Grunwald-Letnikov fractional-order differential definition, which can capture the long-term dynamic behavior of the system. At the same time, the combination of fractional-order discrete memristors of different orders makes the order of the memristor not limited to a uniform value. By selecting fractional-order discrete memristors of different orders, the stability of the system can be adjusted to achieve more flexible dynamic characteristics. The different orders of fractional-order discrete memristors reflect the different memory effects of the system, which can more comprehensively describe the dynamic behavior and nonlinear characteristics of the system and better adapt to the needs of different systems. The analysis of dynamic characteristics shows that this fractional-order discrete memristor circuit of different orders has more complex and rich chaotic characteristics than the general integer-order discrete memristor circuit, and is more practical and more conducive to the further application of discrete memristors in discrete domain systems and digital circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0065] Figure 1 A structural framework diagram of a multi-stability circuit based on fractional-order discrete memristors of different orders according to an embodiment of the present invention;

[0066] Figure 2 It is an overall circuit schematic diagram of a multi-stability circuit based on fractional-order discrete memristors of different orders according to an embodiment of the present invention;

[0067] Figure 3 A schematic diagram of a fractional-order logistic mapping circuit of a multi-stability circuit based on fractional-order discrete memristors of different orders and a chaotic attractor plane of a first fractional-order discrete memristor circuit according to an embodiment of the present invention;

[0068] Figure 4 A schematic diagram of a coexistence attractor plane for initial value control of a multi-stability circuit based on fractional-order discrete memristors of different orders according to an embodiment of the present invention;

[0069] Figure 5 A schematic diagram of a symmetric attractor plane for bidirectional amplitude regulation induced by a system parameter d of a multi-stability circuit based on fractional-order discrete memristors of different orders according to an embodiment of the present invention;

[0070] Figure 6 Schematic diagram of the offset enhancement attractor plane induced by the offset control amount m of the multi-stability circuit based on fractional-order discrete memristors of different orders according to an embodiment of the present invention; wherein the left figure is the coupling parameter Schematic diagram of the offset enhanced attractor plane, with the right figure showing the coupling parameters Schematic diagram of the offset-enhanced attractor plane. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0072] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0073] Embodiment 1:

[0074] like Figure 1 , 2 As shown, an embodiment of the present invention provides a multi-stability circuit based on fractional-order discrete memristors of different orders, including three fractional-order discrete memristors of different orders: The first fractional-order discrete memristor, the order is The second fractional-order discrete memristor with an order of The third fractional-order discrete memristor; the input pulse signals V01, V02, and V03 are all square wave signals, with a sampling frequency of 60KHz and a sampling amplitude of 6V;

[0075] When combining the Grunwald-Letnikov fractional-order forward difference operator to calculate the fractional-order discrete system, taking the solution of the first fractional-order discrete memristor as an example, its mathematical expression is:

[0076]

[0077] in, The coefficient representing the historical data changes with the memory length n, but as n increases, The value of converges quickly to 0. In actual calculation, n cannot be infinite. Usually a suitable summation range is selected, which is called the memory length and is represented by L.

[0078] Among them, L is taken as 3, and the calculation equation for the charge is adjusted to:

[0079]

[0080] Similarly, the charges of the second and third fractional-order discrete memristors can be solved. The mathematical models of fractional-order discrete memristor systems of different orders can be rewritten as:

[0081]

[0082] in, Represents the order of the three fractional-order discrete memristors, with a value range of 0-1. When the value of changes, the order of the corresponding fractional-order discrete memristor changes, so By taking different values ​​respectively, there are three fractional-order discrete memristors of different orders that together construct fractional-order discrete memristor circuits of different orders.

[0083] Furthermore, analog circuits were used to realize fractional-order discrete memristor systems of different orders constructed by combining fractional-order differential operators. On the one hand, this can verify the physical significance of multi-stability circuits of fractional-order discrete memristors of different orders, and on the other hand, it can further expand the application research of discrete memristor system models.

[0084] According to the mathematical model expressions of fractional-order discrete memristor systems of different orders, analog circuits are implemented in combination with analog devices. The multi-stability circuits of fractional-order discrete memristors of different orders are designed, including a first fractional-order discrete memristor circuit, a second fractional-order discrete memristor circuit, a third fractional-order discrete memristor circuit and a fractional-order Logistic mapping circuit. Based on the advantage of the global memory characteristic of the fractional order, the present invention uses three fractional-order discrete memristors of different orders, that is, the order is The first fractional-order discrete memristor circuit of The second fractional-order discrete memristor circuit of The third fractional-order discrete memristor circuit is combined with the fractional-order Logistic mapping circuit to construct a multiple fractional-order discrete memristor coupled Logistic mapping circuit of different orders. The fractional-order discrete memristors of different orders enable the circuit to capture more details and complexity in the dynamic behavior of the system, which is more practical and can be better applied to engineering fields such as nonlinear circuits, neural networks, and secure communications.

[0085] The first fractional-order discrete memristor circuit comprises a first multiplier M1, an input end of the first multiplier M1 is connected to an output end of a second sample-and-hold SAMP2 of the first fractional-order differential operator circuit, and an output end of the first multiplier M1 is connected to an input end of a second multiplier M2;

[0086] The negative electrode of the DC power supply V1 is grounded, and the positive electrode of the DC power supply V1 is connected to the in-phase input terminal of the first voltage follower U1, so as to realize the expression of the memristor parameter value a; the inverting input terminal of the first voltage follower U1 is connected to the output terminal of the first voltage follower U1, and the output terminal of the first voltage follower U1 is connected to the input terminal of the second multiplier M2, so as to isolate the power device and the logic device;

[0087] The input end of the second multiplier M2 is connected to the output end of the first multiplier M1 and the output end of the first voltage follower U1 respectively, and the output end of the second multiplier M2 is connected to the inverting input end of the first inverting adder U3 via the first resistor R1; the non-inverting input end of the first inverting adder U3 is grounded;

[0088] The negative electrode of the DC power supply V2 is grounded, and the positive electrode of the DC power supply V2 is connected to the in-phase input terminal of the second voltage follower U2, so as to realize the expression of the memristor parameter value b; the inverting input terminal of the second voltage follower U2 is connected to the output terminal of the second voltage follower U2, and the output terminal of the second voltage follower U2 is connected to the input terminal of the third multiplier M3, so as to isolate the power device and the logic device;

[0089] The input end of the third multiplier M3 is respectively connected to the output end of the second sample holder of the first fractional-order differential operator circuit and the output end of the second voltage follower U2, and the output end of the third multiplier M3 is connected to the inverting input end of the first inverting adder U3 via the second resistor R2;

[0090] The negative electrode of the DC power supply V3 is grounded, and the positive electrode of the DC power supply V3 is connected to the inverting input terminal of the first inverting adder U3 via the third resistor R3;

[0091] The two ends of the fourth resistor R4 are respectively connected to the inverting input end and the output end of the first inverting adder U3 to implement the addition operation of the first fractional-order discrete memristor expression; the output end of the first inverting adder U3 is connected to the inverting input end of the first inverter U4 via the fifth resistor R5;

[0092] The non-inverting input terminal of the first inverter U4 is grounded, a sixth resistor R6 is connected between the inverting input terminal and the output terminal of the first inverter U4, and the output terminal of the first inverter U4 is connected to the input terminal of the fourth multiplier M4 to restore the input memristor signal to a positive value for output;

[0093] The negative electrode of the DC power supply V4 is grounded, and the positive electrode of the DC power supply V4 is connected to the in-phase input terminal of the third voltage follower U5, which is used to realize the coupling parameter value The inverting input terminal of the third voltage follower U5 is connected to the output terminal of the third voltage follower U5, and the output terminal of the third voltage follower U5 is connected to the input terminal of the fourth multiplier M4, which is used to isolate the power device and the logic device;

[0094] The input end of the fourth multiplier M4 is connected to the output end of the first inverter U4 and the output end of the third voltage follower U5 respectively, and the output end of the first inverter U4 serves as the output end of the first fractional-order discrete memristor circuit to output a memristor signal .

[0095] The second fractional-order discrete memristor circuit includes a fifth multiplier M5, an input end of the fifth multiplier M5 is connected to the output end of the eighth sample holder SAMP8 of the second fractional-order differential operator circuit, an output end of the fifth multiplier M5 is connected to the inverting input end of the second inverting adder U6 via a seventh resistor R7, and a non-inverting input end of the second inverting adder U6 is grounded;

[0096] The negative electrode of the DC power supply V5 is grounded, the positive electrode of the DC power supply V5 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the inverting input end of the second inverting adder U6;

[0097] The two ends of the ninth resistor R9 are respectively connected to the inverting input end and the output end of the second inverting adder U6 to implement the addition operation of the second fractional-order discrete memristor expression; the output end of the second inverting adder U6 is connected to the inverting input end of the second inverter U7 via the tenth resistor R10;

[0098] The non-inverting input terminal of the second inverter U7 is grounded, an eleventh resistor R11 is connected between the inverting input terminal and the output terminal of the second inverter U7, and the output terminal of the second inverter U7 is connected to the input terminal of the sixth multiplier M6 to restore the input memristor signal to a positive value for output;

[0099] The negative electrode of the DC power supply V6 is grounded, and the positive electrode of the DC power supply V6 is connected to the in-phase input terminal of the fourth voltage follower U8, so as to realize the coupling parameter value. The inverting input terminal of the fourth voltage follower U8 is connected to the output terminal of the fourth voltage follower U8, and the output terminal of the fourth voltage follower U8 is connected to the input terminal of the sixth multiplier M6, which is used to isolate the power device and the logic device;

[0100] The input end of the sixth multiplier M6 is connected to the output end of the second inverter U7 and the output end of the fourth voltage follower U8 respectively, and the output end of the second inverter U7 serves as the output end of the second fractional-order discrete memristor circuit to output a memristor signal .

[0101] The third fractional-order discrete memristor circuit includes a seventh multiplier M7, an input end of the seventh multiplier M7 is connected to the output end of the fourteenth sample holder SAMP14 of the third fractional-order differential operator circuit, an output end of the seventh multiplier M7 is connected to the inverting input end of the third inverting adder U9 via a twelfth resistor R12, and a non-inverting input end of the third inverting adder U9 is grounded;

[0102] The negative electrode of the DC power supply V7 is grounded, the positive electrode of the DC power supply V7 is connected to one end of the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is connected to the inverting input end of the third inverting adder U9;

[0103] Two ends of the fourteenth resistor R14 are respectively connected to the inverting input end and the output end of the third inverting adder U9 to implement the addition operation of the third fractional-order discrete memristor expression; the output end of the third inverting adder U9 is connected to the inverting input end of the third inverter U10 via the fifteenth resistor R15;

[0104] The non-inverting input terminal of the third inverter U10 is grounded, a sixteenth resistor R16 is connected between the inverting input terminal and the output terminal of the third inverter U10, and the output terminal of the third inverter U10 is connected to the input terminal of the eighth multiplier M8 to restore the input memristor signal to a positive value for output;

[0105] The negative electrode of the DC power supply V8 is grounded, and the positive electrode of the DC power supply V8 is connected to the in-phase input terminal of the fifth voltage follower U11, which is used to realize the coupling parameter value The inverting input terminal of the fifth voltage follower U11 is connected to the output terminal of the fifth voltage follower U11, and the output terminal of the fifth voltage follower U11 is connected to the input terminal of the eighth multiplier M8, which is used to isolate the power device and the logic device;

[0106] The input end of the eighth multiplier M8 is connected to the output end of the third inverter U10 and the output end of the fifth voltage follower U11 respectively, and the output end of the third inverter U10 serves as the output end of the third fractional-order discrete memristor circuit to output a memristor signal .

[0107] The fractional-order Logistic mapping circuit includes a ninth multiplier M9, an input end of the ninth multiplier M9 is connected to the output end of the eighth multiplier M8 of the third fractional-order discrete memristor circuit and the output end of the twentieth sample holder SAMP20, and the output end of the ninth multiplier M9 is connected to the inverting input end of the fourth inverting adder U14 via the twentieth resistor R20; the non-inverting input end of the fourth inverting adder U14 is grounded;

[0108] The input end of the tenth multiplier M10 is respectively connected to the output end of the fourth multiplier M4 of the first fractional-order discrete memristor circuit and the output end of the twentieth sample holder SAMP20, and the output end of the tenth multiplier M10 is connected to the input end of the eleventh multiplier M11; the output end of the eleventh multiplier M11 is connected to the inverting input end of the fourth inverting adder U14 via the twenty-first resistor R21;

[0109] The positive electrode of the DC power supply V9 ​​is grounded, and the negative electrode of the DC power supply V9 ​​is connected to the inverting input terminal of the fifth inverting adder U12 via the eighteenth resistor R18; the non-inverting input terminal of the fifth inverting adder U12 is grounded;

[0110] One end of the seventeenth resistor R17 is connected to the output end of the twentieth sample holder SAMP20, and the other end of the seventeenth resistor R17 is connected to the inverting input end of the fifth inverting adder U12; two ends of the nineteenth resistor R19 are respectively connected to the inverting input end and the output end of the fifth inverting adder U12;

[0111] The input end of the twelfth multiplier M12 is respectively connected to the output end of the fifth inverting adder U12 and the output end of the twentieth sample holder SAMP20, and the output end of the twelfth multiplier M12 is connected to the input end of the thirteenth multiplier M13;

[0112] The negative electrode of the DC power supply V10 is grounded, and the positive electrode of the DC power supply V10 is connected to the in-phase input terminal of the sixth voltage follower U13, so as to realize the expression of the system parameter value c; the inverting input terminal of the sixth voltage follower U13 is connected to the output terminal of the sixth voltage follower U13, and the output terminal of the sixth voltage follower U13 is connected to the input terminal of the thirteenth multiplier M13, so as to isolate the power device and the logic device;

[0113] The input end of the thirteenth multiplier M13 is connected to the output end of the twelfth multiplier M12 and the output end of the sixth voltage follower U13 respectively, and the output end of the thirteenth multiplier M13 is connected to the inverting input end of the fourth inverting adder U14 via the twenty-second resistor R22;

[0114] The negative electrode of the DC power supply V11 is grounded, and the positive electrode of the DC power supply V11 is connected to the inverting input terminal of the fourth inverting adder U14 via the twenty-third resistor R23, so as to make the system oscillate;

[0115] Two ends of the twenty-fourth resistor R24 ​​are respectively connected to the inverting input terminal and the output terminal of the fourth inverting adder U14 to implement the addition operation of the fractional-order Logistic mapping circuit expression; the output terminal of the fourth inverting adder U14 is connected to the inverting input terminal of the fourth inverter U15 via the twenty-fifth resistor R25;

[0116] The non-inverting input terminal of the fourth inverter U15 is grounded, a twenty-sixth resistor R26 is connected between the inverting input terminal and the output terminal of the fourth inverter U15, the output terminal of the fourth inverter U15 is connected to the input terminal of the nineteenth sample holder, and the input chaotic signal is restored to a positive value output;

[0117] The input end of the nineteenth sample holder SAMP19 is connected to the output end of the fourth inverter U15, and the output end of the nineteenth sample holder SAMP19 is connected to the input end of the twentieth sample holder SAMP20. The two sample holders are cascaded. The control end of the nineteenth sample holder SAMP19 and the control end of the twentieth sample holder SAMP20 are respectively connected to the input end and the output end of the NOT gate A3, and the output of the fourth inverting adder U14 is connected to the input end of the NOT gate A3. Discretize and delay to get , and then respectively input into the first fractional-order differential operator circuit, the second fractional-order differential operator circuit, and the third fractional-order differential operator circuit for operation, and the output end of the 20th sample holder SAMP20 is used as the output end of the fractional-order Logistic mapping circuit to output the chaotic signal .

[0118] The first fractional-order differential operator circuit includes a pulse signal V01, one end of the pulse signal V01 is grounded, and the other end of the pulse signal V01 is connected to the input end of the NOT gate A1;

[0119] The input end of the NOT gate A1 is connected to the output end of the pulse signal V01, the control end of the first sample holder SAMP1, the control end of the third sample holder SAMP3 and the control end of the fifth sample holder SAMP5, and the output end of the NOT gate A1 is respectively connected to the control end of the second sample holder SAMP2, the control end of the fourth sample holder SAMP4 and the control end of the sixth sample holder SAMP6;

[0120] The input end of the first sample and hold SAMP1 is connected to the output end of the inverter UA8, and the input iterative accumulated charge The output end of the first sample holder SAMP1 is connected to the input end of the second sample holder SAMP2. The two sample holders are cascaded and respectively controlled by a pulse signal V01 and two opposite logic signals obtained by the invertor A1, so that the sampling and holding states are exactly opposite, thereby achieving a time delay after the signal is discretized, wherein the delay time is the time occupied by the low level in one cycle, which can be controlled by adjusting the input frequency of the pulse signal; the output end of the sample holder SAMP2 outputs the internal charge of the first fractional-order discrete memristor as the output end of the first fractional-order differential operator circuit ;

[0121] The input end of the third sample holder SAMP3 is connected to the output end of the second sample holder SAMP2, and the output end of the third sample holder SAMP3 is connected to the input end of the fourth sample holder SAMP4. The two sample holders are also cascaded and are respectively controlled by the pulse signal V01 and the two opposite logic signals obtained by the NOT gate A1 to obtain the memristive charge ;

[0122] The input end of the fifth sample holder SAMP5 is connected to the output end of the fourth sample holder SAMP4, and the output end of the fifth sample holder SAMP5 is connected to the input end of the sixth sample holder SAMP6. The two sample holders are also cascaded and are respectively controlled by the pulse signal V01 and the two opposite logic signals obtained by the NOT gate A1 to obtain the memristive charge ;

[0123] The negative electrode of the DC power supply VA1 is grounded, and the positive electrode of the DC power supply VA1 is connected to the in-phase input terminal of the voltage follower UA1, and connected to the input terminal of the multiplier MA1 through the voltage follower UA1, so as to realize the first fractional-order discrete memristor order. the expression of;

[0124] The input end of the multiplier MA1 is connected to the output end of the voltage follower UA1 and the output end of the second sample and hold SAMP2 respectively, and the output end of the multiplier MA1 is connected to the inverting input end of the inverting adder UA7 via the resistor RA7; the non-inverting input end of the inverting adder UA7 is grounded;

[0125] The positive electrode of the DC power supply VA3 is grounded, and the negative electrode of the DC power supply VA3 is connected to the inverting input terminal of the inverting adder UA3 via the resistor RA5; the non-inverting input terminal of the inverting adder UA3 is grounded; one end of the resistor RA4 is connected to the positive electrode of the DC power supply VA1, and the other end of the resistor RA4 is connected to the inverting input terminal of the inverting adder UA3; the two ends of the resistor RA6 are respectively connected to the inverting input terminal and the output terminal of the inverting adder UA3;

[0126] The negative electrode of the DC power supply VA4 is grounded, the positive electrode of the DC power supply VA4 is connected to the in-phase input terminal of the voltage follower UA4, and connected to the input terminal of the multiplier MA4 via the voltage follower UA4; the input terminal of the multiplier MA4 is respectively connected to the output terminal of the voltage follower UA4 and the output terminal of the inverting adder UA3, and the output terminal of the multiplier MA4 is connected to the input terminal of the multiplier MA3;

[0127] The positive electrode of the DC power supply VA2 is grounded, and the negative electrode of the DC power supply VA2 is connected to the inverting input terminal of the inverting adder UA2 via the resistor RA2; the non-inverting input terminal of the inverting adder UA2 is grounded; one end of the resistor RA1 is connected to the positive electrode of the DC power supply VA1, and the other end of the resistor RA1 is connected to the inverting input terminal of the inverting adder UA2; the two ends of the resistor RA3 are respectively connected to the inverting input terminal and the output terminal of the inverting adder UA2; the input terminal of the multiplier MA3 is respectively connected to the output terminal of the multiplier MA4 and the output terminal of the inverting adder UA2, so as to realize the charge coefficient of the first fractional-order discrete memristor the expression of;

[0128] The input end of the multiplier MA2 is connected to the output end of the multiplier MA3 and the output end of the sixth sample holder SAMP6 respectively, and the output end of the multiplier MA2 is connected to the inverting input end of the inverting adder UA7 via the resistor RA8;

[0129] The negative electrode of the DC power supply VA5 is grounded, and the positive electrode of the DC power supply VA5 is connected to the in-phase input terminal of the voltage follower UA5, and connected to the input terminal of the multiplier MA6 through the voltage follower UA5; the input terminal of the multiplier MA6 is respectively connected to the output terminal of the voltage follower UA5 and the output terminal of the multiplier MA4, so as to realize the charge coefficient of the first fractional-order discrete memristor. the expression of;

[0130] The input end of the multiplier MA5 is connected to the output end of the multiplier MA6 and the output end of the fourth sample holder SAMP4 respectively, and the output end of the multiplier MA5 is connected to the inverting input end of the inverting adder UA7 via the resistor RA9;

[0131] The negative electrode of the DC power supply VA6 is grounded, and the positive electrode of the DC power supply VA6 is connected to the in-phase input terminal of the voltage follower UA6, and connected to the input terminal of the multiplier MA7 via the voltage follower UA6, so as to realize the expression of the system parameter value d;

[0132] The input end of the multiplier MA7 is respectively connected to the output end of the voltage follower UA6 and the output end of the twentieth sample holder SAMP20, and the output end of the multiplier MA7 is connected to the inverting input end of the inverting adder UA7 via the resistor RA10; the two ends of the resistor RA11 are respectively connected to the inverting input end and the output end of the inverting adder UA7;

[0133] One end of the resistor RA12 is connected to the output end of the inverting adder UA7, and the other end of the resistor RA12 is connected to the inverting input end of the inverter UA8. The non-inverting input end of the inverter UA8 is grounded; the two ends of the resistor RA13 are respectively connected to the inverting input end and the output end of the inverter UA8, and the output end of the inverter UA8 outputs the iterative accumulated value of the charge. .

[0134] The second fractional-order differential operator circuit includes a pulse signal V02, one end of the pulse signal V02 is grounded, and the other end of the pulse signal V02 is connected to the input end of the NOT gate A2;

[0135] The input end of the NOT gate A2 is connected to the output end of the pulse signal V02, the control end of the seventh sample holder SAMP7, the control end of the ninth sample holder SAMP9 and the control end of the eleventh sample holder SAMP11, and the output end of the NOT gate A2 is respectively connected to the control end of the eighth sample holder SAMP8, the control end of the tenth sample holder SAMP10 and the control end of the twelfth sample holder SAMP12;

[0136] The input end of the seventh sample-and-hold device SAMP7 is connected to the output end of the inverter UB8, and the accumulated charge is input. The output end of the seventh sample holder SAMP7 is connected to the input end of the eighth sample holder SAMP8. The two sample holders are cascaded and respectively controlled by the pulse signal V02 and the two opposite logic signals obtained by the NOT gate A2, so that the sampling and holding states are exactly opposite, thereby realizing the discretization of the continuous signal and then delaying it in time; the output end of the sample holder SAMP8 is used as the output end of the second fractional-order differential operator circuit to output the internal charge of the second fractional-order discrete memristor ;

[0137] The input end of the ninth sample holder SAMP9 is connected to the output end of the eighth sample holder SAMP8, and the output end of the ninth sample holder SAMP9 is connected to the input end of the tenth sample holder SAMP10. The two sample holders are also cascaded and are respectively controlled by the pulse signal V02 and the two opposite logic signals obtained by the NOT gate A2 to obtain the memristive charge. ;

[0138] The input end of the eleventh sample holder SAMP11 is connected to the output end of the tenth sample holder SAMP10, and the output end of the eleventh sample holder SAMP11 is connected to the input end of the twelfth sample holder SAMP12. The two sample holders are also cascaded and are respectively controlled by the pulse signal V02 and the two opposite logic signals obtained by the NOT gate A2 to obtain the memristive charge ;

[0139] The negative electrode of the DC power supply VB1 is grounded, and the positive electrode of the DC power supply VB1 is connected to the in-phase input terminal of the voltage follower UB1, and connected to the input terminal of the multiplier MB1 through the voltage follower UB1, so as to realize the second fractional-order discrete memristor order. the expression of;

[0140] The input end of the multiplier MB1 is connected to the output end of the voltage follower UB1 and the output end of the eighth sample and hold SAMP8 respectively, and the output end of the multiplier MB1 is connected to the inverting input end of the inverting adder UB7 via the resistor RB7; the non-inverting input end of the inverting adder UB7 is grounded;

[0141] The positive electrode of the DC power supply VB3 is grounded, and the negative electrode of the DC power supply VB3 is connected to the inverting input terminal of the inverting adder UB3 via the resistor RB5; the non-inverting input terminal of the inverting adder UB3 is grounded; one end of the resistor RB4 is connected to the positive electrode of the DC power supply VB1, and the other end of the resistor RB4 is connected to the inverting input terminal of the inverting adder UB3; the two ends of the resistor RB6 are respectively connected to the inverting input terminal and the output terminal of the inverting adder UB3;

[0142] The negative electrode of the DC power supply VB4 is grounded, and the positive electrode of the DC power supply VB4 is connected to the in-phase input terminal of the voltage follower UB4, and connected to the input terminal of the multiplier MB4 via the voltage follower UB4; the input terminal of the multiplier MB4 is respectively connected to the output terminal of the voltage follower UB4 and the output terminal of the inverting adder UB3, and the output terminal of the multiplier MB4 is connected to the input terminal of the multiplier MB3;

[0143] The positive electrode of the DC power supply VB2 is grounded, and the negative electrode of the DC power supply VB2 is connected to the inverting input terminal of the inverting adder UB2 via the resistor RB2; the non-inverting input terminal of the inverting adder UB2 is grounded; one end of the resistor RB1 is connected to the positive electrode of the DC power supply VB1, and the other end of the resistor RB1 is connected to the inverting input terminal of the inverting adder UB2; the two ends of the resistor RB3 are respectively connected to the inverting input terminal and the output terminal of the inverting adder UB2; the input terminal of the multiplier MB3 is respectively connected to the output terminal of the multiplier MB4 and the output terminal of the inverting adder UB2, so as to realize the charge coefficient of the second fractional-order discrete memristor. the expression of;

[0144] The input end of the multiplier MB2 is connected to the output end of the multiplier MB3 and the output end of the twelfth sample holder SAMP12 respectively, and the output end of the multiplier MB2 is connected to the inverting input end of the inverting adder UB7 via the resistor RB8;

[0145] The negative electrode of the DC power supply VB5 is grounded, and the positive electrode of the DC power supply VB5 is connected to the in-phase input terminal of the voltage follower UB5, and connected to the input terminal of the multiplier MB6 via the voltage follower UB5; the input terminal of the multiplier MB6 is respectively connected to the output terminal of the voltage follower UB5 and the output terminal of the multiplier MB4, so as to realize the charge coefficient of the second fractional-order discrete memristor. the expression of;

[0146] The input end of the multiplier MB5 is connected to the output end of the multiplier MB6 and the output end of the tenth sample holder SAMP10 respectively, and the output end of the multiplier MB5 is connected to the inverting input end of the inverting adder UB7 via the resistor RB9;

[0147] The negative electrode of the DC power supply VB6 is grounded, and the positive electrode of the DC power supply VB6 is connected to the in-phase input terminal of the voltage follower UB6, and connected to the input terminal of the multiplier MB7 via the voltage follower UB6, so as to realize the expression of the system parameter value d;

[0148] The input end of the multiplier MB7 is connected to the output end of the voltage follower UB6 and the output end of the tenth multiplier M10 respectively, and the output end of the multiplier MB7 is connected to the inverting input end of the inverting adder UB7 via the resistor RB10; the two ends of the resistor RB11 are connected to the inverting input end and the output end of the inverting adder UB7 respectively;

[0149] One end of the resistor RB12 is connected to the output end of the inverting adder UB7, and the other end of the resistor RB12 is connected to the inverting input end of the inverter UB8. The non-inverting input end of the inverter UB8 is grounded; the two ends of the resistor RB13 are respectively connected to the inverting input end and the output end of the inverter UB8, and the output end of the inverter UB8 outputs the iterative accumulated value of the charge. .

[0150] The third fractional-order differential operator circuit includes a pulse signal V03, one end of the pulse signal V03 is grounded, and the other end of the pulse signal V03 is connected to the input end of the NOT gate A3;

[0151] The input end of the NOT gate A3 is connected to the output end of the pulse signal V03, the control end of the thirteenth sample holder SAMP13, the control end of the fifteenth sample holder SAMP15 and the control end of the seventeenth sample holder SAMP17, and the output end of the NOT gate A3 is respectively connected to the control end of the fourteenth sample holder SAMP14, the control end of the sixteenth sample holder SAMP16 and the control end of the eighteenth sample holder SAMP18;

[0152] The input end of the thirteenth sample and hold SAMP13 is connected to the output end of the inverter UC8, and the input iterative accumulated charge The output end of the thirteenth sample holder SAMP13 is connected to the input end of the fourteenth sample holder SAMP14. The two sample holders are cascaded and respectively controlled by the pulse signal V03 and the two opposite logic signals obtained by the NOT gate A3, so that the sampling and holding states are exactly opposite, thereby realizing the discretization of the continuous signal and then delaying it in time; the output end of the sample holder SAMP14 is used as the output end of the third fractional-order differential operator circuit to output the internal charge of the third fractional-order discrete memristor ;

[0153] The input end of the fifteenth sample holder SAMP15 is connected to the output end of the fourteenth sample holder SAMP14, and the output end of the fifteenth sample holder SAMP15 is connected to the input end of the sixteenth sample holder SAMP16. The two sample holders are also cascaded and are respectively controlled by the pulse signal V03 and the two opposite logic signals obtained by the NOT gate A3 to obtain the internal charge of the memristor. ;

[0154] The input end of the seventeenth sample holder SAMP17 is connected to the output end of the sixteenth sample holder SAMP16, and the output end of the seventeenth sample holder SAMP17 is connected to the input end of the eighteenth sample holder SAMP18. The two sample holders are also cascaded and are respectively controlled by the pulse signal V03 and the two opposite logic signals obtained by the NOT gate A3 to obtain the internal charge of the memristor. ;

[0155] The negative electrode of the DC power supply VC1 is grounded, and the positive electrode of the DC power supply VC1 is connected to the in-phase input terminal of the voltage follower UC1, and is connected to the input terminal of the multiplier MC1 through the voltage follower UC1, so as to realize the third fractional-order discrete memristor order. the expression of;

[0156] The input end of the multiplier MC1 is connected to the output end of the voltage follower UC1 and the output end of the fourteenth sample and hold SAMP14 respectively, and the output end of the multiplier MC1 is connected to the inverting input end of the inverting adder UC7 via the resistor RC7; the non-inverting input end of the inverting adder UC7 is grounded;

[0157] The positive electrode of the DC power supply VC3 is grounded, and the negative electrode of the DC power supply VC3 is connected to the inverting input terminal of the inverting adder UC3 via the resistor RC5; the non-inverting input terminal of the inverting adder UC3 is grounded; one end of the resistor RC4 is connected to the positive electrode of the DC power supply VC1, and the other end of the resistor RC4 is connected to the inverting input terminal of the inverting adder UC3; the two ends of the resistor RC6 are respectively connected to the inverting input terminal and the output terminal of the inverting adder UC3;

[0158] The negative electrode of the DC power supply VC4 is grounded, and the positive electrode of the DC power supply VC4 is connected to the in-phase input terminal of the voltage follower UC4, and connected to the input terminal of the multiplier MC4 via the voltage follower UC4; the input terminal of the multiplier MC4 is respectively connected to the output terminal of the voltage follower UC4 and the output terminal of the inverting adder UC3, and the output terminal of the multiplier MC4 is connected to the input terminal of the multiplier MC3;

[0159] The positive electrode of the DC power supply VC2 is grounded, and the negative electrode of the DC power supply VC2 is connected to the inverting input terminal of the inverting adder UC2 via the resistor RC2; the non-inverting input terminal of the inverting adder UC2 is grounded; one end of the resistor RC1 is connected to the positive electrode of the DC power supply VC1, and the other end of the resistor RC1 is connected to the inverting input terminal of the inverting adder UC2; the two ends of the resistor RC3 are respectively connected to the inverting input terminal and the output terminal of the inverting adder UC2; the input terminal of the multiplier MC3 is respectively connected to the output terminal of the multiplier MC4 and the output terminal of the inverting adder UC2, so as to realize the charge coefficient of the third fractional-order discrete memristor. the expression of;

[0160] The input end of the multiplier MC2 is connected to the output end of the multiplier MC3 and the output end of the eighteenth sample holder SAMP18 respectively, and the output end of the multiplier MC2 is connected to the inverting input end of the inverting adder UC7 via the resistor RC8;

[0161] The negative electrode of the DC power supply VC5 is grounded, and the positive electrode of the DC power supply VC5 is connected to the in-phase input terminal of the voltage follower UC5, and connected to the input terminal of the multiplier MC6 through the voltage follower UC5; the input terminal of the multiplier MC6 is respectively connected to the output terminal of the voltage follower UC5 and the output terminal of the multiplier MC4, so as to realize the charge coefficient of the third fractional-order discrete memristor. the expression of;

[0162] The input end of the multiplier MC5 is connected to the output end of the multiplier MC6 and the output end of the sixteenth sample holder SAMP16 respectively, and the output end of the multiplier MC5 is connected to the inverting input end of the inverting adder UC7 via the resistor RC9;

[0163] The negative electrode of the DC power supply VC6 is grounded, and the positive electrode of the DC power supply VC6 is connected to the in-phase input terminal of the voltage follower UC6, and is connected to the input terminal of the multiplier MC7 via the voltage follower UC6, so as to realize the expression of the system parameter value d;

[0164] The input end of the multiplier MC7 is respectively connected to the output end of the voltage follower UC6 and the output end of the twentieth adopting keeper SAMP20, and the output end of the multiplier MC7 is connected to the inverting input end of the inverting adder UC7 via the resistor RC10; the two ends of the resistor RC11 are respectively connected to the inverting input end and the output end of the inverting adder UC7;

[0165] One end of the resistor RC12 is connected to the output end of the inverting adder UC7, and the other end of the resistor RC12 is connected to the inverting input end of the inverter UC8. The non-inverting input end of the inverter UC8 is grounded; the two ends of the resistor RC13 are respectively connected to the inverting input end and the output end of the inverter UC8, and the output end of the inverter UC8 outputs the iterative accumulated value of the charge. .

[0166] The relationship between the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 in the first fractional-order discrete memristor circuit is: R1=R2=R3=R4=R5=R6=10 ; The voltage value relationship between the first DC power supply V1, the second DC power supply V2, the third DC power supply V3 and the fourth DC power supply V4 is: V1 = 0.2V, V2 = 0.05V, V3 = 1V, V4 = 1.08V;

[0167] The relationship between the resistance values ​​of the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and the eleventh resistor R11 in the second fractional-order discrete memristor circuit is: R7=R8=R9=R10=R11=10 ; The voltage value relationship between the fifth DC power supply V5 and the sixth DC power supply V6 is: V5 = -1V, V6 = -3V;

[0168] The relationship between the resistance values ​​of the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15 and the sixteenth resistor R16 in the third fractional-order discrete memristor circuit is: R12=R13=R14=R15=R16=10 ; The voltage value relationship between the seventh DC power supply V7 and the eighth DC power supply V8 is: V7 = -1V, V8 = -1.1V;

[0169] The resistance value relationship of the seventeenth resistor R17, the eighteenth resistor R18, the nineteenth resistor R19, the twentieth resistor R20, the twenty-first resistor R21, the twenty-second resistor R22, the twenty-third resistor R23, the twenty-fourth resistor R24, the twenty-fifth resistor R25 and the twenty-sixth resistor R26 in the fractional-order logistic mapping circuit is: R17=R18=R19=R20=R21=R22=R23=R24=R25=R26=10 The relationship between the voltage values ​​of the ninth DC power supply V9, the tenth DC power supply V10 and the eleventh DC power supply V11 is: V9=1V, V10=0.1V, V11=0.0001V.

[0170] The relationship between the resistance values ​​in the first fractional-order differential operator circuit is: resistance RA1 = resistance RA2 = resistance RA3 = resistance RA4 = resistance RA5 = resistance RA6 = resistance RA7 = resistance RA8 = resistance RA9 = resistance RA10 = resistance RA11 = resistance RA12 = resistance RA13 = 10 ; The voltage value relationship is VA1=0.96V, VA2=2V, VA3=1V, VA4=0.16V, VA5=3V, VA6=1V;

[0171] The relationship between the resistance values ​​in the second fractional-order differential operator circuit is: resistance RB1 = resistance RB2 = resistance RB3 = resistance RB4 = resistance RB5 = resistance RB6 = resistance RB7 = resistance RB8 = resistance RB9 = resistance RB10 = resistance RB11 = resistance RB12 = resistance RB13 = 10 ; The voltage value relationship is VB1=0.87V, VB2=2V, VB3=1V, VB4=0.145V, VB5=3V, VB6=1V;

[0172] The relationship between the resistance values ​​in the third fractional-order differential operator circuit is: resistance RC1 = resistance RC2 = resistance RC3 = resistance RC4 = resistance RC5 = resistance RC6 = resistance RC7 = resistance RC8 = resistance RC9 = resistance RC10 = resistance RC11 = resistance RC12 = resistance RC13 = 10 ; The voltage value relationship is VC1=0.9V, VC2=2V, VC3=1V, VC4=0.15V, VC5=3V, VC6=1V.

[0173] The three discrete memristors of different orders involved in the multi-stability circuit of the fractional-order discrete memristors of different orders are fractional-order charge-controlled discrete memristor models, and the mathematical expression thereof is:

[0174]

[0175]

[0176]

[0177] in, ; represents the memristor output voltage, represents the memristor input current, represents the amount of charge, represents the memristor value, represents the parameters of the memristor model, represents the value of the DC power supply V1 in the first fractional-order discrete memristor circuit, represents the value of the DC power supply V2 in the first fractional-order discrete memristor circuit, is the coefficient of historical data, represents the Grunwald-Letnikov type fractional-order difference definition, represents the order of fractional differences of different selected values, Indicates the current iteration number, Indicates the memory length;

[0178] The multi-stability circuit of the fractional-order discrete memristor of different orders involves a mathematical model of a Logistic mapping system, and its mathematical expression is:

[0179]

[0180] in, ; is the system parameter;

[0181] The mathematical model of the multi-stability circuit of the fractional-order discrete memristor of different orders is expressed as follows:

[0182]

[0183] in, , , ,L=3, ; and are the three fractional-order discrete memristors with different values ​​between 0 and 1, represents the value of the DC power supply VA1 in the first fractional-order difference operator circuit, represents the value of the DC power supply VB1 in the second fractional-order differential operator circuit, represents the value of the DC power supply VC1 in the third fractional-order difference operator circuit; and is the coupling parameter of the memristor coupled chaotic mapping, the value of the DC power supply V4 in the first fractional-order discrete memristor circuit, and the parameter Indicates the value of the DC power supply V6 in the second fractional-order discrete memristor circuit, using the parameter Indicates the value of the DC power supply V8 in the third fractional-order discrete memristor circuit, using the parameter express; is the system parameter, represents the value of the DC power supply V10 in the fractional-order logistic mapping circuit, Represents the values ​​of DC power supplies VA6, VB6, and VC6 in the first fractional-order discrete memristor circuit, the second fractional-order discrete memristor circuit, and the third fractional-order discrete memristor circuit.

[0184] Use constant m as the control quantity and add it to the system variable The system offset can be further controlled to achieve flexible multi-stability such as attractor self-regeneration or attractor multiplication.

[0185] After adding the control quantity m, the mathematical model of the improved fractional-order discrete memristor mapping system of different orders can be obtained, and its mathematical expression is:

[0186]

[0187] Among them, m is a constant, serving as the control variable for the system's offset enhancement behavior.

[0188] like Figure 3-6 As shown, it is an experimental verification of a multi-stability circuit based on fractional-order discrete memristors of different orders, which verifies and illustrates the technical effect of the embodiment of the present invention.

[0189] Introduce three different orders of fractional-order charge-controlled discrete memristors in the Logistic mapping circuit, and design multi-stability circuits of fractional-order discrete memristors of different orders. According to the coupling principle, the mathematical model of multi-stability system involving fractional-order discrete memristor circuits of different orders is obtained, and numerical simulation is carried out in Matlab. By analyzing the bifurcation diagram and Lyapunov index spectrum of the system, the parameters that make the system in a chaotic state are determined. c,d, The value of .

[0190] The multi-stability circuits of fractional-order discrete memristors of different orders are simulated and verified in PSIM, and the system trajectory diagram is output. The results are compared with the Matlab numerical simulation results to verify the correctness of the designed multi-stability circuits of fractional-order discrete memristors of different orders.

[0191] Figure 3 Schematic diagram of the chaotic attractor plane of the fractional-order Logistic mapping circuit and the first fractional-order discrete memristor circuit. Figure 4 Schematic diagram of the coexistence attractor plane for initial value regulation. Figure 5 Schematic diagram of the symmetric attractor plane for bidirectional regulation of amplitude induced by the system parameter d. Figure 6 The figure is a schematic diagram of the offset enhanced attractor plane induced by the offset control amount m. Based on the advantages of the fractional-order global memory characteristics, the different-order fractional-order discrete memristor circuit adopts the discrete memristor defined by Grunwald-Letnikov fractional-order difference and selects different numerical orders to construct a fractional-order discrete memristor coupled Logistic mapping circuit of different orders. Through the chaotic attractor generated by this circuit, the different-order fractional-order discrete memristor circuit has complex and rich dynamic behaviors such as initial value control, symmetric attractor, amplitude bidirectional control and offset enhancement. Compared with the general integer-order discrete memristor circuit, it has more complex chaotic characteristics such as multi-stability.

[0192] The embodiments described above are only descriptions of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. A multi-stability circuit based on fractional-order discrete memristors of different orders, characterized in that: include: A first fractional-order discrete memristor circuit, a second fractional-order discrete memristor circuit, a third fractional-order discrete memristor circuit and a fractional-order logistic mapping circuit; The first fractional-order discrete memristor circuit is connected to the second fractional-order discrete memristor circuit, the third fractional-order discrete memristor circuit, the fractional-order Logistic mapping circuit and the first fractional-order differential operator circuit, the second fractional-order discrete memristor circuit is connected to the third fractional-order discrete memristor circuit, the fractional-order Logistic mapping circuit and the second fractional-order differential operator circuit, and the third fractional-order discrete memristor circuit is connected to the fractional-order Logistic mapping circuit and the third fractional-order differential operator circuit; the order of the first fractional-order discrete memristor circuit is , the order of the second fractional-order discrete memristor circuit is , the order of the third fractional-order discrete memristor circuit is ; The first fractional-order discrete memristor circuit is used to generate charge , the second fractional-order discrete memristor circuit is used to generate the charge , the third fractional-order discrete memristor circuit is used to generate the charge , fractional-order logistic mapping circuit is used to generate chaotic sequence ;in, The expressions of the first fractional-order discrete memristor circuit, the second fractional-order discrete memristor circuit, and the third fractional-order discrete memristor circuit are: in, , represents the memristor output voltage, represents the memristor input current, represents the amount of charge, represents the memristor value, represents the parameters of the memristor model, represents the value of the DC power supply V1 in the first fractional-order discrete memristor circuit, represents the value of the DC power supply V2 in the first fractional-order discrete memristor circuit, is the coefficient of historical data, represents the Grunwald-Letnikov type fractional-order difference definition, represents the order of fractional differences of different selected values, Indicates the current iteration number, Indicates the memory length; The circuit expression of fractional-order logistic mapping is: in, ; is the system parameter; The multi-stability circuit expressions of fractional-order discrete memristors of different orders are: in, , , ,L=3, ; and are the three fractional-order discrete memristors with different values ​​between 0 and 1, represents the value of the DC power supply VA1 in the first fractional-order difference operator circuit, represents the value of the DC power supply VB1 in the second fractional-order differential operator circuit, represents the value of the DC power supply VC1 in the third fractional-order difference operator circuit; and is the coupling parameter of the memristor coupled chaotic mapping, the value of the DC power supply V4 in the first fractional-order discrete memristor circuit, and the parameter Indicates the value of the DC power supply V6 in the second fractional-order discrete memristor circuit, using the parameter Indicates the value of the DC power supply V8 in the third fractional-order discrete memristor circuit, using the parameter express; is the system parameter, represents the value of the DC power supply V10 in the fractional-order logistic mapping circuit, Represents the values ​​of DC power supplies VA6, VB6, and VC6 in the first fractional-order discrete memristor circuit, the second fractional-order discrete memristor circuit, and the third fractional-order discrete memristor circuit.

2. The multi-stability circuit based on fractional-order discrete memristors of different orders as claimed in claim 1, characterized in that: The first fractional-order discrete memristor circuit comprises a first multiplier M1, an input end of the first multiplier M1 is connected to an output end of a second sample-and-hold SAMP2 of the first fractional-order differential operator circuit, and an output end of the first multiplier M1 is connected to an input end of a second multiplier M2; The negative electrode of the DC power supply V1 is grounded, and the positive electrode of the DC power supply V1 is connected to the non-inverting input terminal of the first voltage follower U1; the inverting input terminal of the first voltage follower U1 is connected to the output terminal of the first voltage follower U1, and the output terminal of the first voltage follower U1 is connected to the input terminal of the second multiplier M2; The input end of the second multiplier M2 is connected to the output end of the first multiplier M1 and the output end of the first voltage follower U1 respectively, and the output end of the second multiplier M2 is connected to the inverting input end of the first inverting adder U3 via the first resistor R1; the non-inverting input end of the first inverting adder U3 is grounded; The negative electrode of the DC power supply V2 is grounded, and the positive electrode of the DC power supply V2 is connected to the non-inverting input terminal of the second voltage follower U2; the inverting input terminal of the second voltage follower U2 is connected to the output terminal of the second voltage follower U2, and the output terminal of the second voltage follower U2 is connected to the input terminal of the third multiplier M3; The input end of the third multiplier M3 is respectively connected to the output end of the second sample holder of the first fractional-order differential operator circuit and the output end of the second voltage follower U2, and the output end of the third multiplier M3 is connected to the inverting input end of the first inverting adder U3 via the second resistor R2; The negative electrode of the DC power supply V3 is grounded, and the positive electrode of the DC power supply V3 is connected to the inverting input terminal of the first inverting adder U3 via the third resistor R3; Two ends of the fourth resistor R4 are respectively connected to the inverting input end and the output end of the first inverting adder U3; the output end of the first inverting adder U3 is connected to the inverting input end of the first inverter U4 via the fifth resistor R5; The non-inverting input terminal of the first inverter U4 is grounded, a sixth resistor R6 is connected between the inverting input terminal and the output terminal of the first inverter U4, and the output terminal of the first inverter U4 is connected to the input terminal of the fourth multiplier M4; The negative electrode of the DC power supply V4 is grounded, and the positive electrode of the DC power supply V4 is connected to the non-inverting input terminal of the third voltage follower U5; the inverting input terminal of the third voltage follower U5 is connected to the output terminal of the third voltage follower U5, and the output terminal of the third voltage follower U5 is connected to the input terminal of the fourth multiplier M4; The input end of the fourth multiplier M4 is connected to the output end of the first inverter U4 and the output end of the third voltage follower U5 respectively, and the output end of the first inverter U4 serves as the output end of the first fractional-order discrete memristor circuit to output a memristor signal .

3. The multi-stability circuit based on fractional-order discrete memristors of different orders as claimed in claim 2, characterized in that: The second fractional-order discrete memristor circuit includes a fifth multiplier M5, an input end of the fifth multiplier M5 is connected to the output end of the eighth sample holder SAMP8 of the second fractional-order differential operator circuit, an output end of the fifth multiplier M5 is connected to the inverting input end of the second inverting adder U6 via a seventh resistor R7, and a non-inverting input end of the second inverting adder U6 is grounded; The negative electrode of the DC power supply V5 is grounded, the positive electrode of the DC power supply V5 is connected to one end of the eighth resistor R8, and the other end of the eighth resistor R8 is connected to the inverting input end of the second inverting adder U6; Two ends of the ninth resistor R9 are respectively connected to the inverting input terminal and the output terminal of the second inverting adder U6; The output end of the second inverting adder U6 is connected to the inverting input end of the second inverter U7 via the tenth resistor R10; The non-inverting input terminal of the second inverter U7 is grounded, an eleventh resistor R11 is connected between the inverting input terminal and the output terminal of the second inverter U7, and the output terminal of the second inverter U7 is connected to the input terminal of the sixth multiplier M6; The negative electrode of the DC power supply V6 is grounded, and the positive electrode of the DC power supply V6 is connected to the non-inverting input terminal of the fourth voltage follower U8; the inverting input terminal of the fourth voltage follower U8 is connected to the output terminal of the fourth voltage follower U8, and the output terminal of the fourth voltage follower U8 is connected to the input terminal of the sixth multiplier M6; The input end of the sixth multiplier M6 is connected to the output end of the second inverter U7 and the output end of the fourth voltage follower U8 respectively, and the output end of the second inverter U7 serves as the output end of the second fractional-order discrete memristor circuit to output a memristor signal .

4. The multi-stability circuit based on fractional-order discrete memristors of different orders as claimed in claim 3, characterized in that: The third fractional-order discrete memristor circuit includes a seventh multiplier M7, an input end of the seventh multiplier M7 is connected to the output end of the fourteenth sample holder SAMP14 of the third fractional-order differential operator circuit, an output end of the seventh multiplier M7 is connected to the inverting input end of the third inverting adder U9 via a twelfth resistor R12, and a non-inverting input end of the third inverting adder U9 is grounded; The negative electrode of the DC power supply V7 is grounded, the positive electrode of the DC power supply V7 is connected to one end of the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is connected to the inverting input end of the third inverting adder U9; Two ends of the fourteenth resistor R14 are respectively connected to the inverting input terminal and the output terminal of the third inverting adder U9; the output terminal of the third inverting adder U9 is connected to the inverting input terminal of the third inverter U10 via the fifteenth resistor R15; The non-inverting input terminal of the third inverter U10 is grounded, a sixteenth resistor R16 is connected between the inverting input terminal and the output terminal of the third inverter U10, and the output terminal of the third inverter U10 is connected to the input terminal of the eighth multiplier M8; The negative electrode of the DC power supply V8 is grounded, and the positive electrode of the DC power supply V8 is connected to the non-inverting input terminal of the fifth voltage follower U11; the inverting input terminal of the fifth voltage follower U11 is connected to the output terminal of the fifth voltage follower U11, and the output terminal of the fifth voltage follower U11 is connected to the input terminal of the eighth multiplier M8; The input end of the eighth multiplier M8 is connected to the output end of the third inverter U10 and the output end of the fifth voltage follower U11 respectively, and the output end of the third inverter U10 serves as the output end of the third fractional-order discrete memristor circuit to output a memristor signal .

5. The multi-stability circuit based on fractional-order discrete memristors of different orders as claimed in claim 4, characterized in that: The fractional-order Logistic mapping circuit includes a ninth multiplier M9, an input end of the ninth multiplier M9 is connected to the output end of the eighth multiplier M8 of the third fractional-order discrete memristor circuit and the output end of the twentieth sample holder SAMP20, and the output end of the ninth multiplier M9 is connected to the inverting input end of the fourth inverting adder U14 via the twentieth resistor R20; A non-inverting input terminal of the fourth inverting adder U14 is grounded; The input end of the tenth multiplier M10 is respectively connected to the output end of the fourth multiplier M4 of the first fractional-order discrete memristor circuit and the output end of the twentieth sample holder SAMP20, and the output end of the tenth multiplier M10 is connected to the input end of the eleventh multiplier M11; the output end of the eleventh multiplier M11 is connected to the inverting input end of the fourth inverting adder U14 via the twenty-first resistor R21; The positive electrode of the DC power supply V9 ​​is grounded, and the negative electrode of the DC power supply V9 ​​is connected to the inverting input terminal of the fifth inverting adder U12 via the eighteenth resistor R18; the non-inverting input terminal of the fifth inverting adder U12 is grounded; One end of the seventeenth resistor R17 is connected to the output end of the twentieth sample holder SAMP20, and the other end of the seventeenth resistor R17 is connected to the inverting input end of the fifth inverting adder U12; two ends of the nineteenth resistor R19 are respectively connected to the inverting input end and the output end of the fifth inverting adder U12; The input end of the twelfth multiplier M12 is respectively connected to the output end of the fifth inverting adder U12 and the output end of the twentieth sample holder SAMP20, and the output end of the twelfth multiplier M12 is connected to the input end of the thirteenth multiplier M13; The negative electrode of the DC power supply V10 is grounded, and the positive electrode of the DC power supply V10 is connected to the non-inverting input terminal of the sixth voltage follower U13; the inverting input terminal of the sixth voltage follower U13 is connected to the output terminal of the sixth voltage follower U13, and the output terminal of the sixth voltage follower U13 is connected to the input terminal of the thirteenth multiplier M13; The input end of the thirteenth multiplier M13 is connected to the output end of the twelfth multiplier M12 and the output end of the sixth voltage follower U13 respectively, and the output end of the thirteenth multiplier M13 is connected to the inverting input end of the fourth inverting adder U14 via the twenty-second resistor R22; The negative electrode of the DC power source V11 is grounded, and the positive electrode of the DC power source V11 is connected to the inverting input terminal of the fourth inverting adder U14 via the twenty-third resistor R23; Two ends of the twenty-fourth resistor R24 ​​are respectively connected to the inverting input terminal and the output terminal of the fourth inverting adder U14; the output terminal of the fourth inverting adder U14 is connected to the inverting input terminal of the fourth inverter U15 via the twenty-fifth resistor R25; The non-inverting input terminal of the fourth inverter U15 is grounded, a twenty-sixth resistor R26 is connected between the inverting input terminal and the output terminal of the fourth inverter U15, and the output terminal of the fourth inverter U15 is connected to the input terminal of the nineteenth sample holder; The input end of the nineteenth sample holder SAMP19 is connected to the output end of the fourth inverter U15, and the output end of the nineteenth sample holder SAMP19 is connected to the input end of the twentieth sample holder SAMP20; the control end of the nineteenth sample holder SAMP19 and the control end of the twentieth sample holder SAMP20 are respectively connected to the input end and the output end of the NOT gate A3, and the output end of the twentieth sample holder SAMP20 serves as the output end of the fractional-order Logistic mapping circuit to output a chaotic signal .

6. The multi-stability circuit based on fractional-order discrete memristors of different orders as claimed in claim 5, characterized in that: The first fractional-order differential operator circuit includes a pulse signal V01, and the pulse signal V01 and a NAND gate A1, sample holders SAMP1, SAMP2, SAMP3, SAMP4, SAMP5, and SAMP6 form a sample-hold circuit to achieve output of iterative charges; The inverting adder UA7, the DC power supplies VA1, VA2, VA3, VA4, VA5, VA6, the voltage followers UA1, UA4, UA5, UA6, the resistors RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, RA11, the inverting adders UA2, UA3 form an inverting adding circuit to realize the iterative accumulation process of the charge; Inverter UA8 and resistors RA12 and RA13 form an inverting circuit for restoring the iterated value to a positive value; The value of the DC power supply VA1 is used to realize the first fractional-order discrete memristor circuit order The output end of the sample-and-hold circuit SAMP2 is used as the output end of the first fractional-order differential operator circuit to output the first fractional-order discrete memristor internal charge .

7. The multi-stability circuit based on fractional-order discrete memristors of different orders as claimed in claim 6, characterized in that: The second fractional-order differential operator circuit includes a pulse signal V02, and the pulse signal V02 and a NAND gate A2, sample holders SAMP7, SAMP8, SAMP9, SAMP10, SAMP11, and SAMP12 form a sample-hold circuit to achieve output of iterative charges; The inverting adder UB7, the DC power supplies VB1, VB2, VB3, VB4, VB5, VB6, the voltage followers UB1, UB4, UB5, UB6, the resistors RB1, RB2, RB3, RB4, RB5, RB6, RB7, RB8, RB9, RB10, RB11, the inverting adders UB2 and UB3 form an inverting adding circuit to realize the iterative accumulation process of the charge; Inverter UB8 and resistors RB12 and RB13 form an inverting circuit for restoring the iterated value to a positive value; The value of the DC power supply VB1 is used to realize the second fractional-order discrete memristor circuit order The output end of the sample-and-hold circuit SAMP8 is used as the output end of the second fractional-order differential operator circuit to output the internal charge of the second fractional-order discrete memristor. .

8. The multi-stability circuit based on fractional-order discrete memristors of different orders as claimed in claim 7, characterized in that: The third fractional-order differential operator circuit includes a pulse signal V03, and the pulse signal V03 and a NAND gate A3, sample holders SAMP13, SAMP14, SAMP15, SAMP16, SAMP17, and SAMP18 form a sample-hold circuit to achieve output of iterative charges; The inverting adder UC7, the DC power supplies VC1, VC2, VC3, VC4, VC5, VC6, the voltage followers UC1, UC4, UC5, UC6, the resistors RC1, RC2, RC3, RC4, RC5, RC6, RC7, RC8, RC9, RC10, RC11, the inverting adders UC2, UC3 form an inverting adding circuit to realize the iterative accumulation process of the charge; Inverter UC8 and resistors RC12 and RC13 form an inverting circuit for restoring the iterated value to a positive value; The value of the DC power supply VC1 is used to realize the third fractional-order discrete memristor circuit order The output end of the sample-and-hold circuit SAMP14 is used as the output end of the third fractional-order differential operator circuit to output the internal charge of the third fractional-order discrete memristor. .

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