Preparation method of floating gate structure, floating gate structure and flash memory device

Abstract

The present invention provides a method for preparing a floating gate structure, a floating gate structure and a flash memory device, and specifically relates to the field of semiconductor technology. The preparation method comprises: providing a substrate, on which at least two isolation structures are formed, and a trapezoidal groove with a narrow top and a wide bottom is formed between two adjacent isolation structures; forming a tunneling oxide layer at the bottom of the trapezoidal groove; forming a polysilicon pad layer on the sidewall of the trapezoidal groove to transform the trapezoidal groove into a rectangular groove; and filling the rectangular groove with polysilicon to form a floating gate. The method can effectively improve the void problem in the floating gate filling process and improve the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a floating gate structure, a floating gate structure and a flash memory device. Background Art

[0002] Flash memory is a long-life non-volatile memory. Due to its advantages such as high integration, fast access speed, easy erasure and rewriting, it is widely used in high-tech industries such as mobile communications, data processing, smart terminals, embedded systems, such as personal computers and their peripherals, automotive electronics, network switches, Internet equipment and instrumentation.

[0003] The floating gate (FG) is a key structure for storing charge in flash memory devices. Its performance directly affects the device's data retention, read / write speed, and reliability. With the continuous development of integrated circuit manufacturing technology, the size of flash memory continues to shrink, and the key size of the floating gate in flash memory is also gradually shrinking, which brings challenges to the formation of the floating gate.

[0004] At present, in the process of forming a floating gate, it is necessary to remove the mask layer to form a gap for filling the floating gate. After the mask layer is removed, a trapezoidal gap with a narrow top and wide bottom longitudinal cross-section is easily formed. The opening of this trapezoidal gap is small, and the high aspect ratio and small filling opening make it easy to form a void in the middle of the filled floating gate, thereby reducing the yield of the product. Summary of the invention

[0005] In view of the above shortcomings of the prior art, the present invention provides a method for preparing a floating gate structure, a floating gate structure and a flash memory device to improve the void problem during floating gate filling.

[0006] To achieve the above object and other related objects, the present invention provides a method for preparing a floating gate structure, comprising the following steps:

[0007] Providing a substrate, wherein at least two isolation structures are formed on the substrate, and a trapezoidal trench which is narrow at the top and wide at the bottom is formed between two adjacent isolation structures;

[0008] forming a tunneling oxide layer at the bottom of the trapezoidal trench;

[0009] forming a polysilicon pad layer on the sidewall of the trapezoidal trench to transform the trapezoidal trench into a rectangular trench;

[0010] Polysilicon is filled into the rectangular trench to form a floating gate.

[0011] In an example of the present invention, a polysilicon pad layer is formed on the sidewall of the trapezoidal trench, comprising:

[0012] forming a polysilicon layer on the inner wall of the trapezoidal trench, wherein the polysilicon layer covers the tunneling oxide layer, the sidewall of the trapezoidal trench and the isolation structure on both sides of the trapezoidal trench;

[0013] The polysilicon layer on the isolation structure and the tunnel oxide layer and a portion of the polysilicon layer on the sidewall of the trapezoidal trench are removed to form a polysilicon pad layer on the sidewall of the trapezoidal trench, so that the trapezoidal trench forms a rectangular trench.

[0014] In an example of the present invention, removing the polysilicon layer on the isolation structure and the tunnel oxide layer and a portion of the polysilicon layer on the sidewall of the trapezoidal trench includes:

[0015] Etching the polysilicon layer by dry etching to remove the polysilicon layer on the isolation structure, the polysilicon layer on the tunneling oxide layer, and part of the polysilicon layer on the sidewall of the trapezoidal trench;

[0016] A portion of the polysilicon layer is retained on the sidewall of the trapezoidal trench to form a polysilicon pad layer, so that the trapezoidal trench forms a rectangular trench.

[0017] In an example of the present invention, the side of the polysilicon pad layer that is in contact with the side wall of the trapezoidal trench is tilted, and the side of the polysilicon pad layer that is away from the side wall of the trapezoidal trench is perpendicular to the bottom of the trapezoidal trench.

[0018] In an example of the present invention, after filling the rectangular trench with polysilicon, the method further includes: treating the polysilicon with a chemical mechanical planarization process to remove the polysilicon on the isolation structure to form a floating gate.

[0019] In an example of the present invention, the process of forming at least two isolation structures includes:

[0020] forming a pad oxide layer on the substrate;

[0021] forming a hard mask layer on the pad oxide layer;

[0022] forming a patterned photoresist layer on the hard mask layer, wherein the patterned photoresist layer includes at least two openings defining the isolation structure;

[0023] Using the patterned photoresist layer as a mask, sequentially etching the hard mask layer, the pad oxide layer and the substrate to form a shallow trench;

[0024] An isolation oxide is filled in the shallow trench to form an isolation structure.

[0025] In an example of the present invention, after forming the isolation structure, it also includes: a step of removing the patterned photoresist layer, the hard mask layer and the pad oxide layer, and forming a trapezoidal trench that is narrow at the top and wide at the bottom between two adjacent isolation structures.

[0026] In an example of the present invention, the tunnel oxide layer comprises silicon dioxide, and a method of forming the tunnel oxide layer at the bottom of the trapezoidal trench comprises a thermal oxidation method.

[0027] The present invention further provides a floating gate structure, which is prepared by the above-mentioned preparation method; the floating gate structure comprises:

[0028] A substrate, wherein at least two isolation structures are formed on the substrate, and a trapezoidal trench narrow at the top and wide at the bottom is formed between two adjacent isolation structures;

[0029] a tunneling oxide layer formed at the bottom of the trapezoidal trench;

[0030] A polysilicon pad layer is formed on the sidewall of the trapezoidal trench so that the trapezoidal trench forms a rectangular trench;

[0031] A floating gate is formed in the rectangular trench.

[0032] The present invention also provides a flash memory device, which includes the above-mentioned floating gate structure.

[0033] In an example of the present invention, the flash memory device further includes an inter-gate dielectric layer and a control gate, the inter-gate dielectric layer is disposed on the floating gate, and the control gate is disposed on the inter-gate dielectric layer.

[0034] The preparation method of the floating gate structure of the present invention forms a polysilicon pad on the side wall of the trapezoidal groove before filling the floating gate. The polysilicon pad is completely in contact with the side wall of the trapezoidal groove, and the trapezoidal groove with a narrow top and a wide bottom can be transformed into a rectangular groove. In the subsequent floating gate filling process, the void phenomenon can be effectively improved, and the reliability of the device can be improved. In addition, the polysilicon pad is made of the same material as the polysilicon floating gate, which can improve the void problem in the floating gate while avoiding the introduction of other impurities, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1is a schematic diagram of a floating gate structure prepared in the prior art;

[0037] Figure 2 A flow chart of a method for preparing a floating gate structure according to an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of the structure of a substrate in an embodiment of a method for preparing a floating gate structure of the present invention;

[0039] Figure 4 A schematic diagram of a structure of forming a shallow trench in an embodiment of a method for preparing a floating gate structure of the present invention;

[0040] Figure 5 A schematic diagram of forming an isolation structure in an embodiment of a method for preparing a floating gate structure of the present invention;

[0041] Figure 6 A schematic diagram of a structure of forming a tunnel oxide layer in an embodiment of a method for preparing a floating gate structure of the present invention;

[0042] Figure 7 A schematic diagram of a structure of forming a polysilicon layer in an embodiment of a method for preparing a floating gate structure of the present invention;

[0043] Figure 8 A schematic diagram of a structure of forming a polysilicon pad layer in an embodiment of a method for preparing a floating gate structure of the present invention;

[0044] Fig. 9 for Figure 8 A partial enlarged schematic diagram of the middle area A;

[0045] Fig.10 for Figure 8 A partial enlarged schematic diagram of the middle area B;

[0046] Fig.11 A schematic diagram of a structure of filling floating gate polysilicon in an embodiment of a method for preparing a floating gate structure of the present invention;

[0047] Fig.12 FIG. 4 is a schematic structural diagram of a floating gate structure in an embodiment of the present invention.

[0048] Component number description:

[0049] 100, substrate; 110, pad oxide layer; 120, hard mask layer; 130, isolation structure; 131, shallow trench; 140, trapezoidal trench; 141, tunnel oxide layer; 142, polysilicon layer; 143, polysilicon pad layer; 144, rectangular trench; 150, floating gate. DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0051] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0052] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0053] In the present invention, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0054] In the prior art, the method for preparing a floating gate includes sequentially forming a pad oxide layer and a mask layer on a substrate, then etching a trench, and then filling the trench with oxide to form an isolation structure; then removing the mask layer and the pad oxide layer to form a gap between adjacent isolation structures for filling the floating gate. In the above floating gate preparation process, a very thick mask layer is usually formed, and a trapezoidal isolation trench is easily formed during the etching process of the mask layer, resulting in the gap for filling the floating gate formed after the subsequent removal of the mask layer. It is also a trapezoidal gap that is narrow at the top and wide at the bottom. This trapezoidal gap is prone to cause voids during the floating gate filling process (see Figure 1 ), causing the device to open circuit or even invalid, thus affecting the reliability of the device.

[0055] Based on this, the present invention provides a method for preparing a floating gate structure, a floating gate structure and a flash memory device. Before the floating gate is filled, a polysilicon liner is formed on the side wall of the trapezoidal trench to transform the trapezoidal trench into a rectangular trench, which can effectively improve the void problem in the floating gate filling process.

[0056] See also Figures 2 to 12 According to a first aspect of the present invention, there is provided a method for preparing a floating gate structure, the method comprising the following steps:

[0057] S1. Provide a substrate 100. The substrate 100 has at least two isolation structures 130 formed thereon. A trapezoidal trench 140 (see FIG. 1 ) is formed between two adjacent isolation structures 130 and is narrow at the top and wide at the bottom. Figure 5 );

[0058] S2, forming a tunnel oxide layer 141 at the bottom of the trapezoidal trench 140 (see Figure 6 );

[0059] S3, forming a polysilicon pad layer 143 on the sidewall of the trapezoidal trench 140 to transform the trapezoidal trench 140 into a rectangular trench 144 (see Figures 8 to 10 );

[0060] S4, filling polysilicon into the rectangular trench 144 to form a floating gate 150 (see Fig.12 ).

[0061] Combine the following Figures 3 to 12 The steps of the method for preparing the floating gate structure in the embodiment of the present invention are described in detail.

[0062] See also Figure 3 In step S1, the substrate 100 may be made of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III / V compound semiconductor materials. In addition, the substrate may also be a stacked substrate material such as Si / SiGe, Si / SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI). In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 may form an active region by a doping process, such as an ion implantation process.

[0063] See also Figures 3 to 5 The isolation structure 130 formed on the substrate 100 extends downward into the interior of the substrate 100 and is used to isolate the active areas on the substrate 100. Each active area can be used to form a semiconductor device. The top of the isolation structure 130 is higher than the upper surface of the substrate 100, and the groove area between two adjacent isolation structures 130 forms a filling area for the floating gate 150.

[0064] In one embodiment, the isolation structure 130 is a shallow trench isolation (STI) structure. The formation process of the shallow trench isolation structure is as follows:

[0065] See also Figure 3 , a pad oxide layer 110 is formed on the substrate 100. The pad oxide layer 110 includes but is not limited to silicon dioxide (SiO2). The pad oxide layer 110 can be prepared by, for example, a thermal oxidation method or a chemical vapor deposition (CVD) process.

[0066] A hard mask layer 120 is formed on the pad oxide layer 110. The hard mask layer 120 is, for example, silicon nitride (Si3N4), and can be formed by processes such as chemical vapor deposition and physical vapor deposition (PVD). The pad oxide layer 110 can be used as a buffer layer to prevent the hard mask layer 120 with a relatively high hardness from directly contacting the substrate 100 and damaging the substrate 100; the hard mask layer 120 can be used as a hard mask to etch and replicate the corresponding pattern.

[0067] Furthermore, before etching, a patterned photoresist layer (not shown in the figure) needs to be formed on the hard mask layer 120, that is, the photoresist layer is first spin-coated on the hard mask layer 120, and at least two openings are formed on the photoresist layer through exposure and development processes to form a patterned photoresist layer with an etching pattern on the hard mask layer 120. The at least two openings are used to define the position of the isolation structure 130, and the openings expose the bottom hard mask layer 120.

[0068] See also Figure 4 , using the patterned photoresist layer as a mask, the hard mask layer 120, the pad oxide layer 110 and a portion of the substrate 100 are sequentially etched to form a shallow trench 131, which does not penetrate the substrate 100. The etching process can be performed using methods well known to those skilled in the art, such as dry etching and / or wet etching. The shallow trench 131 structure formed gradually narrows from top to bottom, which is helpful for subsequent filling of insulating materials, and also makes the hard mask layer 120 gradually narrow from bottom to top.

[0069] See also Figure 5After the shallow trench 131 is formed, an isolation oxide is filled in the shallow trench 131 to form an isolation structure 130. The isolation oxide is, for example, an insulating material such as silicon dioxide, but is not limited thereto and may also be other insulating materials. The isolation oxide filling method may adopt, for example, a high aspect ratio filling process (High Aspect Ratio Process, HARP), a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or a plasma chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) and other processes. After the isolation oxide deposition is completed, the isolation oxide is also planarized until the height of the isolation oxide is flush with the hard mask layer 120. The planarization process may adopt, for example, a chemical mechanical polishing (CMP) process. After the planarization process is completed, the isolation structure 130 is formed. However, it can be understood by those skilled in the art that the isolation structure 130 in the present invention may also adopt other existing means in the art, and is not limited to the manufacturing process of the above-mentioned isolation structure 130.

[0070] After the isolation structure 130 is formed, the process also includes removing the patterned photoresist layer, the hard mask layer 120 and the pad oxide layer 110, wherein the patterned photoresist layer can be removed by a plasma ashing process, and the hard mask layer 120 and the pad oxide layer 110 can be removed by an etching process, such as dry etching and / or wet etching. Since the shallow trench 131 formed gradually narrows from top to bottom, the hard mask layer 120 between two adjacent isolation structures 130 gradually narrows from bottom to top, and after removing the hard mask layer 120 and the pad oxide layer 110, a trapezoidal trench 140 gradually narrows from bottom to top is formed, that is, the longitudinal cross section of the formed trench is a trapezoidal shape with a narrow top and a wide bottom.

[0071] See also Figure 6 and Fig.12 , perform step S2 to form a tunneling oxide layer 141 at the bottom of the trapezoidal trench 140. The tunneling oxide layer 141 is used to isolate the floating gate 150 from the substrate 100 to prevent charges from flowing directly from the floating gate 150 to other parts of the transistor. The tunneling oxide layer 141 allows charges to move from one area to another through the quantum tunneling effect. During the flash memory erase process, the charges stored on the floating gate 150 tunnel to the source or body region through the tunneling oxide layer 141 to achieve data erasure. The tunneling oxide layer 141 is, for example, silicon dioxide, and the tunneling oxide layer 141 can be formed by thermal oxidation, chemical vapor deposition, physical vapor deposition and other processes. The thermal oxidation method is, for example, wet oxidation, dry oxidation or in-situ water vapor generation.

[0072] See also Figure 6 , Figure 8 , Fig.10 and Fig.11 Since the groove for filling the floating gate 150 formed in step S1 is a trapezoidal groove 140 with a longitudinal cross section of being narrow at the top and wide at the bottom, such a groove is easy to form voids in the subsequent floating gate 150 filling process due to its small opening size. In order to improve the void problem in the floating gate 150 filling process, the present invention adds step S3 to form a polysilicon pad layer 143 on the side wall of the trapezoidal groove 140. The polysilicon pad layer 143 gradually widens from top to bottom, and the polysilicon pad layer 143 is completely attached to the side wall of the trapezoidal groove 140, so that the trapezoidal groove 140 is transformed into a rectangular groove 144 with a rectangular longitudinal cross section under the auxiliary effect of the polysilicon pad layer 143.

[0073] See also Fig. 9 Specifically, the side of the polysilicon pad layer 143 that is in contact with the side wall of the trapezoidal trench 140 is tilted, and its tilt angle (the angle between the hypotenuse of the polysilicon pad layer 143 and the bottom wall of the trapezoidal trench 140) is the same as the tilt angle of the side wall of the trapezoidal trench 140 (the angle between the side wall and the bottom of the trapezoidal trench 140), and the side of the polysilicon pad layer 143 that is away from the side wall of the trapezoidal trench 140 is perpendicular to the bottom of the trapezoidal trench 140. The polysilicon pad layer 143 of this structure filled in the trapezoidal trench 140 can make up for the tilt angle of the side wall of the trapezoidal trench 140, and transform the trapezoidal trench 140 into a rectangular trench 144. In addition, since the floating gate 150 filled later also uses polysilicon, the use of polysilicon as a pad layer in this step will not introduce additional impurities.

[0074] See also Figures 7 to 10 In one embodiment, the formation process of the polysilicon pad layer 143 is as follows:

[0075] A polysilicon layer 142 is formed on the inner wall of the trapezoidal trench 140. The polysilicon layer 142 covers the tunnel oxide layer 141 at the bottom of the trapezoidal trench 140, the sidewalls of the trapezoidal trench 140, and the isolation structures 130 on both sides of the trapezoidal trench 140 (see Figure 7 ).

[0076] The formation method of the polysilicon layer 142 includes but is not limited to low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). The deposition thickness of the polysilicon layer 142 is not particularly limited, as long as it does not fill the trapezoidal groove 140. Furthermore, the deposition thickness of the polysilicon layer 142 is at least the size of the top of the side wall of the trapezoidal groove 140 exceeding the bottom. For example, if the top of the side wall of the trapezoidal groove 140 exceeds the bottom by 5nm, the deposition thickness of the polysilicon layer 142 is at least 5nm. Only in this way can the polysilicon pad layer 143 obtained in the subsequent processing process completely make up for the inclined part of the side wall of the trapezoidal groove 140. Furthermore, the deposition thickness of the polysilicon layer 142 is less than or equal to half of the size of the top opening of the trapezoidal trench 140. Since the polysilicon layer 142 is deposited on the sidewalls of the trapezoidal trench 140 on both sides, when the deposition thickness of the polysilicon layer 142 is equal to half of the size of the top opening of the trapezoidal trench 140, the deposition thickness of the two sidewalls of the trapezoidal trench 140 on both sides is added to fill the top opening of the trapezoidal trench 140. Therefore, the deposition thickness of the polysilicon layer 142 is less than or equal to half of the size of the top opening of the trapezoidal trench 140. As an example, if the top opening of the trapezoidal trench 140 is 40nm, the deposition thickness of the polysilicon layer 142 is less than or equal to 20nm.

[0077] The polysilicon layer 142 on the isolation structure 130 and the tunnel oxide layer 141 and a portion of the polysilicon layer 142 on the sidewall of the trapezoidal trench 140 are removed to form a polysilicon pad layer 143 on the sidewall of the trapezoidal trench 140 (see Figure 8 and Fig. 9 ).

[0078] Since the polysilicon layer 142 will be deposited on all exposed surfaces of the wafer substrate 100, that is, the tunneling oxide layer 141 at the bottom of the groove 140, the sidewalls of the trapezoidal groove 140, and the isolation structure 130 on both sides of the trapezoidal groove 140 are all deposited with polysilicon, and only part of the polysilicon on the sidewalls of the trapezoidal groove 140 needs to be retained to form the polysilicon pad layer 143, it is necessary to remove the polysilicon layer 142 on the isolation structure 130 and the tunneling oxide layer 141 and part of the polysilicon layer 142 on the sidewalls of the trapezoidal groove 140. In this embodiment, the process of removing the polysilicon layer 142 adopts dry etching, such as plasma etching (Plasma Etching), reactive ion etching (Reactive Ion Etching, RIE), etc. Since the trapezoidal trench 140 is a structure that is narrow at the top and wide at the bottom, the isolation oxide on the sidewall of the trapezoidal trench 140 has a certain blocking effect during the etching process, so the polysilicon layer 142 covered by the sidewall is retained to form a polysilicon pad layer 143, and the polysilicon layer 142 not covered by the sidewall is etched away. After the etching is completed, the trapezoidal trench 140 is transformed into a rectangular trench 144 with the same width at the top and bottom with the assistance of the polysilicon pad layer 143.

[0079] See also Figures 10 to 12 , executing step S4, filling polysilicon into the rectangular trench 144 to form a floating gate 150.

[0080] The filling method of polysilicon in this step can adopt the technical means known in the art, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. While filling the rectangular groove 144, the polysilicon will cover the isolation structure 130 on both sides of the rectangular groove 144 to provide a margin for the subsequent planarization of the polysilicon. After the polysilicon deposition is completed, the polysilicon is also processed by a chemical mechanical planarization process until the top of the isolation structure 130 is exposed, and the thickness of the remaining polysilicon meets the requirements of the floating gate thickness, so as to form a floating gate 150.

[0081] See also Fig.12 The present invention also provides a floating gate structure, which is prepared by the preparation method described above. The floating gate structure includes a substrate 100, a tunneling oxide layer 141, a polysilicon pad layer 143 and a floating gate 150.

[0082] The substrate 100 may be made of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III / V compound semiconductor materials. In addition, the substrate may also be a stacked substrate material such as Si / SiGe, Si / SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI). In this embodiment, the substrate 100 is a silicon substrate.

[0083] At least two isolation structures 130 are formed on the substrate 100, and the bottom of the isolation structure 130 extends into the interior of the substrate 100, and the top of the isolation structure 130 is higher than the upper surface of the substrate 100. The isolation structure 130 is, for example, a shallow trench isolation (STI) structure. A trapezoidal trench 140 with a narrow top and a wide bottom is formed between two adjacent isolation structures 130.

[0084] The tunnel oxide layer 141 is formed at the bottom of the trapezoidal trench 140 . The tunnel oxide layer 141 is, for example, silicon oxide, and its thickness can be designed according to conventional means in the art.

[0085] The polysilicon pad layer 143 is formed on the side wall of the trapezoidal groove 140. Specifically, the side of the polysilicon pad layer 143 that is in contact with the side wall of the trapezoidal groove 140 is tilted, and its tilt angle (the angle between the hypotenuse of the polysilicon pad layer 143 and the bottom wall of the trapezoidal groove 140) is the same as the tilt angle of the side wall of the trapezoidal groove 140 (the angle between the side wall and the bottom of the trapezoidal groove 140). The side of the polysilicon pad layer 143 that is away from the side wall of the trapezoidal groove 140 is perpendicular to the bottom of the trapezoidal groove 140. The polysilicon pad layer 143 of this structure is filled in the trapezoidal groove 140 to make up for the tilt angle of the lower part of the side wall of the trapezoidal groove 140, and the trapezoidal groove 140 is transformed into a rectangular groove 144.

[0086] The floating gate 150 is made of polysilicon, and the polysilicon is filled in the rectangular trench 144 .

[0087] The floating gate structure of the present invention has a polysilicon pad layer 143 added in the trapezoidal trench. Under the action of the polysilicon pad layer 143, the trapezoidal trench 140 is transformed into a rectangular trench 144. In the subsequent filling process, the void problem in the polysilicon of the floating gate 150 can be effectively improved, thereby improving the reliability of the floating gate structure.

[0088] Based on the same inventive concept, the present invention also provides a flash memory device, which includes the above-mentioned floating gate structure.

[0089] In one embodiment, the flash memory device further includes an inter-gate dielectric layer and a control gate, wherein the inter-gate dielectric layer is disposed on the floating gate 150, and the control gate is disposed on the inter-gate dielectric layer. The inter-gate dielectric layer is used to isolate the floating gate 150 from the control gate, and the material of the inter-gate dielectric layer may include silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide (ONO), etc., and the material of the control gate may be polysilicon.

[0090] The preparation method of the floating gate structure of the present invention forms a polysilicon pad on the side wall of the trapezoidal groove before filling the floating gate, and uses the polysilicon pad to transform the narrow upper and wide lower trapezoidal groove into a rectangular groove, which can effectively improve the void phenomenon in the floating gate in the subsequent filling process and improve the reliability of the device. Therefore, the present invention effectively overcomes some practical problems in the prior art and has high utilization value and use significance.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a floating gate structure, characterized in that: include: Providing a substrate, on which at least two isolation structures are formed, a trapezoidal trench narrow at the top and wide at the bottom is formed between two adjacent isolation structures, and the isolation structure is composed of isolation oxide; forming a tunneling oxide layer at the bottom of the trapezoidal trench; forming a polysilicon pad layer on the sidewall of the trapezoidal trench to transform the trapezoidal trench into a rectangular trench; Filling polysilicon into the rectangular trench to form a floating gate; Wherein, forming a polysilicon pad layer on the sidewall of the trapezoidal trench comprises: forming a polysilicon layer on the inner wall of the trapezoidal trench, wherein the polysilicon layer covers the tunneling oxide layer, the sidewall of the trapezoidal trench and the isolation structure on both sides of the trapezoidal trench; Using dry etching to remove the polysilicon layer on the isolation structure and the tunnel oxide layer and part of the polysilicon layer on the sidewall of the trapezoidal trench, so as to form a polysilicon pad layer on the sidewall of the trapezoidal trench, so that the trapezoidal trench forms a rectangular trench; During the etching process, the isolation oxide of the isolation structure has a certain blocking effect, the polysilicon layer located below the isolation oxide is retained to form the polysilicon pad layer, and the polysilicon layer at other positions is etched away; after the etching is completed, the trapezoidal groove is transformed into a rectangular groove with the same width from top to bottom with the assistance of the polysilicon pad layer; The side of the polysilicon pad layer that is in contact with the side wall of the trapezoidal trench is tilted, and the side of the polysilicon pad layer that is away from the side wall of the trapezoidal trench is perpendicular to the bottom of the trapezoidal trench.

2. The preparation method according to claim 1, characterized in that: After the rectangular trench is filled with polysilicon, the method further includes: treating the polysilicon with a chemical mechanical planarization process to remove the polysilicon on the isolation structure to form a floating gate.

3. The preparation method according to claim 1, characterized in that: The process of forming at least two isolation structures comprises: forming a pad oxide layer on the substrate; forming a hard mask layer on the pad oxide layer; forming a patterned photoresist layer on the hard mask layer, wherein the patterned photoresist layer includes at least two openings defining the isolation structure; Using the patterned photoresist layer as a mask, sequentially etching the hard mask layer, the pad oxide layer and the substrate to form a shallow trench; An isolation oxide is filled in the shallow trench to form an isolation structure.

4. The preparation method according to claim 1, characterized in that: The tunnel oxide layer includes silicon dioxide, and a method of forming the tunnel oxide layer at the bottom of the trapezoidal trench includes a thermal oxidation method.

5. A floating gate structure, characterized in that: Prepared by the preparation method according to any one of claims 1 to 4; the floating gate structure comprises: A substrate, wherein at least two isolation structures are formed on the substrate, and a trapezoidal trench narrow at the top and wide at the bottom is formed between two adjacent isolation structures; a tunneling oxide layer formed at the bottom of the trapezoidal trench; A polysilicon pad layer is formed on the sidewall of the trapezoidal trench so that the trapezoidal trench forms a rectangular trench; A floating gate is formed in the rectangular trench.

6. A flash memory device, characterized in that: Includes the floating gate structure as claimed in claim 5.

7. The flash memory device according to claim 6, wherein: The flash memory device further comprises an inter-gate dielectric layer and a control gate, wherein the inter-gate dielectric layer is arranged on the floating gate, and the control gate is arranged on the inter-gate dielectric layer.

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