MOS transistor and method for manufacturing the same

Abstract

The present invention provides a MOS transistor and a preparation method thereof. When the MOS transistor is a Trench NMOS transistor, two switches are set, the first switch is composed of a first polysilicon, two first N-type doping regions and a P-type well region, the first polysilicon is deposited on a first oxide layer, the second switch is composed of a gate formed by a second polysilicon in a groove opened in an epitaxial layer, the second polysilicon is deposited on a second oxide layer, the thickness of the first oxide layer is greater than the thickness of the second oxide layer, and when the MOS transistor is a Trench PMOS transistor, all doping types are opposite to those of the Trench NMOS transistor. Specifically, due to the two switches, the resistance of the MOS transistor is stable when the gate voltage fluctuates, and the MOS transistor can be satisfied with having a larger turn-on voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a MOS transistor and a preparation method thereof. Background Art

[0002] In today's era of rapid development of electronic technology, the performance and stability requirements of circuits are constantly increasing. Power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), also known as MOS transistor, is an important electronic device that plays a key role in many fields.

[0003] With the development trend of miniaturization, intelligence and high precision of electronic devices, many circuits have put forward higher requirements on the performance of power MOS transistors. Among them, in some specific application scenarios, the resistance stability of MOS transistors has become a key factor in achieving high performance and stable operation of circuits.

[0004] In constant current source circuits, stable current output is essential for many electronic devices. Whether it is LED lighting driving, battery charging management or current supply in precision instruments, a reliable constant current source is required. When MOS transistors are used as adjustment tubes in constant current source circuits, if their resistance can remain stable, the stability of the output current can be ensured under different working conditions, such as input voltage fluctuations.

[0005] Taking Trench MOS as an example, generally speaking, the thinner the gate oxide layer of the MOS transistor, the smaller the resistance fluctuation of the MOS transistor is when the gate voltage changes within a certain range, and the more stable it is. However, the thinner the gate oxide layer, the smaller the turn-on voltage of the device. However, in some applications, in order to prevent problems such as false turn-on and leakage, MOS transistors require a larger turn-on voltage, so there is a contradiction between demand and performance. Summary of the invention

[0006] Based on this, the purpose of the present invention is to provide a MOS transistor and a method for preparing the same, aiming to stabilize the resistance of the MOS transistor when the gate voltage fluctuates, while satisfying that the MOS transistor has a larger turn-on voltage.

[0007] According to a MOS transistor in an embodiment of the present invention, when the MOS transistor is a Trench NMOS transistor, the Trench NMOS transistor includes a substrate and an epitaxial layer deposited on the substrate, the epitaxial layer is provided with a trench, two first N-type doping regions and a P-type well region are arranged on both sides of the trench, the P-type well region includes a first sub-region and a second sub-region extending from the first sub-region in a direction away from the substrate, the two first N-type doping regions are symmetrical about the second sub-region, the region between the P-type well region and the substrate is a second N-type doping region, and the doping concentration of the first N-type doping region is greater than the doping concentration of the second N-type doping region;

[0008] The two first N-type doped regions on both sides of the trench and the end of the P-type well region away from the substrate are sequentially deposited with a first oxide layer and a first polysilicon;

[0009] A second oxide layer is deposited on the surface of the groove, and the groove formed by the second oxide layer is filled with second polysilicon;

[0010] The first polysilicon forms a first gate, and forms a first switch with the corresponding two first N-type doped regions and the P-type well region; the second polysilicon forms a second gate, and serves as a second switch; the thickness of the first oxide layer is greater than the thickness of the second oxide layer; the first N-type doped region away from the trench is used to be electrically connected to the source; the first gate and the second gate are electrically connected to the gate, respectively; and the substrate is electrically connected to the drain;

[0011] Alternatively, when the MOS transistor is a Trench PMOS transistor, all doping types are opposite to those of the Trench NMOS transistor.

[0012] Furthermore, the depth of the trenches formed in the epitaxial layer is 1 μm to 1.5 μm.

[0013] Furthermore, the thickness of the first oxide layer is 500Å~1200Å.

[0014] Furthermore, the thickness of the second oxide layer is 80Å~150Å.

[0015] Furthermore, the impurity of the P-type well region is B, and the doping concentration is 1E10 atom / cm 3 ~1E14 atoms / cm 3 , the temperature is 700℃~1000℃.

[0016] Furthermore, the impurity of the first N-type doping region is P, and the doping concentration is 1E13atom / cm 3 ~1E17atom / cm 3, the temperature is 800℃~1100℃.

[0017] Furthermore, the surface of the second polysilicon is 0.2 μm to 0.5 μm lower than the surface of the second oxide layer.

[0018] According to an embodiment of the present invention, a method for preparing a MOS transistor is used to prepare the above-mentioned MOS transistor. When the MOS transistor is a Trench NMOS transistor, the preparation method includes:

[0019] Providing a substrate, and depositing an epitaxial layer on the substrate, wherein the epitaxial layer is an N-type epitaxial layer;

[0020] Etching a groove on the N-type epitaxial layer and depositing a second oxide layer on the surface, then filling the groove formed by the second oxide layer with polysilicon, and then performing CMP grinding and etching to obtain second polysilicon;

[0021] Performing P-type doping in a preset area of ​​the N-type epitaxial layer and depositing a first oxide layer;

[0022] depositing first polysilicon on the first oxide layer;

[0023] On the basis of the preset P-type doped area, N-type doping is performed to obtain a first N-type doped area, and finally two first N-type doped areas and a P-type well area are formed on both sides of the groove etched on the N-type epitaxial layer, the P-type well area includes a first sub-area and a second sub-area extending from the first sub-area in a direction away from the substrate, the two first N-type doped areas are symmetrical about the second sub-area, and the doping concentration of the first N-type doped area is greater than the doping concentration of the N-type epitaxial layer;

[0024] The first polysilicon forms a first gate, and forms a first switch with the corresponding two first N-type doped regions and the P-type well region; the second polysilicon forms a second gate, and serves as a second switch; the thickness of the first oxide layer is greater than the thickness of the second oxide layer; the first N-type doped region away from the trench is used to be electrically connected to the source; the first gate and the second gate are electrically connected to the gate, respectively; and the substrate is electrically connected to the drain;

[0025] Alternatively, when the MOS transistor is a trench PMOS transistor, all doping types are controlled opposite to those of a trench NMOS transistor.

[0026] Compared with the prior art: when the MOS transistor is a Trench NMOS transistor, the Trench NMOS transistor includes a substrate and an epitaxial layer deposited on the substrate, a trench is provided in the epitaxial layer, two first N-type doping regions and a P-type well region are arranged on both sides of the trench, the P-type well region includes a first sub-region and a second sub-region extending from the first sub-region toward a direction away from the substrate, the two first N-type doping regions are symmetrical about the second sub-region, the region between the P-type well region and the substrate is the second N-type doping region, and the doping concentration of the first N-type doping region is greater than the doping concentration of the second N-type doping region; the two first N-type doping regions on both sides of the trench and the end of the P-type well region away from the substrate are sequentially deposited with a first oxide layer and a first polysilicon; A second oxide layer is deposited on the surface of the groove, and the groove formed by the second oxide layer is filled with a second polysilicon; wherein the first polysilicon forms a first gate, and forms a first switch with the corresponding two first N-type doped regions and the P-type well region, and the second polysilicon forms a second gate. As the second switch, the thickness of the first oxide layer is greater than the thickness of the second oxide layer, and the first N-type doped region away from the groove is used to be electrically connected to the source, the first gate and the second gate are electrically connected to the gate respectively, and the substrate is electrically connected to the drain, so that the resistance of the MOS transistor is stable when the gate voltage fluctuates, and the MOS transistor can have a large turn-on voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the structure of a MOS transistor provided by an embodiment of the present invention;

[0028] Figure 2 A flowchart of a method for manufacturing a MOS transistor provided by an embodiment of the present invention;

[0029] Figure 3 A schematic diagram of a process flow of a MOS transistor provided in Example 1 of the present invention.

[0030] Description of main component symbols:

[0031]

[0032] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0034] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0036] refer to Figure 1 , Figure 1 A schematic diagram of a MOS transistor structure provided by an embodiment of the present invention, wherein G1 represents a first gate connection, G2 represents a second gate connection, S represents a source connection, D represents a drain connection, N represents a + The symbol indicates heavy doping. Specifically, when the MOS transistor is a Trench NMOS transistor, the Trench NMOS transistor includes a substrate 1 and an epitaxial layer deposited on the substrate. It can be understood that the Trench NMOS transistor is a special structural form of an NMOS (N-type metal oxide semiconductor) transistor, and its main feature lies in its unique trench design.

[0037] The epitaxial layer in the Trench NMOS transistor is provided with a trench, and the depth of the trench is 1μm~1.5μm. Exemplarily, the depth of the trench is 1μm, 1.1μm, 1.2μm, 1.3μm, 1.4μm or 1.5μm, etc., but not limited thereto. Two first N-type doping regions 2 and P-type well regions 3 are arranged on both sides of the trench. The P-type well region 3 includes a first sub-region 31 and a second sub-region 32 extending from the first sub-region 31 away from the substrate 1. The two first N-type doping regions 2 are symmetrical about the second sub-region 32. The region between the P-type well region 3 and the substrate 1 is the second N-type doping region 4. It should be noted that the pattern of the P-type well region 3 can be a triangle, " ", and the doping concentration of the first N-type doping region 2 is greater than the doping concentration of the second N-type doping region 4, wherein the impurity of the first N-type doping region 2 is P (phosphorus), and the doping concentration is 1E13atom / cm 3 ~1E17atom / cm 3 , the temperature is 800℃~1100℃, and the doping concentration of the second N-type doping region 4 is 5E14atom / cm3 ~1E17atom / cm 3 In addition, the impurity of P-type well region 3 is B (boron) with a doping concentration of 1E10 atom / cm 3 ~1E14 atoms / cm 3 , the temperature is 700℃~1000℃;

[0038] The two first N-type doped regions 2 on both sides of the trench and the end of the P-type well region 3 away from the substrate 1 are sequentially deposited with a first oxide layer 5 and a first polysilicon 6, and the thickness of the first oxide layer 5 is 500Å~1200Å. Exemplarily, the thickness of the first oxide layer 5 is 500Å, 600Å, 700Å, 800Å, 900Å, 1000Å, 1100Å or 1200Å, etc., but not limited thereto;

[0039] A second oxide layer 7 is deposited on the surface of the groove, and the groove formed by the second oxide layer 7 is filled with a second polysilicon 8. The thickness of the second oxide layer 7 is 80Å~150Å. Exemplarily, the thickness of the second oxide layer 7 is 80Å, 90Å, 100Å, 110Å, 120Å, 130Å, 140Å or 150Å, etc., but not limited thereto. It should be noted that the thickness of the first oxide layer 5 should be greater than 3 times the thickness of the second oxide layer 7. In addition, the surface of the second polysilicon 8 is 0.2μm~0.5μm lower than the surface of the second oxide layer 7. Exemplarily, the surface of the second polysilicon 8 is 0.2μm, 0.3μm, 0.4μm or 0.5μm lower than the surface of the second oxide layer 7, etc., but not limited thereto. The purpose is to ensure that there is no polysilicon residue to cause a short circuit while forming the gate;

[0040] Among them, the first polysilicon 6 forms a first gate, and constitutes a first switch with the corresponding two first N-type doped regions 2 and P-type well region 3. The second polysilicon 8 forms a second gate. As a second switch, the thickness of the first oxide layer 5 is greater than the thickness of the second oxide layer 7. The first N-type doped region 2 away from the groove is used to be electrically connected to the source, the first gate and the second gate are electrically connected to the gate respectively, and the substrate is electrically connected to the drain.

[0041] More specifically, when the device is working, a large voltage is connected to the first gate to turn on the horizontal channel below it, and a driving voltage is connected to the second gate to make the device work in the linear region according to the driving requirements. At this time, the vertical channel next to the second gate is turned on, and the entire device is turned on and starts working. At this time, the device is equivalent to the horizontal channel resistance below the first gate and the vertical channel resistance next to the second gate in series. Since the voltage on the first gate is increased, its channel is fully turned on and the channel resistance remains unchanged, so it will not affect the stability of the device resistance.

[0042] When the device is turned off, the device has two switches. The first gate has a large turn-on voltage, which can prevent accidental turn-on. The second gate has a small turn-on voltage. Even if the second gate is mistakenly turned on by a fluctuating voltage, there will be no leakage because the first N-type doped region 2 close to the second gate is floating. The device will only be turned on when the two switches are turned on at the same time, so the device also has ultra-low leakage performance.

[0043] It should be noted that when the MOS transistor is a Trench PMOS transistor, all doping types are opposite to those of the Trench NMOS transistor. Specifically, the Trench NMOS transistor includes a substrate and an epitaxial layer deposited on the substrate, the epitaxial layer is provided with a trench, two first P-type doping regions and an N-type well region are provided on both sides of the trench, the N-type well region includes a third sub-region and a fourth sub-region extending from the third sub-region in a direction away from the substrate, the two first P-type doping regions are symmetrical about the third sub-region, the region between the N-type well region and the substrate is a second P-type doping region, and the doping concentration of the first P-type doping region is greater than the doping concentration of the second P-type doping region;

[0044] The first oxide layer and the first polysilicon are sequentially deposited on the two first P-type doped regions on both sides of the trench and the end of the N-type well region away from the substrate;

[0045] A second oxide layer is deposited on the surface of the groove, and the groove formed by the second oxide layer is filled with second polysilicon;

[0046] Among them, the first polysilicon forms a first gate, and constitutes a first switch with the corresponding two first P-type doped regions and the N-type well region. The second polysilicon forms a second gate as a second switch. The thickness of the first oxide layer is greater than the thickness of the second oxide layer. The first P-type doped region away from the groove is used to be electrically connected to the source. The first gate and the second gate are electrically connected to the gate respectively, and the substrate is electrically connected to the drain.

[0047] In some other embodiments of the present invention, the epitaxial layer on the substrate can be eliminated and the MOS transistor can be directly prepared using an N-type substrate, that is, a trench is opened on the N-type substrate and a first N-type doped region and a P-type well region are set.

[0048] refer to Figure 2 , Figure 2 A flowchart of a method for manufacturing a MOS transistor provided in an embodiment of the present invention is provided. Taking the MOS transistor as a Trench NMOS transistor as an example, the manufacturing method specifically includes the following steps:

[0049] S100: providing a substrate, and depositing an epitaxial layer on the substrate, wherein the epitaxial layer is an N-type epitaxial layer;

[0050] The substrate may be a Si substrate.

[0051] S200: etching a groove on the N-type epitaxial layer and depositing a second oxide layer on the surface, then filling the groove formed by the second oxide layer with polysilicon, and then performing CMP grinding and etching to obtain second polysilicon;

[0052] Among them, the depth of the groove etched on the N-type epitaxial layer is 1μm~1.5μm, and then a high-quality thin oxide layer is grown by thermal oxidation (oxygen is introduced at a high temperature of 800℃~1100℃) as the dielectric layer of the second polysilicon sidewall. Specifically, the second oxide layer is 80Å~150Å. In addition, after CMP grinding and etching, the surface of the second polysilicon is 0.2μm~0.5μm lower than the surface of the second oxide layer.

[0053] S300: performing P-type doping in a preset region of the N-type epitaxial layer, and depositing a first oxide layer;

[0054] It can be understood that the preset area of ​​the N-type epitaxial layer is the area on the top of the N-type epitaxial layer on both sides of the trench, and the P-type doped impurity is B (boron) with a doping concentration of 1E10 atom / cm 3 ~1E14 atoms / cm 3 , the temperature is 700℃~1000℃, and the thickness of the first oxide layer is 500Å~1200Å.

[0055] S400: depositing first polysilicon on the first oxide layer;

[0056] The width of the first polysilicon deposited on the first oxide layer is consistent with that of the first oxide layer, and the thickness of the first polysilicon is 0.6 μm-0.8 μm.

[0057] S500: performing N-type doping on the basis of the preset P-type doped area to obtain a first N-type doped area, and finally forming two first N-type doped areas and a P-type well area on both sides of the trench etched on the N-type epitaxial layer;

[0058] Specifically, the P-type well region includes a first sub-region and a second sub-region extending from the first sub-region toward a direction away from the substrate. The two first N-type doped regions are symmetrical about the second sub-region. The doping concentration of the first N-type doped region is greater than the doping concentration of the N-type epitaxial layer. The N-type doped impurity is P (phosphorus) with a doping concentration of 1E13atom / cm 3 ~1E17atom / cm 3 , the temperature is 800℃~1100℃.

[0059] Among them, the first polysilicon forms a first gate, and constitutes a first switch with the corresponding two first N-type doped regions and P-type well region. The second polysilicon forms a second gate. As a second switch, the thickness of the first oxide layer is greater than the thickness of the second oxide layer. The first N-type doped region away from the groove is used to be electrically connected to the source, the first gate and the second gate are electrically connected to the gate respectively, and the substrate is electrically connected to the drain.

[0060] On the basis of the above, an oxide layer is deposited as a dielectric layer as a whole, and then CT (through hole) etching is performed, and finally metal aluminum is deposited to form the electrode of the MOS transistor.

[0061] It should be noted that when the MOS transistor is a Trench PMOS transistor, all doping types are controlled opposite to those of the Trench NMOS transistor.

[0062] The MOS transistor obtained by the above scheme has the following beneficial effects:

[0063] 1. The device can have a large turn-on voltage according to demand;

[0064] 2. When the device works in the linear region, the resistance fluctuates little with the gate drive voltage and has high stability;

[0065] 3. Double switch structure to prevent accidental opening and ultra-low leakage performance;

[0066] 4. Solve the contradiction that existing devices cannot meet the requirements of large start-up voltage and resistance stability at the same time.

[0067] The present invention will be further described below with specific embodiments:

[0068] Example 1

[0069] Embodiment 1 of the present invention provides a method for preparing a MOS transistor. Taking the MOS transistor as a Trench NMOS transistor as an example, refer to Figure 3 , is a schematic diagram of a process flow of a MOS transistor provided in Embodiment 1 of the present invention. Specifically, the following steps are included:

[0070] (1) providing a Si substrate and depositing an epitaxial layer on the Si substrate, wherein the epitaxial layer is an N-type epitaxial layer 40;

[0071] (2) etching a groove on the N-type epitaxial layer 40 and depositing a second oxide layer 7 on the surface, then filling the groove formed by the second oxide layer 7 with polysilicon, and then performing CMP grinding and etching to obtain a second polysilicon 8, wherein the depth of the groove etched on the N-type epitaxial layer 40 is 1 μm, and then oxygen is introduced at 800° C. to grow a second oxide layer 7 of 100 Å. In addition, after CMP grinding and etching, the surface of the second polysilicon 8 is 0.2 μm lower than the surface of the second oxide layer 7;

[0072] (3) P-type doping is performed in the preset region 9 of the N-type epitaxial layer 40, and a second N-type doping region 4 is obtained. A first oxide layer 5 is deposited, wherein the P-type doped impurity is B (boron) and the doping concentration is 1E10 atom / cm 3 , the temperature is 700°C, and the thickness of the first oxide layer 5 is 500Å;

[0073] (4) depositing a first polysilicon 6 on the first oxide layer 5, wherein the width of the first polysilicon 6 deposited on the first oxide layer 5 is consistent with the first oxide layer 5, and the thickness of the first polysilicon 6 is 0.6 μm;

[0074] (5) Based on the P-type doped preset region 9, N-type doping is performed to obtain a first N-type doped region 2, and finally two first N-type doped regions 2 and a P-type well region 3 are formed on both sides of the trench etched on the N-type epitaxial layer 40;

[0075] Specifically, the P-type well region 3 includes a first sub-region 31 and a second sub-region 32 extending from the first sub-region 31 toward a direction away from the substrate. The two first N-type doping regions 2 are symmetrical about the second sub-region 32. The doping concentration of the first N-type doping region 2 is greater than the doping concentration of the second N-type doping region 4. The N-type doped impurity is P (phosphorus) with a doping concentration of 1E13 atom / cm 3 , the temperature is 800℃.

[0076] Among them, the first polysilicon 6 forms a first gate, and constitutes a first switch with the corresponding two first N-type doped regions 2 and P-type well region 3. The second polysilicon 8 forms a second gate. As a second switch, the thickness of the first oxide layer 5 is greater than the thickness of the second oxide layer 7. The first N-type doped region 2 away from the groove is used to be electrically connected to the source, the first gate and the second gate are electrically connected to the gate respectively, and the substrate is electrically connected to the drain.

[0077] On the basis of the above, an oxide layer is deposited as a dielectric layer as a whole, and then CT (through hole) etching is performed, and finally metal aluminum is deposited to form the electrode of the MOS transistor.

[0078] Example 2

[0079] Embodiment 2 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Embodiment 1 in that the thickness of the second oxide layer is 150Å.

[0080] Example 3

[0081] Embodiment 3 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Embodiment 1 in that the thickness of the first oxide layer is 800Å.

[0082] Example 4

[0083] Embodiment 4 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Embodiment 1 in that the thickness of the first oxide layer is 1200Å, and the thickness of the second oxide layer is 80Å.

[0084] Example 5

[0085] Embodiment 5 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Embodiment 1 in that the thickness of the first oxide layer is 1200Å.

[0086] Example 6

[0087] Embodiment 6 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Embodiment 1 in that the thickness of the first oxide layer is 1200Å, and the thickness of the second oxide layer is 150Å.

[0088] Comparative Example 1 Comparative Example 1 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Example 1 in that the thickness of the second oxide layer is 300 Å.

[0089] Comparative Example 2

[0090] Comparative Example 2 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Example 1 in that the thickness of the first oxide layer is 800Å, and the thickness of the second oxide layer is 300Å.

[0091] Comparative Example 3

[0092] Comparative Example 3 of the present invention provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Example 1 in that the thickness of the first oxide layer is 800Å, and the thickness of the second oxide layer is 500Å.

[0093] Prior art

[0094] The prior art provides a method for preparing a MOS transistor, which is different from the method for preparing a MOS transistor in Example 1 in that it only contains a single vertical channel, that is, a groove, an oxide layer deposited on the surface of the groove, and polysilicon deposited on the oxide layer are prepared, and the epitaxial layer on at least one side of the groove is doped to form an NPN structure.

[0095] The MOS transistors prepared by Examples 1 to 6, Comparative Examples 1 to 3 and the MOS transistor preparation method in the prior art were tested, and the specific results are as follows:

[0096]

[0097] Among them, the turn-on voltage 1 refers to the voltage associated with the thick oxide layer, that is, the voltage associated with the first oxide layer, and the turn-on voltage 2 refers to the voltage associated with the thin oxide layer, that is, the voltage associated with the second oxide layer. They are in a series relationship, and the entire device will only be turned on if both are turned on at the same time. Specifically, the advantage of series connection is that it can prevent leakage after one of them is turned on by mistake, and it will only be turned on if both are turned on at the same time, and the large turn-on voltage is to prevent mistaken turning on. It can be found that the resistance fluctuation of the MOS transistor prepared in the embodiment of the present invention is significantly smaller than the resistance fluctuation of the MOS transistor in the prior art. In addition, the greater the difference in thickness between the first oxide layer and the second oxide layer, the greater the difference between the turn-on voltages; the thinner the second oxide layer, the smaller the resistance fluctuation, but the turn-on voltage will also be smaller.

[0098] In summary, a MOS transistor and a preparation method thereof in an embodiment of the present invention, when the MOS transistor is a Trench NMOS transistor, the Trench NMOS transistor includes a substrate and an epitaxial layer deposited on the substrate, the epitaxial layer is provided with a trench, two first N-type doped regions and a P-type well region are arranged on both sides of the trench, the P-type well region includes a first sub-region and a second sub-region extending from the first sub-region toward a direction away from the substrate, the two first N-type doped regions are symmetrical about the second sub-region, the region between the P-type well region and the substrate is the second N-type doped region, and the doping concentration of the first N-type doped region is greater than the doping concentration of the second N-type doped region; the two first N-type doped regions on both sides of the trench and the end of the P-type well region away from the substrate are sequentially deposited with a first oxide layer and a first polysilicon; A second oxide layer is deposited on the surface of the groove, and the groove formed by the second oxide layer is filled with a second polysilicon; wherein the first polysilicon forms a first gate, and forms a first switch with the corresponding two first N-type doped regions and the P-type well region, and the second polysilicon forms a second gate. As the second switch, the thickness of the first oxide layer is greater than the thickness of the second oxide layer, and the first N-type doped region away from the groove is used to be electrically connected to the source, the first gate and the second gate are electrically connected to the gate respectively, and the substrate is electrically connected to the drain, so that the resistance of the MOS transistor is stable when the gate voltage fluctuates, and the MOS transistor can have a large turn-on voltage.

[0099] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A MOS transistor, characterized in that: When the MOS transistor is a Trench NMOS transistor, the Trench NMOS transistor includes a substrate and an epitaxial layer deposited on the substrate, the epitaxial layer is provided with a trench, two first N-type doping regions and a P-type well region are provided on both sides of the trench, the P-type well region includes a first sub-region and a second sub-region extending from the first sub-region in a direction away from the substrate, the two first N-type doping regions are symmetrical about the second sub-region, the region between the P-type well region and the substrate is a second N-type doping region, and the doping concentration of the first N-type doping region is greater than the doping concentration of the second N-type doping region; The two first N-type doping regions on both sides of the groove and the end of the P-type well region away from the substrate are sequentially deposited with a first oxide layer and a first polysilicon, and the first N-type doping region closer to the groove among the two first N-type doping regions is in contact with the second oxide layer on the surface of the groove; A second oxide layer is deposited on the surface of the groove, and the groove formed by the second oxide layer is filled with second polysilicon; The first polysilicon forms a first gate, and forms a first switch with the corresponding two first N-type doped regions and the P-type well region; the second polysilicon forms a second gate, and serves as a second switch; the thickness of the first oxide layer is greater than the thickness of the second oxide layer; the first N-type doped region away from the trench is used to be electrically connected to the source; the first gate and the second gate are electrically connected to the gate, respectively; and the substrate is electrically connected to the drain; Alternatively, when the MOS transistor is a Trench PMOS transistor, all doping types are opposite to those of the Trench NMOS transistor. Specifically, the Trench PMOS transistor includes a substrate and an epitaxial layer deposited on the substrate, the epitaxial layer is provided with a trench, two first P-type doping regions and an N-type well region are arranged on both sides of the trench, the N-type well region includes a third sub-region and a fourth sub-region extending from the third sub-region in a direction away from the substrate, the two first P-type doping regions are symmetrical about the fourth sub-region, the region between the N-type well region and the substrate is a second P-type doping region, and the doping concentration of the first P-type doping region is greater than the doping concentration of the second P-type doping region; The first oxide layer and the first polysilicon are deposited in sequence on the two first P-type doping regions on both sides of the groove and the end of the N-type well region away from the substrate, and the first P-type doping region closer to the groove among the two first P-type doping regions is in contact with the second oxide layer on the surface of the groove; A second oxide layer is deposited on the surface of the groove, and the groove formed by the second oxide layer is filled with second polysilicon; Among them, the first polysilicon forms a first gate, and constitutes a first switch with the corresponding two first P-type doped regions and the N-type well region. The second polysilicon forms a second gate as a second switch. The thickness of the first oxide layer is greater than the thickness of the second oxide layer. The first P-type doped region away from the groove is used to be electrically connected to the source. The first gate and the second gate are electrically connected to the gate respectively, and the substrate is electrically connected to the drain.

2. The MOS transistor according to claim 1, characterized in that The depth of the trenches formed in the epitaxial layer is 1 μm to 1.5 μm.

3. The MOS transistor according to claim 2, characterized in that: The thickness of the first oxide layer is 500Å~1200Å.

4. The MOS transistor according to claim 3, characterized in that: The thickness of the second oxide layer is 80Å~150Å.

5. The MOS transistor according to claim 4, characterized in that: The impurity of the P-type well region is B, and the doping concentration is 1E10 atom / cm 3 ~1E14 atoms / cm 3 , the temperature is 700℃~1000℃.

6. The MOS transistor according to claim 5, characterized in that The impurity of the first N-type doping region is P, and the doping concentration is 1E13atom / cm 3 ~1E17atom / cm 3 , the temperature is 800℃~1100℃.

7. The MOS transistor according to claim 6, characterized in that: The surface of the second polysilicon is 0.2 μm to 0.5 μm lower than the surface of the second oxide layer.

8. A method for preparing a MOS transistor, characterized in that: Used to prepare the MOS transistor according to any one of claims 1 to 7, when the MOS transistor is a Trench NMOS transistor, the preparation method comprises: Providing a substrate, and depositing an epitaxial layer on the substrate, wherein the epitaxial layer is an N-type epitaxial layer; Etching a groove on the N-type epitaxial layer and depositing a second oxide layer on the surface, then filling the groove formed by the second oxide layer with polysilicon, and then performing CMP grinding and etching to obtain second polysilicon; Performing P-type doping in a preset area of ​​the N-type epitaxial layer and depositing a first oxide layer; depositing first polysilicon on the first oxide layer; On the basis of the preset P-type doped area, N-type doping is performed to obtain a first N-type doped area, and finally two first N-type doped areas and a P-type well area are formed on both sides of the groove etched on the N-type epitaxial layer, the P-type well area includes a first sub-area and a second sub-area extending from the first sub-area in a direction away from the substrate, the two first N-type doped areas are symmetrical about the second sub-area, and the doping concentration of the first N-type doped area is greater than the doping concentration of the N-type epitaxial layer; The first polysilicon forms a first gate, and forms a first switch with the corresponding two first N-type doped regions and the P-type well region; the second polysilicon forms a second gate, and serves as a second switch; the thickness of the first oxide layer is greater than the thickness of the second oxide layer; the first N-type doped region away from the trench is used to be electrically connected to the source; the first gate and the second gate are electrically connected to the gate, respectively; and the substrate is electrically connected to the drain; Alternatively, when the MOS transistor is a Trench PMOS transistor, all doping types are controlled opposite to those of a Trench NMOS transistor.

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